From 68b7f550ba140d275c6f9bb26c2186069354be24 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 12 May 2008 09:00:40 -0400 Subject: Radeon IGP: wrap MCIND access first step in merging rs4xx/rs6xx gart setup --- shared-core/radeon_drv.h | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) (limited to 'shared-core/radeon_drv.h') diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 639a1398..452583ef 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -1145,14 +1145,6 @@ do { \ RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ } while (0) -#define RADEON_WRITE_IGPGART( addr, val ) \ -do { \ - RADEON_WRITE( RS400_NB_MC_INDEX, \ - ((addr) & 0x7f) | RS400_NB_MC_IND_WR_EN); \ - RADEON_WRITE( RS400_NB_MC_DATA, (val) ); \ - RADEON_WRITE( RS400_NB_MC_INDEX, 0x7f ); \ -} while (0) - #define RADEON_WRITE_PCIE( addr, val ) \ do { \ RADEON_WRITE8( RADEON_PCIE_INDEX, \ @@ -1160,12 +1152,20 @@ do { \ RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ } while (0) -#define RADEON_WRITE_MCIND( addr, val ) \ - do { \ - RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ - RADEON_WRITE(R520_MC_IND_DATA, (val)); \ - RADEON_WRITE(R520_MC_IND_INDEX, 0); \ - } while (0) +#define R500_WRITE_MCIND( addr, val ) \ +do { \ + RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ + RADEON_WRITE(R520_MC_IND_DATA, (val)); \ + RADEON_WRITE(R520_MC_IND_INDEX, 0); \ +} while (0) + +#define RS400_WRITE_MCIND( addr, val ) \ +do { \ + RADEON_WRITE( RS400_NB_MC_INDEX, \ + ((addr) & 0x7f) | RS400_NB_MC_IND_WR_EN); \ + RADEON_WRITE( RS400_NB_MC_DATA, (val) ); \ + RADEON_WRITE( RS400_NB_MC_INDEX, 0x7f ); \ +} while (0) #define RS690_WRITE_MCIND( addr, val ) \ do { \ @@ -1174,6 +1174,14 @@ do { \ RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ } while (0) +#define IGP_WRITE_MCIND( addr, val ) \ +do { \ + if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \ + RS690_WRITE_MCIND( addr, val ); \ + else \ + RS400_WRITE_MCIND( addr, val ); \ +} while (0) + #define CP_PACKET0( reg, n ) \ (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) #define CP_PACKET0_TABLE( reg, n ) \ -- cgit v1.2.3