From 4b98f6d74ffb119174237d30356ed3e2724b27da Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 6 Oct 2008 03:08:27 -0400 Subject: radeon: fix bus master enabled bits on newer asics --- shared-core/radeon_drv.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'shared-core/radeon_drv.h') diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 5e188bfc..f3b65310 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -123,6 +123,7 @@ enum radeon_family { CHIP_RV350, CHIP_RV380, CHIP_R420, + CHIP_R423, CHIP_RV410, CHIP_RS400, CHIP_RS480, @@ -432,7 +433,20 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, # define RADEON_SCISSOR_2_ENABLE (1 << 30) #define RADEON_BUS_CNTL 0x0030 +/* r1xx, r2xx, r300, r(v)350, r420, rs480 */ # define RADEON_BUS_MASTER_DIS (1 << 6) +/* rs400, rs690, rs740 */ +# define RS400_BUS_MASTER_DIS (1 << 14) +# define RS400_MSI_REARM (1 << 20) + +#define RV370_BUS_CNTL 0x004c +/* rv370, rv380, rv410, r423, r430, r480, r5xx */ +# define RV370_PMI_BM_DIS (1 << 5) +# define RV370_PMI_INT_DIS (1 << 6) + +#define RADEON_MSI_REARM_EN 0x0160 +/* rv370, rv380, rv410, r423, r430, r480, r5xx */ +# define RADEON_MSI_REARM_EN (1 << 0) #define RADEON_CLOCK_CNTL_DATA 0x000c # define RADEON_PLL_WR_EN (1 << 7) @@ -912,6 +926,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, #define RADEON_AIC_CNTL 0x01d0 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) +# define RS480_MSI_REARM (1 << 3) #define RADEON_AIC_STAT 0x01d4 #define RADEON_AIC_PT_BASE 0x01d8 #define RADEON_AIC_LO_ADDR 0x01dc -- cgit v1.2.3