From a70f8e0ab265cc4a26ed2f9e92ab0618bd920a93 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Apr 2007 21:52:59 +1000 Subject: radeon: add support for reverse engineered xpress200m The IGPGART setup code was traced using mmio-trace on fglrx by myself and Phillip Ezolt on dri-devel. This code doesn't let the 3D driver work properly as the card has no vertex shader support. Thanks to Matthew Garrett + Ubuntu for providing me some hardware to do this work on. --- shared-core/radeon_drv.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'shared-core/radeon_drv.h') diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 3e56af30..646b2c56 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -145,6 +145,7 @@ enum radeon_chip_flags { RADEON_IS_PCIE = 0x00200000UL, RADEON_NEW_MEMMAP = 0x00400000UL, RADEON_IS_PCI = 0x00800000UL, + RADEON_IS_IGPGART = 0x01000000UL, }; #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ @@ -432,6 +433,16 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, #define RADEON_PCIE_TX_GART_END_LO 0x16 #define RADEON_PCIE_TX_GART_END_HI 0x17 +#define RADEON_IGPGART_INDEX 0x168 +#define RADEON_IGPGART_DATA 0x16c +#define RADEON_IGPGART_UNK_18 0x18 +#define RADEON_IGPGART_CTRL 0x2b +#define RADEON_IGPGART_BASE_ADDR 0x2c +#define RADEON_IGPGART_UNK_2E 0x2e +#define RADEON_IGPGART_UNK_38 0x38 +#define RADEON_IGPGART_UNK_39 0x39 + + #define RADEON_MPP_TB_CONFIG 0x01c0 #define RADEON_MEM_CNTL 0x0140 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 @@ -994,6 +1005,14 @@ do { \ RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ } while (0) +#define RADEON_WRITE_IGPGART( addr, val ) \ +do { \ + RADEON_WRITE( RADEON_IGPGART_INDEX, \ + ((addr) & 0x7f) | (1 << 8)); \ + RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \ + RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \ +} while (0) + #define RADEON_WRITE_PCIE( addr, val ) \ do { \ RADEON_WRITE8( RADEON_PCIE_INDEX, \ -- cgit v1.2.3 From 29f8fe80469a161c89c1a690ae2b62b3c21e4794 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Apr 2007 22:00:34 +1000 Subject: radeon: bump version for IGPGART support --- shared-core/radeon_drv.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'shared-core/radeon_drv.h') diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 646b2c56..950f6828 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -96,10 +96,11 @@ * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, * new packet type) * 1.26- Add support for variable size PCI(E) gart aperture + * 1.27- Add support for IGP GART */ #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 26 +#define DRIVER_MINOR 27 #define DRIVER_PATCHLEVEL 0 /* -- cgit v1.2.3 From 059b5d90770e32ba3d6d9a62acf74b352de7f421 Mon Sep 17 00:00:00 2001 From: Oliver McFadden Date: Mon, 9 Apr 2007 23:23:40 +0000 Subject: rs480: Renamed some unknown registers. See dri-devel list. --- shared-core/radeon_drv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core/radeon_drv.h') diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 950f6828..00646c8f 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -439,8 +439,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, #define RADEON_IGPGART_UNK_18 0x18 #define RADEON_IGPGART_CTRL 0x2b #define RADEON_IGPGART_BASE_ADDR 0x2c -#define RADEON_IGPGART_UNK_2E 0x2e -#define RADEON_IGPGART_UNK_38 0x38 +#define RADEON_IGPGART_FLUSH 0x2e +#define RADEON_IGPGART_ENABLE 0x38 #define RADEON_IGPGART_UNK_39 0x39 -- cgit v1.2.3 From ca1cd3257c7c41821788ca45d45e51065f436803 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Sun, 29 Apr 2007 12:17:57 +0200 Subject: radeon: Don't mess up page flipping when a file descriptor is closed. There can still be other contexts that may use page flipping later on, so don't just unilaterally 'clean it up', which could lead to the wrong page being displayed, e.g. when running 3D apps with a GLX compositing manager such as compiz using page flipping. --- shared-core/radeon_drv.h | 1 - 1 file changed, 1 deletion(-) (limited to 'shared-core/radeon_drv.h') diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 00646c8f..4a36ea70 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -245,7 +245,6 @@ typedef struct drm_radeon_private { int do_boxes; int page_flipping; - int current_page; u32 color_fmt; unsigned int front_offset; -- cgit v1.2.3 From 4e9d215bdfe72588cbacdb17ab9b60a42a43aefb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 3 Jun 2007 16:28:21 +1000 Subject: radeon: add support for vblank on crtc2 This add support for CRTC2 vblank on radeon similiar to the i915 support --- shared-core/radeon_drv.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'shared-core/radeon_drv.h') diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 4a36ea70..f1d9ca9e 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -97,10 +97,11 @@ * new packet type) * 1.26- Add support for variable size PCI(E) gart aperture * 1.27- Add support for IGP GART + * 1.28- Add support for VBL on CRTC2 */ #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 27 +#define DRIVER_MINOR 28 #define DRIVER_PATCHLEVEL 0 /* @@ -279,6 +280,9 @@ typedef struct drm_radeon_private { /* SW interrupt */ wait_queue_head_t swi_queue; atomic_t swi_emitted; + int vblank_crtc; + uint32_t irq_enable_reg; + int irq_enabled; struct radeon_surface surfaces[RADEON_MAX_SURFACES]; struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; @@ -355,10 +359,14 @@ extern int radeon_irq_wait(DRM_IOCTL_ARGS); extern void radeon_do_release(drm_device_t * dev); extern int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence); +extern int radeon_driver_vblank_wait2(drm_device_t * dev, + unsigned int *sequence); extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); extern void radeon_driver_irq_preinstall(drm_device_t * dev); extern void radeon_driver_irq_postinstall(drm_device_t * dev); extern void radeon_driver_irq_uninstall(drm_device_t * dev); +extern int radeon_vblank_crtc_get(drm_device_t *dev); +extern int radeon_vblank_crtc_set(drm_device_t *dev, int64_t value); extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); extern int radeon_driver_unload(struct drm_device *dev); @@ -495,12 +503,15 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, #define RADEON_GEN_INT_CNTL 0x0040 # define RADEON_CRTC_VBLANK_MASK (1 << 0) +# define RADEON_CRTC2_VBLANK_MASK (1 << 9) # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) # define RADEON_SW_INT_ENABLE (1 << 25) #define RADEON_GEN_INT_STATUS 0x0044 # define RADEON_CRTC_VBLANK_STAT (1 << 0) # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) +# define RADEON_CRTC2_VBLANK_STAT (1 << 9) +# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) # define RADEON_SW_INT_TEST (1 << 25) # define RADEON_SW_INT_TEST_ACK (1 << 25) -- cgit v1.2.3