From a12cbf8aa5cf21d30bd2c798ff059cb1ba92b382 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 30 May 2008 18:20:01 -0400 Subject: RADEON: fix typo in last commit --- shared-core/radeon_cp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core/radeon_cp.c') diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 819a61ae..5675fda6 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -127,7 +127,7 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); } else { - RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_base_lo); + RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); } -- cgit v1.2.3 From 6905c7a29d2a3bc0e605a09b98ac02a4a50893d0 Mon Sep 17 00:00:00 2001 From: Dennis Kasprzyk Date: Thu, 5 Jun 2008 17:08:44 +0200 Subject: radeon: Restore software interrupt on resume. Fixes performance drop after suspend/resume on some systems. --- shared-core/radeon_cp.c | 1 + 1 file changed, 1 insertion(+) (limited to 'shared-core/radeon_cp.c') diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 5675fda6..75b1dc55 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -1296,6 +1296,7 @@ static int radeon_do_resume_cp(struct drm_device * dev) radeon_cp_init_ring_buffer(dev, dev_priv); radeon_do_engine_reset(dev); + radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); DRM_DEBUG("radeon_do_resume_cp() complete\n"); -- cgit v1.2.3 From f6982b54c96bc871df94d01abad72a501e87aa65 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 9 Jun 2008 16:28:35 -0400 Subject: RADEON: switch IGP gart to use radeon_write_agp_base() --- shared-core/radeon_cp.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'shared-core/radeon_cp.c') diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 75b1dc55..696f12be 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -126,6 +126,9 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); + } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) { + RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); + RADEON_WRITE(RS480_AGP_BASE_2, 0); } else { RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) @@ -741,14 +744,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS)); - if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { - IGP_WRITE_MCIND(RS690_MC_AGP_BASE, - (unsigned int)dev_priv->gart_vm_start); - IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0); - } else { - RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start); - RADEON_WRITE(RS480_AGP_BASE_2, 0); - } + radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); dev_priv->gart_size = 32*1024*1024; temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & -- cgit v1.2.3 From 4b8aecbde8e62af5370d5401d49a8ab8d089fe8e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 9 Jun 2008 16:58:06 -0400 Subject: RADEON: Add untested support for RS400 chips GART setup appears to work the same as RS480 chips. Also RC4xx chips are actually RS400 based, not RS480 based. --- shared-core/radeon_cp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'shared-core/radeon_cp.c') diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 696f12be..afe850c1 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -126,9 +126,10 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); - } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) { + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); - RADEON_WRITE(RS480_AGP_BASE_2, 0); + RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi); } else { RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) @@ -355,6 +356,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { DRM_INFO("Loading R300 Microcode\n"); for (i = 0; i < 256; i++) { -- cgit v1.2.3 From a07c82183abdcde9777a456d45b7ae741ddfd44c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 11 Jun 2008 18:25:47 -0400 Subject: RADEON: use DSTCACHE_CTLSTAT rather than RB2D_DSTCACHE_CTLSTAT According to the hw guys, you should use DSTCACHE_CTLSTAT to flush the 2D dst cache rather than RB2D_DSTCACHE_CTLSTAT. --- shared-core/radeon_cp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'shared-core/radeon_cp.c') diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index afe850c1..7317d184 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -204,12 +204,12 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp); /* 2D */ - tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT); + tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT); tmp |= RADEON_RB3D_DC_FLUSH_ALL; - RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); + RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp); for (i = 0; i < dev_priv->usec_timeout; i++) { - if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT) + if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY)) { return 0; } -- cgit v1.2.3 From 1aafbb83d97ccc78b78d5cbd311f1239a3dad11e Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Fri, 13 Jun 2008 09:54:05 +0200 Subject: radeon: r345xx fixe hard lockup This patch should fixe hard lockup and convert them in softlockup (ie you can ssh the box but the gpu is busted and we are waiting in loop for it to come back to reason). --- shared-core/radeon_cp.c | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-) (limited to 'shared-core/radeon_cp.c') diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 7317d184..ec914df1 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -39,6 +39,7 @@ #define RADEON_FIFO_DEBUG 0 static int radeon_do_cleanup_cp(struct drm_device * dev); +static void radeon_do_cp_start(drm_radeon_private_t * dev_priv); static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) { @@ -198,23 +199,8 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) DRM_UDELAY(1); } } else { - /* 3D */ - tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT); - tmp |= RADEON_RB3D_DC_FLUSH_ALL; - RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp); - - /* 2D */ - tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT); - tmp |= RADEON_RB3D_DC_FLUSH_ALL; - RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp); - - for (i = 0; i < dev_priv->usec_timeout; i++) { - if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT) - & RADEON_RB3D_DC_BUSY)) { - return 0; - } - DRM_UDELAY(1); - } + /* don't flush or purge cache here or lockup */ + return 0; } #if RADEON_FIFO_DEBUG @@ -237,6 +223,9 @@ static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) return 0; DRM_UDELAY(1); } + DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", + RADEON_READ(RADEON_RBBM_STATUS), + RADEON_READ(R300_VAP_CNTL_STATUS)); #if RADEON_FIFO_DEBUG DRM_ERROR("failed!\n"); @@ -263,6 +252,9 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) } DRM_UDELAY(1); } + DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", + RADEON_READ(RADEON_RBBM_STATUS), + RADEON_READ(R300_VAP_CNTL_STATUS)); #if RADEON_FIFO_DEBUG DRM_ERROR("failed!\n"); @@ -445,14 +437,20 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) dev_priv->cp_running = 1; - BEGIN_RING(6); - + BEGIN_RING(8); + /* isync can only be written through cp on r5xx write it here */ + OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); + OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | + RADEON_ISYNC_ANY3D_IDLE2D | + RADEON_ISYNC_CPSCRATCH_IDLEGUI | + RADEON_ISYNC_CPSCRATCH_IDLEGUI); RADEON_PURGE_CACHE(); RADEON_PURGE_ZCACHE(); RADEON_WAIT_UNTIL_IDLE(); - ADVANCE_RING(); COMMIT_RING(); + + dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; } /* Reset the Command Processor. This will not flush any pending -- cgit v1.2.3 From 59112c9e521d1543e8b76635ef223e7f29d35e6a Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sun, 15 Jun 2008 20:18:29 +0200 Subject: radeon: *really* fix screen corruption thanks to Lukasz Krotowski --- shared-core/radeon_cp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core/radeon_cp.c') diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index ec914df1..9b1ea855 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -442,7 +442,7 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | RADEON_ISYNC_ANY3D_IDLE2D | - RADEON_ISYNC_CPSCRATCH_IDLEGUI | + RADEON_ISYNC_WAIT_IDLEGUI | RADEON_ISYNC_CPSCRATCH_IDLEGUI); RADEON_PURGE_CACHE(); RADEON_PURGE_ZCACHE(); -- cgit v1.2.3 From abdd523c759a5e19e733e3b544c2f1bcaa7a0b9a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 15 Jul 2008 16:18:22 +1000 Subject: drm: add fix for PAT on radeon with 2.6.26 --- shared-core/radeon_cp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core/radeon_cp.c') diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 9b1ea855..9bfda005 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -1158,7 +1158,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) dev_priv->gart_info.mapping.size = dev_priv->gart_info.table_size; - drm_core_ioremap(&dev_priv->gart_info.mapping, dev); + drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); dev_priv->gart_info.addr = dev_priv->gart_info.mapping.handle; -- cgit v1.2.3 From 7cfdba2b30e40efc688f1704bd4f4141dc6f9a6c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 18 Jul 2008 14:30:57 +1000 Subject: radeon: remove microcode version --- shared-core/radeon_cp.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) (limited to 'shared-core/radeon_cp.c') diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 9bfda005..ae31e969 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -893,17 +893,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) */ dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; - switch(init->func) { - case RADEON_INIT_R200_CP: - dev_priv->microcode_version = UCODE_R200; - break; - case RADEON_INIT_R300_CP: - dev_priv->microcode_version = UCODE_R300; - break; - default: - dev_priv->microcode_version = UCODE_R100; - } - dev_priv->do_boxes = 0; dev_priv->cp_mode = init->cp_mode; @@ -951,8 +940,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) */ dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | (dev_priv->color_fmt << 10) | - (dev_priv->microcode_version == - UCODE_R100 ? RADEON_ZBLOCK16 : 0)); + (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0)); dev_priv->depth_clear.rb3d_zstencilcntl = (dev_priv->depth_fmt | @@ -1731,6 +1719,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags) break; } + dev_priv->chip_family = flags & RADEON_FAMILY_MASK; if (drm_device_is_agp(dev)) dev_priv->flags |= RADEON_IS_AGP; else if (drm_device_is_pcie(dev)) -- cgit v1.2.3