From c806bba4665bb369168ee0b453fa28e2e0bf2a5d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 5 Jul 2007 00:12:33 +1000 Subject: nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80. --- shared-core/nv50_fifo.c | 259 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 255 insertions(+), 4 deletions(-) (limited to 'shared-core/nv50_fifo.c') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index e5d37949..d4c3ca87 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -28,55 +28,306 @@ #include "drm.h" #include "nouveau_drv.h" +typedef struct { + nouveau_gpuobj_ref_t *thingo; + nouveau_gpuobj_ref_t *dummyctx; +} nv50_fifo_priv; + +#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) + +static void +nv50_fifo_init_thingo(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; + nouveau_gpuobj_ref_t *thingo = priv->thingo; + int i, fi=2; + + DRM_DEBUG("\n"); + + INSTANCE_WR(thingo->gpuobj, 0, 0x7e); + INSTANCE_WR(thingo->gpuobj, 1, 0x7e); + for (i = 0; i fifos[i]) { + INSTANCE_WR(thingo->gpuobj, fi, i); + fi++; + } + } + + NV_WRITE(0x32f4, thingo->instance >> 12); + NV_WRITE(0x32ec, fi); + NV_WRITE(0x2500, 0x101); +} + +static int +nv50_fifo_channel_enable(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + + DRM_DEBUG("ch%d\n", channel); + + if (IS_G80) { + if (!chan->ramin) + return DRM_ERR(EINVAL); + + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), + (chan->ramin->instance >> 12) | + NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); + } else { + if (!chan->ramfc) + return DRM_ERR(EINVAL); + + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), + (chan->ramfc->instance >> 8) | + NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); + } + + nv50_fifo_init_thingo(dev); + return 0; +} + +static void +nv50_fifo_channel_disable(drm_device_t *dev, int channel, int nt) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("ch%d, nt=%d\n", channel, nt); + + if (IS_G80) { + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), + NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80); + } else { + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), + NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84); + } + + if (!nt) nv50_fifo_init_thingo(dev); +} + static void nv50_fifo_init_reset(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; uint32_t pmc_e; + DRM_DEBUG("\n"); + pmc_e = NV_READ(NV03_PMC_ENABLE); NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PFIFO); pmc_e = NV_READ(NV03_PMC_ENABLE); NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PFIFO); } +static void +nv50_fifo_init_context_table(drm_device_t *dev) +{ + int i; + + DRM_DEBUG("\n"); + + for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++) + nv50_fifo_channel_disable(dev, i, 1); + nv50_fifo_init_thingo(dev); +} + +static void +nv50_fifo_init_regs__nv(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("\n"); + + NV_WRITE(0x250c, 0x6f3cfc34); +} + +static int +nv50_fifo_init_regs(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; + int ret; + + DRM_DEBUG("\n"); + + if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, 0x1000, + 0x1000, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ZERO_FREE, + &priv->dummyctx))) + return ret; + + NV_WRITE(0x2500, 0); + NV_WRITE(0x3250, 0); + NV_WRITE(0x3220, 0); + NV_WRITE(0x3204, 0); + NV_WRITE(0x3210, 0); + NV_WRITE(0x3270, 0); + + if (IS_G80) { + NV_WRITE(0x2600, (priv->dummyctx->instance>>8) | (1<<31)); + NV_WRITE(0x27fc, (priv->dummyctx->instance>>8) | (1<<31)); + } else { + NV_WRITE(0x2600, (priv->dummyctx->instance>>12) | (1<<31)); + NV_WRITE(0x27fc, (priv->dummyctx->instance>>12) | (1<<31)); + } + + return 0; +} + int nv50_fifo_init(drm_device_t *dev) { + drm_nouveau_private_t *dev_priv = dev->dev_private; + nv50_fifo_priv *priv; + int ret; + + DRM_DEBUG("\n"); + + priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); + if (!priv) + return DRM_ERR(ENOMEM); + dev_priv->Engine.fifo.priv = priv; + nv50_fifo_init_reset(dev); - DRM_ERROR("stub!\n"); + if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, (128+2)*4, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, + &priv->thingo))) { + DRM_ERROR("error creating thingo: %d\n", ret); + return ret; + } + nv50_fifo_init_context_table(dev); + + nv50_fifo_init_regs__nv(dev); + if ((ret = nv50_fifo_init_regs(dev))) + return ret; + return 0; } void nv50_fifo_takedown(drm_device_t *dev) { - DRM_ERROR("stub!\n"); + drm_nouveau_private_t *dev_priv = dev->dev_private; + nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; + + DRM_DEBUG("\n"); + + if (!priv) + return; + + nouveau_gpuobj_ref_del(dev, &priv->thingo); + nouveau_gpuobj_ref_del(dev, &priv->dummyctx); + + dev_priv->Engine.fifo.priv = NULL; + drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); } int nv50_fifo_create_context(drm_device_t *dev, int channel) { - DRM_ERROR("stub!\n"); + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + nouveau_gpuobj_t *ramfc = NULL; + int ret; + + DRM_DEBUG("ch%d\n", channel); + + if (IS_G80) { + uint32_t ramfc_offset; + ramfc_offset = chan->ramin->gpuobj->im_pramin->start + 0x1000; + if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, 0x100, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ZERO_FREE, + &ramfc, &chan->ramfc))) + return ret; + } else { + if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, 0x100, + 256, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ZERO_FREE, + &chan->ramfc))) + return ret; + ramfc = chan->ramfc->gpuobj; + } + + INSTANCE_WR(ramfc, 0x48/4, chan->pushbuf->instance >> 4); + INSTANCE_WR(ramfc, 0x80/4, (0xc << 24) | (chan->ramht->instance >> 4)); + INSTANCE_WR(ramfc, 0x3c/4, 0x000f0078); /* fetch? */ + INSTANCE_WR(ramfc, 0x44/4, 0x2101ffff); + INSTANCE_WR(ramfc, 0x60/4, 0x7fffffff); + INSTANCE_WR(ramfc, 0x10/4, 0x00000000); + INSTANCE_WR(ramfc, 0x08/4, 0x00000000); + INSTANCE_WR(ramfc, 0x40/4, 0x00000000); + INSTANCE_WR(ramfc, 0x50/4, 0x2039b2e0); + INSTANCE_WR(ramfc, 0x54/4, 0x000f0000); + INSTANCE_WR(ramfc, 0x7c/4, 0x30000001); + INSTANCE_WR(ramfc, 0x78/4, 0x00000000); + INSTANCE_WR(ramfc, 0x4c/4, 0x00007fff); + + if (!IS_G80) { + INSTANCE_WR(chan->ramin->gpuobj, 0, channel); + INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance); + + INSTANCE_WR(ramfc, 0x88/4, 0x3d520); /* some vram addy >> 10 */ + INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12); + } + + if ((ret = nv50_fifo_channel_enable(dev, channel))) { + DRM_ERROR("error enabling ch%d: %d\n", channel, ret); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); + return ret; + } + return 0; } void nv50_fifo_destroy_context(drm_device_t *dev, int channel) { + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + + DRM_DEBUG("ch%d\n", channel); + + nv50_fifo_channel_disable(dev, channel, 0); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int nv50_fifo_load_context(drm_device_t *dev, int channel) { - DRM_ERROR("stub!\n"); + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + nouveau_gpuobj_t *ramfc = chan->ramfc->gpuobj; + + DRM_DEBUG("ch%d\n", channel); + + /*XXX: incomplete, only touches the regs that NV does */ + + NV_WRITE(0x3244, 0); + NV_WRITE(0x3240, 0); + + NV_WRITE(0x3224, INSTANCE_RD(ramfc, 0x3c/4)); + NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, INSTANCE_RD(ramfc, 0x48/4)); + NV_WRITE(0x3234, INSTANCE_RD(ramfc, 0x4c/4)); + NV_WRITE(0x3254, 1); + NV_WRITE(NV03_PFIFO_RAMHT, INSTANCE_RD(ramfc, 0x80/4)); + + if (!IS_G80) { + NV_WRITE(0x340c, INSTANCE_RD(ramfc, 0x88/4)); + NV_WRITE(0x3410, INSTANCE_RD(ramfc, 0x98/4)); + } + + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, channel | (1<<16)); return 0; } int nv50_fifo_save_context(drm_device_t *dev, int channel) { + DRM_DEBUG("ch%d\n", channel); DRM_ERROR("stub!\n"); return 0; } -- cgit v1.2.3 From 5ccadac9e3b1beb8ac0177c7a39862094fe3b6de Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 11 Jul 2007 14:22:59 +1000 Subject: nouveau/nv50: G80 fixes. Again, no hardware, so no idea if it'll even work yet. I understand how the PRAMIN setup works now, un-hardcoding stuff will come "RealSoonNow(tm)". --- shared-core/nv50_fifo.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'shared-core/nv50_fifo.c') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index d4c3ca87..ee1fb887 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -235,8 +235,7 @@ nv50_fifo_create_context(drm_device_t *dev, int channel) DRM_DEBUG("ch%d\n", channel); if (IS_G80) { - uint32_t ramfc_offset; - ramfc_offset = chan->ramin->gpuobj->im_pramin->start + 0x1000; + uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, 0x100, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, -- cgit v1.2.3 From 0029713451af6f5f216079775ff77cae9b423c0e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 13 Jul 2007 15:09:31 +1000 Subject: nouveau: nuke internal typedefs, and drm_device_t use. --- shared-core/nv50_fifo.c | 58 ++++++++++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 29 deletions(-) (limited to 'shared-core/nv50_fifo.c') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index ee1fb887..feab24c4 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -29,18 +29,18 @@ #include "nouveau_drv.h" typedef struct { - nouveau_gpuobj_ref_t *thingo; - nouveau_gpuobj_ref_t *dummyctx; + struct nouveau_gpuobj_ref *thingo; + struct nouveau_gpuobj_ref *dummyctx; } nv50_fifo_priv; #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) static void -nv50_fifo_init_thingo(drm_device_t *dev) +nv50_fifo_init_thingo(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; - nouveau_gpuobj_ref_t *thingo = priv->thingo; + struct nouveau_gpuobj_ref *thingo = priv->thingo; int i, fi=2; DRM_DEBUG("\n"); @@ -60,9 +60,9 @@ nv50_fifo_init_thingo(drm_device_t *dev) } static int -nv50_fifo_channel_enable(drm_device_t *dev, int channel) +nv50_fifo_channel_enable(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; DRM_DEBUG("ch%d\n", channel); @@ -88,9 +88,9 @@ nv50_fifo_channel_enable(drm_device_t *dev, int channel) } static void -nv50_fifo_channel_disable(drm_device_t *dev, int channel, int nt) +nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("ch%d, nt=%d\n", channel, nt); @@ -106,9 +106,9 @@ nv50_fifo_channel_disable(drm_device_t *dev, int channel, int nt) } static void -nv50_fifo_init_reset(drm_device_t *dev) +nv50_fifo_init_reset(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t pmc_e; DRM_DEBUG("\n"); @@ -120,7 +120,7 @@ nv50_fifo_init_reset(drm_device_t *dev) } static void -nv50_fifo_init_context_table(drm_device_t *dev) +nv50_fifo_init_context_table(struct drm_device *dev) { int i; @@ -132,9 +132,9 @@ nv50_fifo_init_context_table(drm_device_t *dev) } static void -nv50_fifo_init_regs__nv(drm_device_t *dev) +nv50_fifo_init_regs__nv(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; DRM_DEBUG("\n"); @@ -142,9 +142,9 @@ nv50_fifo_init_regs__nv(drm_device_t *dev) } static int -nv50_fifo_init_regs(drm_device_t *dev) +nv50_fifo_init_regs(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; int ret; @@ -176,9 +176,9 @@ nv50_fifo_init_regs(drm_device_t *dev) } int -nv50_fifo_init(drm_device_t *dev) +nv50_fifo_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_fifo_priv *priv; int ret; @@ -207,9 +207,9 @@ nv50_fifo_init(drm_device_t *dev) } void -nv50_fifo_takedown(drm_device_t *dev) +nv50_fifo_takedown(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; DRM_DEBUG("\n"); @@ -225,11 +225,11 @@ nv50_fifo_takedown(drm_device_t *dev) } int -nv50_fifo_create_context(drm_device_t *dev, int channel) +nv50_fifo_create_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - nouveau_gpuobj_t *ramfc = NULL; + struct nouveau_gpuobj *ramfc = NULL; int ret; DRM_DEBUG("ch%d\n", channel); @@ -283,9 +283,9 @@ nv50_fifo_create_context(drm_device_t *dev, int channel) } void -nv50_fifo_destroy_context(drm_device_t *dev, int channel) +nv50_fifo_destroy_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; DRM_DEBUG("ch%d\n", channel); @@ -295,11 +295,11 @@ nv50_fifo_destroy_context(drm_device_t *dev, int channel) } int -nv50_fifo_load_context(drm_device_t *dev, int channel) +nv50_fifo_load_context(struct drm_device *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; - nouveau_gpuobj_t *ramfc = chan->ramfc->gpuobj; + struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj; DRM_DEBUG("ch%d\n", channel); @@ -324,7 +324,7 @@ nv50_fifo_load_context(drm_device_t *dev, int channel) } int -nv50_fifo_save_context(drm_device_t *dev, int channel) +nv50_fifo_save_context(struct drm_device *dev, int channel) { DRM_DEBUG("ch%d\n", channel); DRM_ERROR("stub!\n"); -- cgit v1.2.3 From 0c95d489abd19efd2ba017e78a4b28cea0854e77 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 19 Jul 2007 16:42:58 +1000 Subject: nouveau/nv50: get non-default push buffer sizes working. --- shared-core/nv50_fifo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core/nv50_fifo.c') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index feab24c4..4933bbf3 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -263,7 +263,7 @@ nv50_fifo_create_context(struct drm_device *dev, int channel) INSTANCE_WR(ramfc, 0x54/4, 0x000f0000); INSTANCE_WR(ramfc, 0x7c/4, 0x30000001); INSTANCE_WR(ramfc, 0x78/4, 0x00000000); - INSTANCE_WR(ramfc, 0x4c/4, 0x00007fff); + INSTANCE_WR(ramfc, 0x4c/4, chan->pushbuf_mem->size - 1); if (!IS_G80) { INSTANCE_WR(chan->ramin->gpuobj, 0, channel); -- cgit v1.2.3 From e39286eb5eab8846a228863abf8f1b8b07a9e29d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 19 Jul 2007 17:00:17 -0700 Subject: Remove DRM_ERR OS macro. This was used to make all ioctl handlers return -errno on linux and errno on *BSD. Instead, just return -errno in shared code, and flip sign on return from shared code to *BSD code. --- shared-core/nv50_fifo.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'shared-core/nv50_fifo.c') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index 4933bbf3..f7b98220 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -69,14 +69,14 @@ nv50_fifo_channel_enable(struct drm_device *dev, int channel) if (IS_G80) { if (!chan->ramin) - return DRM_ERR(EINVAL); + return -EINVAL; NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), (chan->ramin->instance >> 12) | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); } else { if (!chan->ramfc) - return DRM_ERR(EINVAL); + return -EINVAL; NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), (chan->ramfc->instance >> 8) | @@ -186,7 +186,7 @@ nv50_fifo_init(struct drm_device *dev) priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); if (!priv) - return DRM_ERR(ENOMEM); + return -ENOMEM; dev_priv->Engine.fifo.priv = priv; nv50_fifo_init_reset(dev); -- cgit v1.2.3 From beaa0c9a28b30a6ba3292184d04875b6a597e433 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2007 03:40:43 +1000 Subject: nouveau: Pass channel struct around instead of channel id. --- shared-core/nv50_fifo.c | 41 ++++++++++++++++++++--------------------- 1 file changed, 20 insertions(+), 21 deletions(-) (limited to 'shared-core/nv50_fifo.c') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index f7b98220..a5e79260 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -63,7 +63,7 @@ static int nv50_fifo_channel_enable(struct drm_device *dev, int channel) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct nouveau_channel *chan = dev_priv->fifos[channel]; DRM_DEBUG("ch%d\n", channel); @@ -150,7 +150,7 @@ nv50_fifo_init_regs(struct drm_device *dev) DRM_DEBUG("\n"); - if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, 0x1000, + if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 0x1000, 0x1000, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, @@ -191,7 +191,7 @@ nv50_fifo_init(struct drm_device *dev) nv50_fifo_init_reset(dev); - if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, (128+2)*4, 0x1000, + if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, (128+2)*4, 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo))) { DRM_ERROR("error creating thingo: %d\n", ret); @@ -225,14 +225,14 @@ nv50_fifo_takedown(struct drm_device *dev) } int -nv50_fifo_create_context(struct drm_device *dev, int channel) +nv50_fifo_create_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_gpuobj *ramfc = NULL; int ret; - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); if (IS_G80) { uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; @@ -242,7 +242,7 @@ nv50_fifo_create_context(struct drm_device *dev, int channel) &ramfc, &chan->ramfc))) return ret; } else { - if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, 0x100, + if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100, 256, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, @@ -266,15 +266,15 @@ nv50_fifo_create_context(struct drm_device *dev, int channel) INSTANCE_WR(ramfc, 0x4c/4, chan->pushbuf_mem->size - 1); if (!IS_G80) { - INSTANCE_WR(chan->ramin->gpuobj, 0, channel); + INSTANCE_WR(chan->ramin->gpuobj, 0, chan->id); INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance); INSTANCE_WR(ramfc, 0x88/4, 0x3d520); /* some vram addy >> 10 */ INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12); } - if ((ret = nv50_fifo_channel_enable(dev, channel))) { - DRM_ERROR("error enabling ch%d: %d\n", channel, ret); + if ((ret = nv50_fifo_channel_enable(dev, chan->id))) { + DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret); nouveau_gpuobj_ref_del(dev, &chan->ramfc); return ret; } @@ -283,25 +283,24 @@ nv50_fifo_create_context(struct drm_device *dev, int channel) } void -nv50_fifo_destroy_context(struct drm_device *dev, int channel) +nv50_fifo_destroy_context(struct nouveau_channel *chan) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; + struct drm_device *dev = chan->dev; - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); - nv50_fifo_channel_disable(dev, channel, 0); + nv50_fifo_channel_disable(dev, chan->id, 0); nouveau_gpuobj_ref_del(dev, &chan->ramfc); } int -nv50_fifo_load_context(struct drm_device *dev, int channel) +nv50_fifo_load_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj; - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); /*XXX: incomplete, only touches the regs that NV does */ @@ -319,14 +318,14 @@ nv50_fifo_load_context(struct drm_device *dev, int channel) NV_WRITE(0x3410, INSTANCE_RD(ramfc, 0x98/4)); } - NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, channel | (1<<16)); + NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16)); return 0; } int -nv50_fifo_save_context(struct drm_device *dev, int channel) +nv50_fifo_save_context(struct nouveau_channel *chan) { - DRM_DEBUG("ch%d\n", channel); + DRM_DEBUG("ch%d\n", chan->id); DRM_ERROR("stub!\n"); return 0; } -- cgit v1.2.3 From 4ad487190d5b79947c65e238330506db6b77e523 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 8 Aug 2007 10:42:12 +1000 Subject: nouveau: enable/disable engine-specific interrupts in _init()/_takedown() All interrupts are still masked by PMC until init is finished. --- shared-core/nv50_fifo.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'shared-core/nv50_fifo.c') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index a5e79260..f915d332 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -119,6 +119,17 @@ nv50_fifo_init_reset(struct drm_device *dev) NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PFIFO); } +static void +nv50_fifo_init_intr(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + + DRM_DEBUG("\n"); + + NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF); + NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF); +} + static void nv50_fifo_init_context_table(struct drm_device *dev) { @@ -190,6 +201,7 @@ nv50_fifo_init(struct drm_device *dev) dev_priv->Engine.fifo.priv = priv; nv50_fifo_init_reset(dev); + nv50_fifo_init_intr(dev); if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, (128+2)*4, 0x1000, NVOBJ_FLAG_ZERO_ALLOC, -- cgit v1.2.3 From a46104674f129e873b8dfa29cf8aac9c67bd77be Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 10 Aug 2007 13:54:26 +1000 Subject: nouveau/nv50: demagic instmem setup. --- shared-core/nv50_fifo.c | 37 ++++++++++++++----------------------- 1 file changed, 14 insertions(+), 23 deletions(-) (limited to 'shared-core/nv50_fifo.c') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index f915d332..71b89d6d 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -30,7 +30,6 @@ typedef struct { struct nouveau_gpuobj_ref *thingo; - struct nouveau_gpuobj_ref *dummyctx; } nv50_fifo_priv; #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) @@ -47,7 +46,7 @@ nv50_fifo_init_thingo(struct drm_device *dev) INSTANCE_WR(thingo->gpuobj, 0, 0x7e); INSTANCE_WR(thingo->gpuobj, 1, 0x7e); - for (i = 0; i fifos[i]) { INSTANCE_WR(thingo->gpuobj, fi, i); fi++; @@ -60,7 +59,7 @@ nv50_fifo_init_thingo(struct drm_device *dev) } static int -nv50_fifo_channel_enable(struct drm_device *dev, int channel) +nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_channel *chan = dev_priv->fifos[channel]; @@ -83,7 +82,7 @@ nv50_fifo_channel_enable(struct drm_device *dev, int channel) NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); } - nv50_fifo_init_thingo(dev); + if (!nt) nv50_fifo_init_thingo(dev); return 0; } @@ -156,18 +155,9 @@ static int nv50_fifo_init_regs(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; - int ret; DRM_DEBUG("\n"); - if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 0x1000, - 0x1000, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ZERO_FREE, - &priv->dummyctx))) - return ret; - NV_WRITE(0x2500, 0); NV_WRITE(0x3250, 0); NV_WRITE(0x3220, 0); @@ -175,13 +165,9 @@ nv50_fifo_init_regs(struct drm_device *dev) NV_WRITE(0x3210, 0); NV_WRITE(0x3270, 0); - if (IS_G80) { - NV_WRITE(0x2600, (priv->dummyctx->instance>>8) | (1<<31)); - NV_WRITE(0x27fc, (priv->dummyctx->instance>>8) | (1<<31)); - } else { - NV_WRITE(0x2600, (priv->dummyctx->instance>>12) | (1<<31)); - NV_WRITE(0x27fc, (priv->dummyctx->instance>>12) | (1<<31)); - } + /* Enable dummy channels setup by nv50_instmem.c */ + nv50_fifo_channel_enable(dev, 0, 1); + nv50_fifo_channel_enable(dev, 127, 1); return 0; } @@ -209,6 +195,7 @@ nv50_fifo_init(struct drm_device *dev) DRM_ERROR("error creating thingo: %d\n", ret); return ret; } + nv50_fifo_init_context_table(dev); nv50_fifo_init_regs__nv(dev); @@ -230,7 +217,6 @@ nv50_fifo_takedown(struct drm_device *dev) return; nouveau_gpuobj_ref_del(dev, &priv->thingo); - nouveau_gpuobj_ref_del(dev, &priv->dummyctx); dev_priv->Engine.fifo.priv = NULL; drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); @@ -248,7 +234,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan) if (IS_G80) { uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; - if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, 0x100, + if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, ~0, 0x100, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, &ramfc, &chan->ramfc))) @@ -285,7 +271,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan) INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12); } - if ((ret = nv50_fifo_channel_enable(dev, chan->id))) { + if ((ret = nv50_fifo_channel_enable(dev, chan->id, 0))) { DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret); nouveau_gpuobj_ref_del(dev, &chan->ramfc); return ret; @@ -302,6 +288,11 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan) DRM_DEBUG("ch%d\n", chan->id); nv50_fifo_channel_disable(dev, chan->id, 0); + + /* Dummy channel, also used on ch 127 */ + if (chan->id == 0) + nv50_fifo_channel_disable(dev, 127, 0); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); } -- cgit v1.2.3 From ae883c97ad7af5529d40c8d52c2da614d34233e0 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 22 Aug 2007 12:54:26 +1000 Subject: nouveau/nv50: Correct thinko for 8800 chips + cleanup a bit. --- shared-core/nv50_fifo.c | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) (limited to 'shared-core/nv50_fifo.c') diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index 71b89d6d..7859544a 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -63,24 +63,17 @@ nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_channel *chan = dev_priv->fifos[channel]; + uint32_t inst; DRM_DEBUG("ch%d\n", channel); - if (IS_G80) { - if (!chan->ramin) - return -EINVAL; - - NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), - (chan->ramin->instance >> 12) | - NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); - } else { - if (!chan->ramfc) - return -EINVAL; + if (!chan->ramfc) + return -EINVAL; - NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), - (chan->ramfc->instance >> 8) | - NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); - } + if (IS_G80) inst = chan->ramfc->instance >> 12; + else inst = chan->ramfc->instance >> 8; + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), + inst | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); if (!nt) nv50_fifo_init_thingo(dev); return 0; @@ -90,16 +83,13 @@ static void nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt) { struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t inst; DRM_DEBUG("ch%d, nt=%d\n", channel, nt); - if (IS_G80) { - NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), - NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80); - } else { - NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), - NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84); - } + if (IS_G80) inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80; + else inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84; + NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst); if (!nt) nv50_fifo_init_thingo(dev); } @@ -234,7 +224,9 @@ nv50_fifo_create_context(struct nouveau_channel *chan) if (IS_G80) { uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; - if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, ~0, 0x100, + uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start; + if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, + vram_offset, 0x100, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, &ramfc, &chan->ramfc))) -- cgit v1.2.3