From 674cefd4fe4b537a20a10edcb4ec5df55facca8e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 26 Mar 2007 19:43:48 +1000 Subject: nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E --- shared-core/nv40_mc.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 shared-core/nv40_mc.c (limited to 'shared-core/nv40_mc.c') diff --git a/shared-core/nv40_mc.c b/shared-core/nv40_mc.c new file mode 100644 index 00000000..554a2241 --- /dev/null +++ b/shared-core/nv40_mc.c @@ -0,0 +1,36 @@ +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" +#include "nouveau_drm.h" + +int +nv40_mc_init(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t tmp; + + NV_WRITE(NV03_PMC_INTR_EN_0, 0); + + switch (dev_priv->chipset) { + case 0x44: + case 0x46: /* G72 */ + case 0x4e: + case 0x4c: /* C51_G7X */ + tmp = NV_READ(NV40_PFB_020C); + NV_WRITE(NV40_PMC_1700, tmp); + NV_WRITE(NV40_PMC_1704, 0); + NV_WRITE(NV40_PMC_1708, 0); + NV_WRITE(NV40_PMC_170C, tmp); + break; + default: + break; + } + + return 0; +} + +void +nv40_mc_takedown(drm_device_t *dev) +{ +} + -- cgit v1.2.3