From 163f8526123ffa38783fc911b5f7a19debce7f73 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 2 Jul 2007 19:31:18 +1000 Subject: nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object. --- shared-core/nv20_graph.c | 53 ++++++++++++++++++++++++------------------------ 1 file changed, 26 insertions(+), 27 deletions(-) (limited to 'shared-core/nv20_graph.c') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 1b8a6727..13271051 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -34,19 +34,18 @@ int nv20_graph_create_context(drm_device_t *dev, int channel) { (drm_nouveau_private_t *)dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; unsigned int ctx_size = NV20_GRCTX_SIZE; - int i; + int ret; - /* Alloc and clear RAMIN to store the context */ - chan->ramin_grctx = nouveau_instmem_alloc(dev, ctx_size, 4); - if (!chan->ramin_grctx) - return DRM_ERR(ENOMEM); - for (i=0; iramin_grctx, i/4, 0x00000000); + if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, ctx_size, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &chan->ramin_grctx))) + return ret; /* Initialise default context values */ - INSTANCE_WR(chan->ramin_grctx, 10, channel << 24); /* CTX_USER */ + INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, channel<<24); /* CTX_USER */ - INSTANCE_WR(dev_priv->ctx_table, channel, nouveau_chip_instance_get(dev, chan->ramin_grctx)); + INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, + chan->ramin_grctx->instance >> 4); return 0; } @@ -54,12 +53,10 @@ void nv20_graph_destroy_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; struct nouveau_fifo *chan = &dev_priv->fifos[channel]; - if (chan->ramin_grctx) { - nouveau_instmem_free(dev, chan->ramin_grctx); - chan->ramin_grctx = NULL; - } + if (chan->ramin_grctx) + nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); - INSTANCE_WR(dev_priv->ctx_table, channel, 0); + INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, 0); } static void nv20_graph_rdi(drm_device_t *dev) { @@ -79,13 +76,14 @@ static void nv20_graph_rdi(drm_device_t *dev) { int nv20_graph_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; uint32_t instance; - instance = INSTANCE_RD(dev_priv->ctx_table, channel); + instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); if (!instance) { return DRM_ERR(EINVAL); } - if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx)) + if (instance != (chan->ramin_grctx->instance >> 4)) DRM_ERROR("nv20_graph_save_context : bad instance\n"); NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance); @@ -99,13 +97,14 @@ int nv20_graph_save_context(drm_device_t *dev, int channel) { int nv20_graph_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; + struct nouveau_fifo *chan = &dev_priv->fifos[channel]; uint32_t instance; - instance = INSTANCE_RD(dev_priv->ctx_table, channel); + instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); if (!instance) { return DRM_ERR(EINVAL); } - if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx)) + if (instance != (chan->ramin_grctx->instance >> 4)) DRM_ERROR("nv20_graph_load_context_current : bad instance\n"); NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); @@ -148,8 +147,8 @@ void nouveau_nv20_context_switch(drm_device_t *dev) int nv20_graph_init(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - int i; uint32_t tmp, vramsz; + int ret, i; NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); @@ -158,14 +157,14 @@ int nv20_graph_init(drm_device_t *dev) { /* Create Context Pointer Table */ dev_priv->ctx_table_size = 32 * 4; - dev_priv->ctx_table = nouveau_instmem_alloc(dev, dev_priv->ctx_table_size, 4); - if (!dev_priv->ctx_table) - return DRM_ERR(ENOMEM); - - for (i=0; i< dev_priv->ctx_table_size; i+=4) - INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000); - - NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table)); + if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, + dev_priv->ctx_table_size, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &dev_priv->ctx_table))) + return ret; + + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, + dev_priv->ctx_table->instance >> 4); //XXX need to be done and save/restore for each fifo ??? nv20_graph_rdi(dev); -- cgit v1.2.3 From c806bba4665bb369168ee0b453fa28e2e0bf2a5d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 5 Jul 2007 00:12:33 +1000 Subject: nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80. --- shared-core/nv20_graph.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'shared-core/nv20_graph.c') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 13271051..06d7e440 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -32,7 +32,7 @@ int nv20_graph_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; unsigned int ctx_size = NV20_GRCTX_SIZE; int ret; @@ -51,7 +51,7 @@ int nv20_graph_create_context(drm_device_t *dev, int channel) { void nv20_graph_destroy_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; if (chan->ramin_grctx) nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); @@ -76,7 +76,7 @@ static void nv20_graph_rdi(drm_device_t *dev) { int nv20_graph_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t instance; instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); @@ -97,7 +97,7 @@ int nv20_graph_save_context(drm_device_t *dev, int channel) { int nv20_graph_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t instance; instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); -- cgit v1.2.3 From 0029713451af6f5f216079775ff77cae9b423c0e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 13 Jul 2007 15:09:31 +1000 Subject: nouveau: nuke internal typedefs, and drm_device_t use. --- shared-core/nv20_graph.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) (limited to 'shared-core/nv20_graph.c') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 06d7e440..e6aa1e2a 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -29,9 +29,9 @@ #define NV20_GRCTX_SIZE (3529*4) -int nv20_graph_create_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; +int nv20_graph_create_context(struct drm_device *dev, int channel) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; unsigned int ctx_size = NV20_GRCTX_SIZE; int ret; @@ -49,8 +49,8 @@ int nv20_graph_create_context(drm_device_t *dev, int channel) { return 0; } -void nv20_graph_destroy_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = dev->dev_private; +void nv20_graph_destroy_context(struct drm_device *dev, int channel) { + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; if (chan->ramin_grctx) @@ -59,9 +59,9 @@ void nv20_graph_destroy_context(drm_device_t *dev, int channel) { INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, 0); } -static void nv20_graph_rdi(drm_device_t *dev) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; +static void nv20_graph_rdi(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; int i; NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000); @@ -73,9 +73,9 @@ static void nv20_graph_rdi(drm_device_t *dev) { /* Save current context (from PGRAPH) into the channel's context */ -int nv20_graph_save_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; +int nv20_graph_save_context(struct drm_device *dev, int channel) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t instance; @@ -94,9 +94,9 @@ int nv20_graph_save_context(drm_device_t *dev, int channel) { /* Restore the context for a specific channel into PGRAPH */ -int nv20_graph_load_context(drm_device_t *dev, int channel) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; +int nv20_graph_load_context(struct drm_device *dev, int channel) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t instance; @@ -113,9 +113,9 @@ int nv20_graph_load_context(drm_device_t *dev, int channel) { return 0; } -void nouveau_nv20_context_switch(drm_device_t *dev) +void nouveau_nv20_context_switch(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int channel, channel_old; channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); @@ -144,9 +144,9 @@ void nouveau_nv20_context_switch(drm_device_t *dev) NV_WRITE(NV04_PGRAPH_FIFO,0x1); } -int nv20_graph_init(drm_device_t *dev) { - drm_nouveau_private_t *dev_priv = - (drm_nouveau_private_t *)dev->dev_private; +int nv20_graph_init(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = + (struct drm_nouveau_private *)dev->dev_private; uint32_t tmp, vramsz; int ret, i; @@ -240,7 +240,7 @@ int nv20_graph_init(drm_device_t *dev) { return 0; } -void nv20_graph_takedown(drm_device_t *dev) +void nv20_graph_takedown(struct drm_device *dev) { } -- cgit v1.2.3 From 875dd1e53852d231b60eb82bfed33c016f92f3b8 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 17 Jul 2007 14:06:05 +1000 Subject: nouveau: Destroy PGRAPH context table on PGRAPH takedown --- shared-core/nv20_graph.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'shared-core/nv20_graph.c') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index e6aa1e2a..8af3bd12 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -242,5 +242,8 @@ int nv20_graph_init(struct drm_device *dev) { void nv20_graph_takedown(struct drm_device *dev) { + struct drm_nouveau_private *dev_priv = dev->dev_private; + + nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table); } -- cgit v1.2.3 From e39286eb5eab8846a228863abf8f1b8b07a9e29d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 19 Jul 2007 17:00:17 -0700 Subject: Remove DRM_ERR OS macro. This was used to make all ioctl handlers return -errno on linux and errno on *BSD. Instead, just return -errno in shared code, and flip sign on return from shared code to *BSD code. --- shared-core/nv20_graph.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'shared-core/nv20_graph.c') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 8af3bd12..1670c527 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -81,7 +81,7 @@ int nv20_graph_save_context(struct drm_device *dev, int channel) { instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); if (!instance) { - return DRM_ERR(EINVAL); + return -EINVAL; } if (instance != (chan->ramin_grctx->instance >> 4)) DRM_ERROR("nv20_graph_save_context : bad instance\n"); @@ -102,7 +102,7 @@ int nv20_graph_load_context(struct drm_device *dev, int channel) { instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); if (!instance) { - return DRM_ERR(EINVAL); + return -EINVAL; } if (instance != (chan->ramin_grctx->instance >> 4)) DRM_ERROR("nv20_graph_load_context_current : bad instance\n"); -- cgit v1.2.3 From beaa0c9a28b30a6ba3292184d04875b6a597e433 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2007 03:40:43 +1000 Subject: nouveau: Pass channel struct around instead of channel id. --- shared-core/nv20_graph.c | 68 ++++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 34 deletions(-) (limited to 'shared-core/nv20_graph.c') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index 1670c527..d397390f 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -29,39 +29,36 @@ #define NV20_GRCTX_SIZE (3529*4) -int nv20_graph_create_context(struct drm_device *dev, int channel) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; +int nv20_graph_create_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; unsigned int ctx_size = NV20_GRCTX_SIZE; int ret; - if ((ret = nouveau_gpuobj_new_ref(dev, channel, -1, 0, ctx_size, 16, + if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16, NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx))) return ret; /* Initialise default context values */ - INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, channel<<24); /* CTX_USER */ + INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); /* CTX_USER */ - INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, + INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, chan->ramin_grctx->instance >> 4); return 0; } -void nv20_graph_destroy_context(struct drm_device *dev, int channel) { +void nv20_graph_destroy_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; - if (chan->ramin_grctx) - nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); + nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); - INSTANCE_WR(dev_priv->ctx_table->gpuobj, channel, 0); + INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0); } static void nv20_graph_rdi(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000); @@ -73,13 +70,12 @@ static void nv20_graph_rdi(struct drm_device *dev) { /* Save current context (from PGRAPH) into the channel's context */ -int nv20_graph_save_context(struct drm_device *dev, int channel) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; +int nv20_graph_save_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t instance; - instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); + instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, chan->id); if (!instance) { return -EINVAL; } @@ -94,20 +90,19 @@ int nv20_graph_save_context(struct drm_device *dev, int channel) { /* Restore the context for a specific channel into PGRAPH */ -int nv20_graph_load_context(struct drm_device *dev, int channel) { - struct drm_nouveau_private *dev_priv = - (struct drm_nouveau_private *)dev->dev_private; - struct nouveau_fifo *chan = dev_priv->fifos[channel]; +int nv20_graph_load_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t instance; - instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, channel); + instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, chan->id); if (!instance) { return -EINVAL; } if (instance != (chan->ramin_grctx->instance >> 4)) DRM_ERROR("nv20_graph_load_context_current : bad instance\n"); - NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); + NV_WRITE(NV10_PGRAPH_CTX_USER, chan->id << 24); NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance); NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */); return 0; @@ -116,27 +111,32 @@ int nv20_graph_load_context(struct drm_device *dev, int channel) { void nouveau_nv20_context_switch(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int channel, channel_old; + struct nouveau_channel *next, *last; + int chid; + + chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + next = dev_priv->fifos[chid]; - channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); - channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + last = dev_priv->fifos[chid]; - DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); + DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n", + last->id, next->id); NV_WRITE(NV04_PGRAPH_FIFO,0x0); - nv20_graph_save_context(dev, channel_old); + nv20_graph_save_context(last); nouveau_wait_for_idle(dev); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000); - nv20_graph_load_context(dev, channel); + nv20_graph_load_context(next); nouveau_wait_for_idle(dev); - if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != channel) - DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV10_PGRAPH_CTX_USER) >> 24); + if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != next->id) + DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", next->id, NV_READ(NV10_PGRAPH_CTX_USER) >> 24); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); @@ -157,7 +157,7 @@ int nv20_graph_init(struct drm_device *dev) { /* Create Context Pointer Table */ dev_priv->ctx_table_size = 32 * 4; - if ((ret = nouveau_gpuobj_new_ref(dev, -1, -1, 0, + if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, dev_priv->ctx_table_size, 16, NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ctx_table))) -- cgit v1.2.3 From 4ad487190d5b79947c65e238330506db6b77e523 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 8 Aug 2007 10:42:12 +1000 Subject: nouveau: enable/disable engine-specific interrupts in _init()/_takedown() All interrupts are still masked by PMC until init is finished. --- shared-core/nv20_graph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core/nv20_graph.c') diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c index d397390f..c163daf9 100644 --- a/shared-core/nv20_graph.c +++ b/shared-core/nv20_graph.c @@ -169,8 +169,8 @@ int nv20_graph_init(struct drm_device *dev) { //XXX need to be done and save/restore for each fifo ??? nv20_graph_rdi(dev); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000); NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); + NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); -- cgit v1.2.3