From 2453ba19b6f9956ea5d412a66d5d33c8a8b301b2 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Fri, 3 Aug 2007 23:06:39 +0200 Subject: nouveau:nv10: fill and use load,save graph context functions --- shared-core/nv10_graph.c | 55 +++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 29 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 930fcbdf..ce1cbfa7 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -544,24 +544,42 @@ static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg) return -1; } -static void restore_ctx_regs(struct drm_device *dev, int channel) +int nv10_graph_load_context(struct drm_device *dev, int channel) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *fifo = dev_priv->fifos[channel]; int i, j; + for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) NV_WRITE(nv10_graph_ctx_regs[i], fifo->pgraph_ctx[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) NV_WRITE(nv17_graph_ctx_regs[j], fifo->pgraph_ctx[i]); } - nouveau_wait_for_idle(dev); + + return 0; +} + +int nv10_graph_save_context(struct drm_device *dev, int channel) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_fifo *fifo = dev_priv->fifos[channel]; + int i, j; + + for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) + fifo->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + if (dev_priv->chipset>=0x17) { + for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) + fifo->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); + } + + return 0; } void nouveau_nv10_context_switch(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int channel, channel_old, i, j; + int channel, channel_old; channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); @@ -574,14 +592,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); NV_WRITE(NV_PFIFO_CACHES, 0x00000000); #endif - - // save PGRAPH context - for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - dev_priv->fifos[channel_old]->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); - if (dev_priv->chipset>=0x17) { - for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - dev_priv->fifos[channel_old]->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); - } + nv10_graph_save_context(dev, channel_old); nouveau_wait_for_idle(dev); @@ -589,15 +600,12 @@ void nouveau_nv10_context_switch(struct drm_device *dev) NV_WRITE(NV10_PGRAPH_CTX_USER, (NV_READ(NV10_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); nouveau_wait_for_idle(dev); - // restore PGRAPH context -#if 1 - restore_ctx_regs(dev, channel); -#endif + + nv10_graph_load_context(dev, channel); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); - #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); @@ -611,6 +619,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) if (offset > 0) \ fifo->pgraph_ctx[offset] = val; \ } while (0) + int nv10_graph_create_context(struct drm_device *dev, int channel) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_fifo *fifo = dev_priv->fifos[channel]; @@ -654,7 +663,7 @@ int nv10_graph_create_context(struct drm_device *dev, int channel) { /* for the first channel init the regs */ if (dev_priv->fifo_alloc_count == 0) - restore_ctx_regs(dev, channel); + nv10_graph_load_context(dev, channel); //XXX should be saved/restored for each fifo @@ -667,18 +676,6 @@ void nv10_graph_destroy_context(struct drm_device *dev, int channel) { } -int nv10_graph_load_context(struct drm_device *dev, int channel) -{ - DRM_ERROR("stub!\n"); - return 0; -} - -int nv10_graph_save_context(struct drm_device *dev, int channel) -{ - DRM_ERROR("stub!\n"); - return 0; -} - int nv10_graph_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; int i; -- cgit v1.2.3 From beaa0c9a28b30a6ba3292184d04875b6a597e433 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2007 03:40:43 +1000 Subject: nouveau: Pass channel struct around instead of channel id. --- shared-core/nv10_graph.c | 49 ++++++++++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 22 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index ce1cbfa7..a2df2d71 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -544,33 +544,33 @@ static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg) return -1; } -int nv10_graph_load_context(struct drm_device *dev, int channel) +int nv10_graph_load_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *fifo = dev_priv->fifos[channel]; int i, j; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - NV_WRITE(nv10_graph_ctx_regs[i], fifo->pgraph_ctx[i]); + NV_WRITE(nv10_graph_ctx_regs[i], chan->pgraph_ctx[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - NV_WRITE(nv17_graph_ctx_regs[j], fifo->pgraph_ctx[i]); + NV_WRITE(nv17_graph_ctx_regs[j], chan->pgraph_ctx[i]); } return 0; } -int nv10_graph_save_context(struct drm_device *dev, int channel) +int nv10_graph_save_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *fifo = dev_priv->fifos[channel]; int i, j; for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - fifo->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + chan->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - fifo->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); + chan->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); } return 0; @@ -579,12 +579,17 @@ int nv10_graph_save_context(struct drm_device *dev, int channel) void nouveau_nv10_context_switch(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int channel, channel_old; + struct nouveau_channel *next, *last; + int chid; - channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); - channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + next = dev_priv->fifos[chid]; - DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); + chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + last = dev_priv->fifos[chid]; + + DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n", + last->id, next->id); NV_WRITE(NV04_PGRAPH_FIFO,0x0); #if 0 @@ -592,7 +597,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); NV_WRITE(NV_PFIFO_CACHES, 0x00000000); #endif - nv10_graph_save_context(dev, channel_old); + nv10_graph_save_context(last); nouveau_wait_for_idle(dev); @@ -601,10 +606,10 @@ void nouveau_nv10_context_switch(struct drm_device *dev) nouveau_wait_for_idle(dev); - nv10_graph_load_context(dev, channel); + nv10_graph_load_context(next); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); + NV_WRITE(NV10_PGRAPH_CTX_USER, next->id << 24); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); @@ -617,17 +622,17 @@ void nouveau_nv10_context_switch(struct drm_device *dev) #define NV_WRITE_CTX(reg, val) do { \ int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \ if (offset > 0) \ - fifo->pgraph_ctx[offset] = val; \ + chan->pgraph_ctx[offset] = val; \ } while (0) -int nv10_graph_create_context(struct drm_device *dev, int channel) { +int nv10_graph_create_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_fifo *fifo = dev_priv->fifos[channel]; uint32_t tmp, vramsz; - DRM_DEBUG("nv10_graph_context_create %d\n", channel); + DRM_DEBUG("nv10_graph_context_create %d\n", chan->id); - memset(fifo->pgraph_ctx, 0, sizeof(fifo->pgraph_ctx)); + memset(chan->pgraph_ctx, 0, sizeof(chan->pgraph_ctx)); /* per channel init from ddx */ tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; @@ -663,7 +668,7 @@ int nv10_graph_create_context(struct drm_device *dev, int channel) { /* for the first channel init the regs */ if (dev_priv->fifo_alloc_count == 0) - nv10_graph_load_context(dev, channel); + nv10_graph_load_context(chan); //XXX should be saved/restored for each fifo @@ -672,7 +677,7 @@ int nv10_graph_create_context(struct drm_device *dev, int channel) { return 0; } -void nv10_graph_destroy_context(struct drm_device *dev, int channel) +void nv10_graph_destroy_context(struct nouveau_channel *chan) { } -- cgit v1.2.3 From 4ad487190d5b79947c65e238330506db6b77e523 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 8 Aug 2007 10:42:12 +1000 Subject: nouveau: enable/disable engine-specific interrupts in _init()/_takedown() All interrupts are still masked by PMC until init is finished. --- shared-core/nv10_graph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index a2df2d71..53b93758 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -690,8 +690,8 @@ int nv10_graph_init(struct drm_device *dev) { NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH); - NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000); NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF); + NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); -- cgit v1.2.3 From 98750111961a5729eba9433b927f8c24548fbace Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Thu, 23 Aug 2007 10:18:34 +0200 Subject: nouveau: nv10: check some NULL pointers inside context switch --- shared-core/nv10_graph.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 53b93758..567ce6a4 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -578,16 +578,40 @@ int nv10_graph_save_context(struct nouveau_channel *chan) void nouveau_nv10_context_switch(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv; struct nouveau_channel *next, *last; int chid; + if (!dev) { + DRM_DEBUG("Invalid drm_device\n"); + return; + } + dev_priv = dev->dev_private; + if (!dev_priv) { + DRM_DEBUG("Invalid drm_nouveau_private\n"); + return; + } + if (!dev_priv->fifos) { + DRM_DEBUG("Invalid drm_nouveau_private->fifos\n"); + return; + } + chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); next = dev_priv->fifos[chid]; + if (!next) { + DRM_DEBUG("Invalid next channel\n"); + return; + } + chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); last = dev_priv->fifos[chid]; + if (!last) { + DRM_DEBUG("Invalid last channel\n"); + return; + } + DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n", last->id, next->id); @@ -607,7 +631,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) nouveau_wait_for_idle(dev); nv10_graph_load_context(next); - + NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV10_PGRAPH_CTX_USER, next->id << 24); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); -- cgit v1.2.3 From 502bbdbe14fa458ed06c7fa4b1ccb63e4f126625 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Sat, 25 Aug 2007 00:12:58 +0200 Subject: nouveau: nv10: output a warning if last channel invalid, and switch to next --- shared-core/nv10_graph.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 567ce6a4..18bab7eb 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -608,21 +608,23 @@ void nouveau_nv10_context_switch(struct drm_device *dev) last = dev_priv->fifos[chid]; if (!last) { - DRM_DEBUG("Invalid last channel\n"); - return; + DRM_DEBUG("WARNING: Invalid last channel, switch to %x\n", + next->id); + } else { + DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n", + last->id, next->id); } - DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n", - last->id, next->id); - NV_WRITE(NV04_PGRAPH_FIFO,0x0); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); NV_WRITE(NV_PFIFO_CACHES, 0x00000000); #endif - nv10_graph_save_context(last); - + if (last) { + nv10_graph_save_context(last); + } + nouveau_wait_for_idle(dev); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000); -- cgit v1.2.3 From 4182fce4084f4d884a7435b8ad2acb5c209f4544 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Sat, 25 Aug 2007 22:10:45 +0200 Subject: nouveau : nv1x graph reworks - add forgotten init value - use the same PGRAPH_DEBUG than the blob - remove init of ddx reg : it should be done with object - better handle of channel destruction hope I didn't break anything ;) --- shared-core/nv10_graph.c | 67 ++++++++++++++++++++++++++++++++++-------------- 1 file changed, 48 insertions(+), 19 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 18bab7eb..c604ff2e 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -181,11 +181,7 @@ static void nv10_praph_pipe(struct drm_device *dev) { nouveau_wait_for_idle(dev); } -/* TODO replace address with name - use loops */ static int nv10_graph_ctx_regs [] = { -NV03_PGRAPH_XY_LOGIC_MISC0, - NV10_PGRAPH_CTX_SWITCH1, NV10_PGRAPH_CTX_SWITCH2, NV10_PGRAPH_CTX_SWITCH3, @@ -455,6 +451,7 @@ NV03_PGRAPH_ABS_UCLIPA_YMIN, NV03_PGRAPH_ABS_UCLIPA_YMAX, NV03_PGRAPH_ABS_ICLIP_XMAX, NV03_PGRAPH_ABS_ICLIP_YMAX, +NV03_PGRAPH_XY_LOGIC_MISC0, NV03_PGRAPH_XY_LOGIC_MISC1, NV03_PGRAPH_XY_LOGIC_MISC2, NV03_PGRAPH_XY_LOGIC_MISC3, @@ -556,6 +553,7 @@ int nv10_graph_load_context(struct nouveau_channel *chan) for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) NV_WRITE(nv17_graph_ctx_regs[j], chan->pgraph_ctx[i]); } + NV_WRITE(NV10_PGRAPH_CTX_USER, chan->id << 24); return 0; } @@ -616,11 +614,6 @@ void nouveau_nv10_context_switch(struct drm_device *dev) } NV_WRITE(NV04_PGRAPH_FIFO,0x0); -#if 0 - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); - NV_WRITE(NV_PFIFO_CACHES, 0x00000000); -#endif if (last) { nv10_graph_save_context(last); } @@ -635,13 +628,8 @@ void nouveau_nv10_context_switch(struct drm_device *dev) nv10_graph_load_context(next); NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV10_PGRAPH_CTX_USER, next->id << 24); + //NV_WRITE(NV10_PGRAPH_CTX_USER, next->id << 24); NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); -#if 0 - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); - NV_WRITE(NV_PFIFO_CACHES, 0x00000001); -#endif NV_WRITE(NV04_PGRAPH_FIFO,0x1); } @@ -654,12 +642,14 @@ void nouveau_nv10_context_switch(struct drm_device *dev) int nv10_graph_create_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t tmp, vramsz; DRM_DEBUG("nv10_graph_context_create %d\n", chan->id); memset(chan->pgraph_ctx, 0, sizeof(chan->pgraph_ctx)); + /* mmio trace suggest that should be done in ddx with methods/objects */ +#if 0 + uint32_t tmp, vramsz; /* per channel init from ddx */ tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; /*XXX the original ddx code, does this in 2 steps : @@ -684,12 +674,23 @@ int nv10_graph_create_context(struct nouveau_channel *chan) { NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMIN, 0); NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); +#endif + NV_WRITE_CTX(0x00400e88, 0x08000000); + NV_WRITE_CTX(0x00400e9c, 0x4b7fffff); NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff); - /* is it really needed ??? */ + NV_WRITE_CTX(0x00400e10, 0x00001000); + NV_WRITE_CTX(0x00400e14, 0x00001000); + NV_WRITE_CTX(0x00400e30, 0x00080008); + NV_WRITE_CTX(0x00400e34, 0x00080008); if (dev_priv->chipset>=0x17) { + /* is it really needed ??? */ NV_WRITE_CTX(NV10_PGRAPH_DEBUG_4, NV_READ(NV10_PGRAPH_DEBUG_4)); NV_WRITE_CTX(0x004006b0, NV_READ(0x004006b0)); + NV_WRITE_CTX(0x00400eac, 0x0fff0000); + NV_WRITE_CTX(0x00400eb0, 0x0fff0000); + NV_WRITE_CTX(0x00400ec0, 0x00000080); + NV_WRITE_CTX(0x00400ed0, 0x00000080); } /* for the first channel init the regs */ @@ -705,6 +706,23 @@ int nv10_graph_create_context(struct nouveau_channel *chan) { void nv10_graph_destroy_context(struct nouveau_channel *chan) { + struct drm_device *dev = chan->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + int chid; + chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + + /* does this avoid a potential context switch while we are written graph + * reg, or we should mask graph interrupt ??? + */ + NV_WRITE(NV04_PGRAPH_FIFO,0x0); + if (chid == chan->id) { + DRM_INFO("cleanning a channel with graph in current context\n"); + nouveau_wait_for_idle(dev); + DRM_INFO("reseting current graph context\n"); + nv10_graph_create_context(chan); + nv10_graph_load_context(chan); + } + NV_WRITE(NV04_PGRAPH_FIFO,0x1); } int nv10_graph_init(struct drm_device *dev) { @@ -722,10 +740,17 @@ int nv10_graph_init(struct drm_device *dev) { NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000); NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700); - NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x24E00810); - NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x55DE0030 | + //NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x24E00810); /* 0x25f92ad9 */ + NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x25f92ad9); + NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1<<29) | (1<<31)); + if (dev_priv->chipset>=0x17) { + NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x1f000000); + NV_WRITE(0x004006b0, 0x40000020); + } + else + NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000); /* copy tile info from PFB */ for (i=0; i Date: Sun, 26 Aug 2007 20:48:32 +0200 Subject: nouveau : add NV04_PGRAPH_TRAPPED_ADDR definition - fix offset for nv04 - use it in nv10 graph ctx switch for getting next channel - dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+ --- shared-core/nv10_graph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index c604ff2e..e470ff06 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -594,7 +594,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev) return; } - chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + chid = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20)&(nouveau_fifo_number(dev)-1); next = dev_priv->fifos[chid]; if (!next) { -- cgit v1.2.3