From d4c9f135b56eee826f0d5eaf41f2088a861da590 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Fri, 26 Jan 2007 18:10:31 +0100 Subject: nouveau: add some nv10 pgraph defines --- shared-core/nv10_graph.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index ccbb34de..038e09cc 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -193,11 +193,11 @@ NV_PGRAPH_CTX_SWITCH2, NV_PGRAPH_CTX_SWITCH3, NV_PGRAPH_CTX_SWITCH4, NV_PGRAPH_CTX_SWITCH5, -0x00400160, -0x00400180, -0x004001a0, -0x004001c0, -0x004001e0, +NV_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */ +NV_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */ +NV_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */ +NV_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */ +NV_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */ 0x00400164, 0x00400184, 0x004001a4, @@ -270,7 +270,7 @@ NV_PGRAPH_BPIXEL, NV_PGRAPH_NOTIFY, NV_PGRAPH_PATT_COLOR0, NV_PGRAPH_PATT_COLOR1, -0x00400900, +NV_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */ 0x00400904, 0x00400908, 0x0040090c, @@ -334,7 +334,7 @@ NV_PGRAPH_PATT_COLOR1, 0x004009f4, 0x004009f8, 0x004009fc, -0x00400808, +NV_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */ 0x0040080c, NV_PGRAPH_PATTERN_SHAPE, NV_PGRAPH_MONO_COLOR0, @@ -373,8 +373,8 @@ NV_PGRAPH_BETA_PREMULT, 0x00400e94, 0x00400e98, 0x00400e9c, -0x00400f00, -0x00400f20, +NV_PGRAPH_WINDOWCLIP_HORIZONTAL,/* 8 values from 0x400f00 to 0x400f1c */ +NV_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */ 0x00400f04, 0x00400f24, 0x00400f08, @@ -395,8 +395,8 @@ NV_PGRAPH_GLOBALSTATE0, NV_PGRAPH_GLOBALSTATE1, NV_PGRAPH_STORED_FMT, NV_PGRAPH_SOURCE_COLOR, -0x00400400, -0x00400480, +NV_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */ +NV_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */ 0x00400404, 0x00400484, 0x00400408, -- cgit v1.2.3 From 05d3ed472e6ab5cfa7741e523bdb3992591ecc7e Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Fri, 26 Jan 2007 19:25:49 +0100 Subject: nouveau: only save/restore nv17 regs on nv17,18 hw --- shared-core/nv10_graph.c | 46 +++++++++++++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 15 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 038e09cc..9a04bd86 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -354,21 +354,6 @@ NV_PGRAPH_BETA_PREMULT, 0x00400ea4, 0x00400ea8, 0x00400eac, -0x00400eb0, -0x00400eb4, -0x00400eb8, -0x00400ebc, -0x00400ec0, -0x00400ec4, -0x00400ec8, -0x00400ecc, -0x00400ed0, -0x00400ed4, -0x00400ed8, -0x00400edc, -0x00400ee0, -0x00400a00, -0x00400a04, 0x00400e90, 0x00400e94, 0x00400e98, @@ -525,6 +510,25 @@ NV_PGRAPH_VALID2, 0 }; +static int nv17_graph_ctx_regs [] = { +0x00400eb0, +0x00400eb4, +0x00400eb8, +0x00400ebc, +0x00400ec0, +0x00400ec4, +0x00400ec8, +0x00400ecc, +0x00400ed0, +0x00400ed4, +0x00400ed8, +0x00400edc, +0x00400ee0, +0x00400a00, +0x00400a04, +0 +}; + void nouveau_nv10_context_switch(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; @@ -545,6 +549,12 @@ void nouveau_nv10_context_switch(drm_device_t *dev) // save PGRAPH context for (i = 0; nv10_graph_ctx_regs[i]; i++) dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + if ((NV_READ(NV_PMC_BOOT_0) & 0x0ff00000)==0x01700000) + || (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000)==0x01800000)) + { + for (; nv17_graph_ctx_regs[i]; i++) + dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[i]); + } nouveau_wait_for_idle(dev); @@ -557,6 +567,12 @@ void nouveau_nv10_context_switch(drm_device_t *dev) #if 0 for (i = 0; nv10_graph_ctx_regs[i]; i++) NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); + if ((NV_READ(NV_PMC_BOOT_0) & 0x0ff00000)==0x01700000) + || (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000)==0x01800000)) + { + for (; nv17_graph_ctx_regs[i]; i++) + NV_WRITE(nv17_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); + } nouveau_wait_for_idle(dev); #endif -- cgit v1.2.3 From 5534c90ff39bf2bd41daca024d5b19889e78b1a0 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Fri, 26 Jan 2007 19:54:35 +0100 Subject: nouveau: read gpu type once --- shared-core/nv10_graph.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 9a04bd86..b67122af 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -532,7 +532,7 @@ static int nv17_graph_ctx_regs [] = { void nouveau_nv10_context_switch(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; - int channel, channel_old, i; + int channel, channel_old, i, gpu_type; channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); @@ -549,8 +549,10 @@ void nouveau_nv10_context_switch(drm_device_t *dev) // save PGRAPH context for (i = 0; nv10_graph_ctx_regs[i]; i++) dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); - if ((NV_READ(NV_PMC_BOOT_0) & 0x0ff00000)==0x01700000) - || (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000)==0x01800000)) + gpu_type = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000); + if ((gpu_type==0x01700000) + || (gpu_type==0x01800000) + || (gpu_type==0x01f00000)) { for (; nv17_graph_ctx_regs[i]; i++) dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[i]); @@ -567,8 +569,9 @@ void nouveau_nv10_context_switch(drm_device_t *dev) #if 0 for (i = 0; nv10_graph_ctx_regs[i]; i++) NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); - if ((NV_READ(NV_PMC_BOOT_0) & 0x0ff00000)==0x01700000) - || (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000)==0x01800000)) + if ((gpu_type==0x01700000) + || (gpu_type==0x01800000) + || (gpu_type==0x01f00000)) { for (; nv17_graph_ctx_regs[i]; i++) NV_WRITE(nv17_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); -- cgit v1.2.3 From 9c03ca81e75c1c0749b719bb62ae56b99c9ff2ae Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Fri, 26 Jan 2007 21:05:59 +0100 Subject: nouveau: oops, wrong indexing in nv17 regs --- shared-core/nv10_graph.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index b67122af..54d1c34b 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -532,7 +532,7 @@ static int nv17_graph_ctx_regs [] = { void nouveau_nv10_context_switch(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; - int channel, channel_old, i, gpu_type; + int channel, channel_old, i, j, gpu_type; channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); @@ -554,8 +554,8 @@ void nouveau_nv10_context_switch(drm_device_t *dev) || (gpu_type==0x01800000) || (gpu_type==0x01f00000)) { - for (; nv17_graph_ctx_regs[i]; i++) - dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[i]); + for (j = 0; nv17_graph_ctx_regs[j]; i++,j++) + dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); } nouveau_wait_for_idle(dev); @@ -573,8 +573,8 @@ void nouveau_nv10_context_switch(drm_device_t *dev) || (gpu_type==0x01800000) || (gpu_type==0x01f00000)) { - for (; nv17_graph_ctx_regs[i]; i++) - NV_WRITE(nv17_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); + for (j = 0; nv17_graph_ctx_regs[j]; i++,j++) + NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); } nouveau_wait_for_idle(dev); #endif -- cgit v1.2.3 From c744bfde2de1713f0c15a185538a003d64c52d80 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Fri, 26 Jan 2007 21:57:44 +0100 Subject: make works ctx switch on nv10. --- shared-core/nv10_graph.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 54d1c34b..c9ff96ea 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -188,7 +188,7 @@ NV_PGRAPH_XY_LOGIC_MISC0, NV_PGRAPH_DEBUG_4, 0x004006b0, -NV_PGRAPH_CTX_SWITCH1, +//NV_PGRAPH_CTX_SWITCH1, make ctx switch crash NV_PGRAPH_CTX_SWITCH2, NV_PGRAPH_CTX_SWITCH3, NV_PGRAPH_CTX_SWITCH4, @@ -566,7 +566,7 @@ void nouveau_nv10_context_switch(drm_device_t *dev) nouveau_wait_for_idle(dev); // restore PGRAPH context //XXX not working yet -#if 0 +#if 1 for (i = 0; nv10_graph_ctx_regs[i]; i++) NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); if ((gpu_type==0x01700000) @@ -602,12 +602,15 @@ int nv10_graph_context_create(drm_device_t *dev, int channel) { /* is it really needed ??? */ dev_priv->fifos[channel].nv10_pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4); dev_priv->fifos[channel].nv10_pgraph_ctx[2] = NV_READ(0x004006b0); + + + //XXX should be saved/restored for each fifo + //we supposed here we have X fifo and only one 3D fifo. + nv10_praph_pipe(dev); return 0; } int nv10_graph_init(drm_device_t *dev) { - //XXX should be call at each fifo init - nv10_praph_pipe(dev); return 0; } -- cgit v1.2.3 From ee4ac5c897faa499ad24c148b4f065bc770b529d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 28 Jan 2007 23:48:33 +1100 Subject: nouveau: determine chipset type at startup, instead of every time we use it. --- shared-core/nv10_graph.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index c9ff96ea..39aaba60 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -532,7 +532,7 @@ static int nv17_graph_ctx_regs [] = { void nouveau_nv10_context_switch(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; - int channel, channel_old, i, j, gpu_type; + int channel, channel_old, i, j; channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); @@ -549,10 +549,9 @@ void nouveau_nv10_context_switch(drm_device_t *dev) // save PGRAPH context for (i = 0; nv10_graph_ctx_regs[i]; i++) dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); - gpu_type = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000); - if ((gpu_type==0x01700000) - || (gpu_type==0x01800000) - || (gpu_type==0x01f00000)) + if ((dev_priv->chipset==0x17) + || (dev_priv->chipset==0x18) + || (dev_priv->chipset==0x1f)) { for (j = 0; nv17_graph_ctx_regs[j]; i++,j++) dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); @@ -569,9 +568,9 @@ void nouveau_nv10_context_switch(drm_device_t *dev) #if 1 for (i = 0; nv10_graph_ctx_regs[i]; i++) NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); - if ((gpu_type==0x01700000) - || (gpu_type==0x01800000) - || (gpu_type==0x01f00000)) + if ((dev_priv->chipset==0x17) + || (dev_priv->chipset==0x18) + || (dev_priv->chipset==0x1f)) { for (j = 0; nv17_graph_ctx_regs[j]; i++,j++) NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); -- cgit v1.2.3 From 63cf3b3da7ee039c98c793d31ea1aa586a069c43 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Fri, 2 Feb 2007 20:08:33 +0100 Subject: nouveau: nv10 ctx switch, some regs are nv17+ only --- shared-core/nv10_graph.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 39aaba60..726ec6df 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -185,8 +185,6 @@ static void nv10_praph_pipe(drm_device_t *dev) { use loops */ static int nv10_graph_ctx_regs [] = { NV_PGRAPH_XY_LOGIC_MISC0, -NV_PGRAPH_DEBUG_4, -0x004006b0, //NV_PGRAPH_CTX_SWITCH1, make ctx switch crash NV_PGRAPH_CTX_SWITCH2, @@ -353,7 +351,6 @@ NV_PGRAPH_BETA_PREMULT, 0x00400ea0, 0x00400ea4, 0x00400ea8, -0x00400eac, 0x00400e90, 0x00400e94, 0x00400e98, @@ -507,10 +504,12 @@ NV_PGRAPH_X_MISC, NV_PGRAPH_Y_MISC, NV_PGRAPH_VALID1, NV_PGRAPH_VALID2, -0 }; static int nv17_graph_ctx_regs [] = { +NV_PGRAPH_DEBUG_4, +0x004006b0, +0x00400eac, 0x00400eb0, 0x00400eb4, 0x00400eb8, @@ -526,7 +525,6 @@ static int nv17_graph_ctx_regs [] = { 0x00400ee0, 0x00400a00, 0x00400a04, -0 }; void nouveau_nv10_context_switch(drm_device_t *dev) @@ -547,13 +545,10 @@ void nouveau_nv10_context_switch(drm_device_t *dev) #endif // save PGRAPH context - for (i = 0; nv10_graph_ctx_regs[i]; i++) + for (i = 0; i < sizeof(nv10_graph_ctx_regs); i++) dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); - if ((dev_priv->chipset==0x17) - || (dev_priv->chipset==0x18) - || (dev_priv->chipset==0x1f)) - { - for (j = 0; nv17_graph_ctx_regs[j]; i++,j++) + if (dev_priv->chipset>=0x17) { + for (j = 0; j < sizeof(nv17_graph_ctx_regs); i++,j++) dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); } @@ -566,13 +561,10 @@ void nouveau_nv10_context_switch(drm_device_t *dev) // restore PGRAPH context //XXX not working yet #if 1 - for (i = 0; nv10_graph_ctx_regs[i]; i++) + for (i = 0; i < sizeof(nv10_graph_ctx_regs); i++) NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); - if ((dev_priv->chipset==0x17) - || (dev_priv->chipset==0x18) - || (dev_priv->chipset==0x1f)) - { - for (j = 0; nv17_graph_ctx_regs[j]; i++,j++) + if (dev_priv->chipset>=0x17) { + for (j = 0; j < sizeof(nv17_graph_ctx_regs); i++,j++) NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); } nouveau_wait_for_idle(dev); @@ -599,8 +591,10 @@ int nv10_graph_context_create(drm_device_t *dev, int channel) { //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; dev_priv->fifos[channel].nv10_pgraph_ctx[0] = 0x0001ffff; /* is it really needed ??? */ - dev_priv->fifos[channel].nv10_pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4); - dev_priv->fifos[channel].nv10_pgraph_ctx[2] = NV_READ(0x004006b0); + if (dev_priv->chipset>=0x17) { + dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV_PGRAPH_DEBUG_4); + dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0); + } //XXX should be saved/restored for each fifo -- cgit v1.2.3 From 55f7859a256814e3843790d88b275150f6161a26 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Fri, 2 Feb 2007 23:01:03 +0100 Subject: nouveau: nv ctx switch opps the size of array was wrong --- shared-core/nv10_graph.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 726ec6df..7270344d 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -545,10 +545,10 @@ void nouveau_nv10_context_switch(drm_device_t *dev) #endif // save PGRAPH context - for (i = 0; i < sizeof(nv10_graph_ctx_regs); i++) + for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); if (dev_priv->chipset>=0x17) { - for (j = 0; j < sizeof(nv17_graph_ctx_regs); i++,j++) + for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); } @@ -561,10 +561,10 @@ void nouveau_nv10_context_switch(drm_device_t *dev) // restore PGRAPH context //XXX not working yet #if 1 - for (i = 0; i < sizeof(nv10_graph_ctx_regs); i++) + for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); if (dev_priv->chipset>=0x17) { - for (j = 0; j < sizeof(nv17_graph_ctx_regs); i++,j++) + for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); } nouveau_wait_for_idle(dev); -- cgit v1.2.3 From 5a072f32c8f941d1ef301811881e8c89c8d8a5f1 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Sat, 3 Feb 2007 04:57:06 +0100 Subject: nouveau: rename registers to their proper names. --- shared-core/nv10_graph.c | 448 +++++++++++++++++++++++------------------------ 1 file changed, 224 insertions(+), 224 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index 7270344d..fe9a6a40 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -34,149 +34,149 @@ static void nv10_praph_pipe(drm_device_t *dev) { nouveau_wait_for_idle(dev); /* XXX check haiku comments */ - NV_WRITE(NV_PGRAPH_XFMODE0, 0x10000000); - NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x000064c0); + NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000); + NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); for (i = 0; i < 4; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); for (i = 0; i < 4; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006ab0); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); for (i = 0; i < 3; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006a80); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); for (i = 0; i < 3; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000008); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000200); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000200); for (i = 0; i < 48; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); nouveau_wait_for_idle(dev); - NV_WRITE(NV_PGRAPH_XFMODE0, 0x00000000); - NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006400); + NV_WRITE(NV10_PGRAPH_XFMODE0, 0x00000000); + NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006400); for (i = 0; i < 211; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); - - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006800); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); + + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006800); for (i = 0; i < 162; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000); for (i = 0; i < 25; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006c00); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0xbf800000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006c00); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0xbf800000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca); for (i = 0; i < 35; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007400); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007400); for (i = 0; i < 48; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007800); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007800); for (i = 0; i < 48; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00004400); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00004400); for (i = 0; i < 32; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000000); for (i = 0; i < 16; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); - NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040); + NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); for (i = 0; i < 4; i++) - NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000); + NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000); nouveau_wait_for_idle(dev); } @@ -184,18 +184,18 @@ static void nv10_praph_pipe(drm_device_t *dev) { /* TODO replace address with name use loops */ static int nv10_graph_ctx_regs [] = { -NV_PGRAPH_XY_LOGIC_MISC0, - -//NV_PGRAPH_CTX_SWITCH1, make ctx switch crash -NV_PGRAPH_CTX_SWITCH2, -NV_PGRAPH_CTX_SWITCH3, -NV_PGRAPH_CTX_SWITCH4, -NV_PGRAPH_CTX_SWITCH5, -NV_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */ -NV_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */ -NV_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */ -NV_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */ -NV_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */ +NV03_PGRAPH_XY_LOGIC_MISC0, + +//NV10_PGRAPH_CTX_SWITCH1, make ctx switch crash +NV10_PGRAPH_CTX_SWITCH2, +NV10_PGRAPH_CTX_SWITCH3, +NV10_PGRAPH_CTX_SWITCH4, +NV10_PGRAPH_CTX_SWITCH5, +NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */ +NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */ +NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */ +NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */ +NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */ 0x00400164, 0x00400184, 0x004001a4, @@ -231,44 +231,44 @@ NV_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */ 0x004001bc, 0x004001dc, 0x004001fc, -NV_PGRAPH_CTX_USER, -NV_PGRAPH_DMA_START_0, -NV_PGRAPH_DMA_START_1, -NV_PGRAPH_DMA_LENGTH, -NV_PGRAPH_DMA_MISC, -NV_PGRAPH_DMA_PITCH, -NV_PGRAPH_BOFFSET0, -NV_PGRAPH_BBASE0, -NV_PGRAPH_BLIMIT0, -NV_PGRAPH_BOFFSET1, -NV_PGRAPH_BBASE1, -NV_PGRAPH_BLIMIT1, -NV_PGRAPH_BOFFSET2, -NV_PGRAPH_BBASE2, -NV_PGRAPH_BLIMIT2, -NV_PGRAPH_BOFFSET3, -NV_PGRAPH_BBASE3, -NV_PGRAPH_BLIMIT3, -NV_PGRAPH_BOFFSET4, -NV_PGRAPH_BBASE4, -NV_PGRAPH_BLIMIT4, -NV_PGRAPH_BOFFSET5, -NV_PGRAPH_BBASE5, -NV_PGRAPH_BLIMIT5, -NV_PGRAPH_BPITCH0, -NV_PGRAPH_BPITCH1, -NV_PGRAPH_BPITCH2, -NV_PGRAPH_BPITCH3, -NV_PGRAPH_BPITCH4, -NV_PGRAPH_SURFACE, -NV_PGRAPH_STATE, -NV_PGRAPH_BSWIZZLE2, -NV_PGRAPH_BSWIZZLE5, -NV_PGRAPH_BPIXEL, -NV_PGRAPH_NOTIFY, -NV_PGRAPH_PATT_COLOR0, -NV_PGRAPH_PATT_COLOR1, -NV_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */ +NV10_PGRAPH_CTX_USER, +NV04_PGRAPH_DMA_START_0, +NV04_PGRAPH_DMA_START_1, +NV04_PGRAPH_DMA_LENGTH, +NV04_PGRAPH_DMA_MISC, +NV10_PGRAPH_DMA_PITCH, +NV04_PGRAPH_BOFFSET0, +NV04_PGRAPH_BBASE0, +NV04_PGRAPH_BLIMIT0, +NV04_PGRAPH_BOFFSET1, +NV04_PGRAPH_BBASE1, +NV04_PGRAPH_BLIMIT1, +NV04_PGRAPH_BOFFSET2, +NV04_PGRAPH_BBASE2, +NV04_PGRAPH_BLIMIT2, +NV04_PGRAPH_BOFFSET3, +NV04_PGRAPH_BBASE3, +NV04_PGRAPH_BLIMIT3, +NV04_PGRAPH_BOFFSET4, +NV04_PGRAPH_BBASE4, +NV04_PGRAPH_BLIMIT4, +NV04_PGRAPH_BOFFSET5, +NV04_PGRAPH_BBASE5, +NV04_PGRAPH_BLIMIT5, +NV04_PGRAPH_BPITCH0, +NV04_PGRAPH_BPITCH1, +NV04_PGRAPH_BPITCH2, +NV04_PGRAPH_BPITCH3, +NV04_PGRAPH_BPITCH4, +NV10_PGRAPH_SURFACE, +NV10_PGRAPH_STATE, +NV04_PGRAPH_BSWIZZLE2, +NV04_PGRAPH_BSWIZZLE5, +NV04_PGRAPH_BPIXEL, +NV10_PGRAPH_NOTIFY, +NV04_PGRAPH_PATT_COLOR0, +NV04_PGRAPH_PATT_COLOR1, +NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */ 0x00400904, 0x00400908, 0x0040090c, @@ -332,14 +332,14 @@ NV_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */ 0x004009f4, 0x004009f8, 0x004009fc, -NV_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */ +NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */ 0x0040080c, -NV_PGRAPH_PATTERN_SHAPE, -NV_PGRAPH_MONO_COLOR0, -NV_PGRAPH_ROP3, -NV_PGRAPH_CHROMA, -NV_PGRAPH_BETA_AND, -NV_PGRAPH_BETA_PREMULT, +NV04_PGRAPH_PATTERN_SHAPE, +NV03_PGRAPH_MONO_COLOR0, +NV04_PGRAPH_ROP3, +NV04_PGRAPH_CHROMA, +NV04_PGRAPH_BETA_AND, +NV04_PGRAPH_BETA_PREMULT, 0x00400e70, 0x00400e74, 0x00400e78, @@ -355,8 +355,8 @@ NV_PGRAPH_BETA_PREMULT, 0x00400e94, 0x00400e98, 0x00400e9c, -NV_PGRAPH_WINDOWCLIP_HORIZONTAL,/* 8 values from 0x400f00 to 0x400f1c */ -NV_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */ +NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00 to 0x400f1c */ +NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */ 0x00400f04, 0x00400f24, 0x00400f08, @@ -371,14 +371,14 @@ NV_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */ 0x00400f38, 0x00400f1c, 0x00400f3c, -NV_PGRAPH_XFMODE0, -NV_PGRAPH_XFMODE1, -NV_PGRAPH_GLOBALSTATE0, -NV_PGRAPH_GLOBALSTATE1, -NV_PGRAPH_STORED_FMT, -NV_PGRAPH_SOURCE_COLOR, -NV_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */ -NV_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */ +NV10_PGRAPH_XFMODE0, +NV10_PGRAPH_XFMODE1, +NV10_PGRAPH_GLOBALSTATE0, +NV10_PGRAPH_GLOBALSTATE1, +NV04_PGRAPH_STORED_FMT, +NV04_PGRAPH_SOURCE_COLOR, +NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */ +NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */ 0x00400404, 0x00400484, 0x00400408, @@ -441,27 +441,27 @@ NV_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */ 0x004004f8, 0x0040047c, 0x004004fc, -NV_PGRAPH_ABS_UCLIP_XMIN, -NV_PGRAPH_ABS_UCLIP_XMAX, -NV_PGRAPH_ABS_UCLIP_YMIN, -NV_PGRAPH_ABS_UCLIP_YMAX, +NV03_PGRAPH_ABS_UCLIP_XMIN, +NV03_PGRAPH_ABS_UCLIP_XMAX, +NV03_PGRAPH_ABS_UCLIP_YMIN, +NV03_PGRAPH_ABS_UCLIP_YMAX, 0x00400550, 0x00400558, 0x00400554, 0x0040055c, -NV_PGRAPH_ABS_UCLIPA_XMIN, -NV_PGRAPH_ABS_UCLIPA_XMAX, -NV_PGRAPH_ABS_UCLIPA_YMIN, -NV_PGRAPH_ABS_UCLIPA_YMAX, -NV_PGRAPH_ABS_ICLIP_XMAX, -NV_PGRAPH_ABS_ICLIP_YMAX, -NV_PGRAPH_XY_LOGIC_MISC1, -NV_PGRAPH_XY_LOGIC_MISC2, -NV_PGRAPH_XY_LOGIC_MISC3, -NV_PGRAPH_CLIPX_0, -NV_PGRAPH_CLIPX_1, -NV_PGRAPH_CLIPY_0, -NV_PGRAPH_CLIPY_1, +NV03_PGRAPH_ABS_UCLIPA_XMIN, +NV03_PGRAPH_ABS_UCLIPA_XMAX, +NV03_PGRAPH_ABS_UCLIPA_YMIN, +NV03_PGRAPH_ABS_UCLIPA_YMAX, +NV03_PGRAPH_ABS_ICLIP_XMAX, +NV03_PGRAPH_ABS_ICLIP_YMAX, +NV03_PGRAPH_XY_LOGIC_MISC1, +NV03_PGRAPH_XY_LOGIC_MISC2, +NV03_PGRAPH_XY_LOGIC_MISC3, +NV03_PGRAPH_CLIPX_0, +NV03_PGRAPH_CLIPX_1, +NV03_PGRAPH_CLIPY_0, +NV03_PGRAPH_CLIPY_1, 0x00400e40, 0x00400e44, 0x00400e48, @@ -490,24 +490,24 @@ NV_PGRAPH_CLIPY_1, 0x00400e34, 0x00400e38, 0x00400e3c, -NV_PGRAPH_PASSTHRU_0, -NV_PGRAPH_PASSTHRU_1, -NV_PGRAPH_PASSTHRU_2, -NV_PGRAPH_DIMX_TEXTURE, -NV_PGRAPH_WDIMX_TEXTURE, -NV_PGRAPH_DVD_COLORFMT, -NV_PGRAPH_SCALED_FORMAT, -NV_PGRAPH_MISC24_0, -NV_PGRAPH_MISC24_1, -NV_PGRAPH_MISC24_2, -NV_PGRAPH_X_MISC, -NV_PGRAPH_Y_MISC, -NV_PGRAPH_VALID1, -NV_PGRAPH_VALID2, +NV04_PGRAPH_PASSTHRU_0, +NV04_PGRAPH_PASSTHRU_1, +NV04_PGRAPH_PASSTHRU_2, +NV10_PGRAPH_DIMX_TEXTURE, +NV10_PGRAPH_WDIMX_TEXTURE, +NV10_PGRAPH_DVD_COLORFMT, +NV10_PGRAPH_SCALED_FORMAT, +NV04_PGRAPH_MISC24_0, +NV04_PGRAPH_MISC24_1, +NV04_PGRAPH_MISC24_2, +NV03_PGRAPH_X_MISC, +NV03_PGRAPH_Y_MISC, +NV04_PGRAPH_VALID1, +NV04_PGRAPH_VALID2, }; static int nv17_graph_ctx_regs [] = { -NV_PGRAPH_DEBUG_4, +NV10_PGRAPH_DEBUG_4, 0x004006b0, 0x00400eac, 0x00400eb0, @@ -532,12 +532,12 @@ void nouveau_nv10_context_switch(drm_device_t *dev) drm_nouveau_private_t *dev_priv = dev->dev_private; int channel, channel_old, i, j; - channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); - channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); + channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1); + channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1); DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); - NV_WRITE(NV_PGRAPH_FIFO,0x0); + NV_WRITE(NV04_PGRAPH_FIFO,0x0); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); @@ -554,8 +554,8 @@ void nouveau_nv10_context_switch(drm_device_t *dev) nouveau_wait_for_idle(dev); - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000); - NV_WRITE(NV_PGRAPH_CTX_USER, (NV_READ(NV_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); + NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000); + NV_WRITE(NV10_PGRAPH_CTX_USER, (NV_READ(NV10_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); nouveau_wait_for_idle(dev); // restore PGRAPH context @@ -570,16 +570,16 @@ void nouveau_nv10_context_switch(drm_device_t *dev) nouveau_wait_for_idle(dev); #endif - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100); - NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24); - NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); + NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100); + NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24); + NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); #if 0 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); NV_WRITE(NV_PFIFO_CACHES, 0x00000001); #endif - NV_WRITE(NV_PGRAPH_FIFO,0x1); + NV_WRITE(NV04_PGRAPH_FIFO,0x1); } int nv10_graph_context_create(drm_device_t *dev, int channel) { @@ -592,7 +592,7 @@ int nv10_graph_context_create(drm_device_t *dev, int channel) { dev_priv->fifos[channel].nv10_pgraph_ctx[0] = 0x0001ffff; /* is it really needed ??? */ if (dev_priv->chipset>=0x17) { - dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV_PGRAPH_DEBUG_4); + dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV10_PGRAPH_DEBUG_4); dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0); } -- cgit v1.2.3 From d69902db3b1f82dd35f5bbb3327bdf836961850c Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Sat, 3 Feb 2007 05:25:36 +0100 Subject: nouveau: fix nv04 graph routines for new register names. --- shared-core/nv10_graph.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'shared-core/nv10_graph.c') diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index fe9a6a40..ad74b840 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -546,10 +546,10 @@ void nouveau_nv10_context_switch(drm_device_t *dev) // save PGRAPH context for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); + dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); + dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]); } nouveau_wait_for_idle(dev); @@ -562,10 +562,10 @@ void nouveau_nv10_context_switch(drm_device_t *dev) //XXX not working yet #if 1 for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); + NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].pgraph_ctx[i]); if (dev_priv->chipset>=0x17) { for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].nv10_pgraph_ctx[i]); + NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].pgraph_ctx[i]); } nouveau_wait_for_idle(dev); #endif @@ -586,14 +586,14 @@ int nv10_graph_context_create(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; DRM_DEBUG("nv10_graph_context_create %d\n", channel); - memset(dev_priv->fifos[channel].nv10_pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].nv10_pgraph_ctx)); + memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx)); //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; - dev_priv->fifos[channel].nv10_pgraph_ctx[0] = 0x0001ffff; + dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff; /* is it really needed ??? */ if (dev_priv->chipset>=0x17) { - dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV10_PGRAPH_DEBUG_4); - dev_priv->fifos[channel].nv10_pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0); + dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV10_PGRAPH_DEBUG_4); + dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0); } -- cgit v1.2.3