From c806bba4665bb369168ee0b453fa28e2e0bf2a5d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 5 Jul 2007 00:12:33 +1000 Subject: nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80. --- shared-core/nv04_instmem.c | 165 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 shared-core/nv04_instmem.c (limited to 'shared-core/nv04_instmem.c') diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c new file mode 100644 index 00000000..ac7d4347 --- /dev/null +++ b/shared-core/nv04_instmem.c @@ -0,0 +1,165 @@ +#include "drmP.h" +#include "drm.h" +#include "nouveau_drv.h" + +static void +nv04_instmem_determine_amount(struct drm_device *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int i; + + /* Figure out how much instance memory we need */ + switch (dev_priv->card_type) { + case NV_40: + /* We'll want more instance memory than this on some NV4x cards. + * There's a 16MB aperture to play with that maps onto the end + * of vram. For now, only reserve a small piece until we know + * more about what each chipset requires. + */ + dev_priv->ramin_rsvd_vram = (1*1024* 1024); + break; + default: + /*XXX: what *are* the limits on ramin_rsvd_vram = (512*1024); + break; + } + DRM_DEBUG("RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram>>10); + + /* Clear all of it, except the BIOS image that's in the first 64KiB */ + for (i=(64*1024); iramin_rsvd_vram; i+=4) + NV_WI32(i, 0x00000000); +} + +static void +nv04_instmem_configure_fixed_tables(struct drm_device *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + /* FIFO hash table (RAMHT) + * use 4k hash table at RAMIN+0x10000 + * TODO: extend the hash table + */ + dev_priv->ramht_offset = 0x10000; + dev_priv->ramht_bits = 9; + dev_priv->ramht_size = (1 << dev_priv->ramht_bits); + DRM_DEBUG("RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset, + dev_priv->ramht_size); + + /* FIFO runout table (RAMRO) - 512k at 0x11200 */ + dev_priv->ramro_offset = 0x11200; + dev_priv->ramro_size = 512; + DRM_DEBUG("RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset, + dev_priv->ramro_size); + + /* FIFO context table (RAMFC) + * NV40 : Not sure exactly how to position RAMFC on some cards, + * 0x30002 seems to position it at RAMIN+0x20000 on these + * cards. RAMFC is 4kb (32 fifos, 128byte entries). + * Others: Position RAMFC at RAMIN+0x11400 + */ + switch(dev_priv->card_type) + { + case NV_40: + case NV_44: + dev_priv->ramfc_offset = 0x20000; + dev_priv->ramfc_size = nouveau_fifo_number(dev) * + nouveau_fifo_ctx_size(dev); + break; + case NV_30: + case NV_20: + case NV_17: + case NV_10: + case NV_04: + case NV_03: + default: + dev_priv->ramfc_offset = 0x11400; + dev_priv->ramfc_size = nouveau_fifo_number(dev) * + nouveau_fifo_ctx_size(dev); + break; + } + DRM_DEBUG("RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset, + dev_priv->ramfc_size); +} + +int nv04_instmem_init(struct drm_device *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t offset; + int ret = 0; + + nv04_instmem_determine_amount(dev); + nv04_instmem_configure_fixed_tables(dev); + + if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, + dev_priv->ramht_size, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ALLOW_NO_REFS, + &dev_priv->ramht, NULL))) + return ret; + + /* Create a heap to manage RAMIN allocations, we don't allocate + * the space that was reserved for RAMHT/FC/RO. + */ + offset = dev_priv->ramfc_offset + dev_priv->ramfc_size; + ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, + offset, dev_priv->ramin_rsvd_vram - offset); + if (ret) { + dev_priv->ramin_heap = NULL; + DRM_ERROR("Failed to init RAMIN heap\n"); + } + + return ret; +} + +void +nv04_instmem_takedown(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + nouveau_gpuobj_del(dev, &dev_priv->ramht); +} + +int +nv04_instmem_populate(drm_device_t *dev, nouveau_gpuobj_t *gpuobj, uint32_t *sz) +{ + if (gpuobj->im_backing) + return DRM_ERR(EINVAL); + + return 0; +} + +void +nv04_instmem_clear(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + if (gpuobj && gpuobj->im_backing) { + if (gpuobj->im_bound) + dev_priv->Engine.instmem.unbind(dev, gpuobj); + nouveau_mem_free(dev, gpuobj->im_backing); + gpuobj->im_backing = NULL; + } +} + +int +nv04_instmem_bind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +{ + if (!gpuobj->im_pramin || gpuobj->im_bound) + return DRM_ERR(EINVAL); + + gpuobj->im_bound = 1; + return 0; +} + +int +nv04_instmem_unbind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +{ + if (gpuobj->im_bound == 0) + return DRM_ERR(EINVAL); + + gpuobj->im_bound = 0; + return 0; +} + -- cgit v1.2.3 From 0029713451af6f5f216079775ff77cae9b423c0e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 13 Jul 2007 15:09:31 +1000 Subject: nouveau: nuke internal typedefs, and drm_device_t use. --- shared-core/nv04_instmem.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'shared-core/nv04_instmem.c') diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index ac7d4347..fc3b116d 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -5,7 +5,7 @@ static void nv04_instmem_determine_amount(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; int i; /* Figure out how much instance memory we need */ @@ -35,7 +35,7 @@ nv04_instmem_determine_amount(struct drm_device *dev) static void nv04_instmem_configure_fixed_tables(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; /* FIFO hash table (RAMHT) * use 4k hash table at RAMIN+0x10000 @@ -85,7 +85,7 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev) int nv04_instmem_init(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t offset; int ret = 0; @@ -114,15 +114,15 @@ int nv04_instmem_init(struct drm_device *dev) } void -nv04_instmem_takedown(drm_device_t *dev) +nv04_instmem_takedown(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; nouveau_gpuobj_del(dev, &dev_priv->ramht); } int -nv04_instmem_populate(drm_device_t *dev, nouveau_gpuobj_t *gpuobj, uint32_t *sz) +nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz) { if (gpuobj->im_backing) return DRM_ERR(EINVAL); @@ -131,9 +131,9 @@ nv04_instmem_populate(drm_device_t *dev, nouveau_gpuobj_t *gpuobj, uint32_t *sz) } void -nv04_instmem_clear(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { - drm_nouveau_private_t *dev_priv = dev->dev_private; + struct drm_nouveau_private *dev_priv = dev->dev_private; if (gpuobj && gpuobj->im_backing) { if (gpuobj->im_bound) @@ -144,7 +144,7 @@ nv04_instmem_clear(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) } int -nv04_instmem_bind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { if (!gpuobj->im_pramin || gpuobj->im_bound) return DRM_ERR(EINVAL); @@ -154,7 +154,7 @@ nv04_instmem_bind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) } int -nv04_instmem_unbind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj) +nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { if (gpuobj->im_bound == 0) return DRM_ERR(EINVAL); -- cgit v1.2.3 From bc7d6c76fab2ff4d2f11b6bd84ca8b8f124729fd Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Sat, 14 Jul 2007 18:32:11 +0200 Subject: nouveau: nv10 and nv11/15 are different --- shared-core/nv04_instmem.c | 1 + 1 file changed, 1 insertion(+) (limited to 'shared-core/nv04_instmem.c') diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index fc3b116d..7cf06269 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -70,6 +70,7 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev) case NV_30: case NV_20: case NV_17: + case NV_11: case NV_10: case NV_04: case NV_03: -- cgit v1.2.3 From e39286eb5eab8846a228863abf8f1b8b07a9e29d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 19 Jul 2007 17:00:17 -0700 Subject: Remove DRM_ERR OS macro. This was used to make all ioctl handlers return -errno on linux and errno on *BSD. Instead, just return -errno in shared code, and flip sign on return from shared code to *BSD code. --- shared-core/nv04_instmem.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'shared-core/nv04_instmem.c') diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index 7cf06269..35b20abd 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -126,7 +126,7 @@ int nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz) { if (gpuobj->im_backing) - return DRM_ERR(EINVAL); + return -EINVAL; return 0; } @@ -148,7 +148,7 @@ int nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { if (!gpuobj->im_pramin || gpuobj->im_bound) - return DRM_ERR(EINVAL); + return -EINVAL; gpuobj->im_bound = 1; return 0; @@ -158,7 +158,7 @@ int nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { if (gpuobj->im_bound == 0) - return DRM_ERR(EINVAL); + return -EINVAL; gpuobj->im_bound = 0; return 0; -- cgit v1.2.3 From 97770db72040dc032130413e0cdabc1777560a75 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2007 21:45:18 +1000 Subject: nouveau: Various internal and external API changes 1. DRM_NOUVEAU_GPUOBJ_FREE Used to free GPU objects. The obvious usage case is for Gr objects, but notifiers can also be destroyed in the same way. GPU objects gain a destructor method and private data fields with this change, so other specialised cases (like notifiers) can be implemented on top of gpuobjs. 2. DRM_NOUVEAU_CHANNEL_FREE 3. DRM_NOUVEAU_CARD_INIT Ideally we'd do init during module load, but this isn't currently possible. Doing init during firstopen() is bad as X has a love of opening/closing the DRM many times during startup. Once the modesetting-101 branch is merged this can go away. IRQs are enabled in nouveau_card_init() now, rather than having the X server call drmCtlInstHandler(). We'll need this for when we give the kernel module its own channel. 4. DRM_NOUVEAU_GETPARAM Add CHIPSET_ID value, which will return the chipset id derived from NV_PMC_BOOT_0. 4. Use list_* in a few places, rather than home-brewed stuff. --- shared-core/nv04_instmem.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'shared-core/nv04_instmem.c') diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index 35b20abd..36aa6200 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -93,13 +93,6 @@ int nv04_instmem_init(struct drm_device *dev) nv04_instmem_determine_amount(dev); nv04_instmem_configure_fixed_tables(dev); - if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, - dev_priv->ramht_size, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ALLOW_NO_REFS, - &dev_priv->ramht, NULL))) - return ret; - /* Create a heap to manage RAMIN allocations, we don't allocate * the space that was reserved for RAMHT/FC/RO. */ @@ -117,9 +110,6 @@ int nv04_instmem_init(struct drm_device *dev) void nv04_instmem_takedown(struct drm_device *dev) { - struct drm_nouveau_private *dev_priv = dev->dev_private; - - nouveau_gpuobj_del(dev, &dev_priv->ramht); } int -- cgit v1.2.3 From cf04641bc61c8bc18101713a8d95ef98e6afae7f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Aug 2007 22:05:31 +1000 Subject: nouveau: Give DRM its own gpu channel If your card doesn't have working context switching, it is now broken. --- shared-core/nv04_instmem.c | 1 - 1 file changed, 1 deletion(-) (limited to 'shared-core/nv04_instmem.c') diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index 36aa6200..5e0f6f4e 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -129,7 +129,6 @@ nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) if (gpuobj && gpuobj->im_backing) { if (gpuobj->im_bound) dev_priv->Engine.instmem.unbind(dev, gpuobj); - nouveau_mem_free(dev, gpuobj->im_backing); gpuobj->im_backing = NULL; } } -- cgit v1.2.3 From a6ea60c77e8d4a266d696e0d99c11b1f39578dcc Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 15 Aug 2007 01:40:46 +1000 Subject: nouveau: Catch all NV4x chips instead of just NV_40. --- shared-core/nv04_instmem.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'shared-core/nv04_instmem.c') diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index 5e0f6f4e..b5569b55 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -9,21 +9,18 @@ nv04_instmem_determine_amount(struct drm_device *dev) int i; /* Figure out how much instance memory we need */ - switch (dev_priv->card_type) { - case NV_40: + if (dev_priv->card_type >= NV_40) { /* We'll want more instance memory than this on some NV4x cards. * There's a 16MB aperture to play with that maps onto the end * of vram. For now, only reserve a small piece until we know * more about what each chipset requires. */ dev_priv->ramin_rsvd_vram = (1*1024* 1024); - break; - default: + } else { /*XXX: what *are* the limits on ramin_rsvd_vram = (512*1024); - break; } DRM_DEBUG("RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram>>10); -- cgit v1.2.3 From ee01d3755ac03f2c47e3b4d9bf084d68e6ee95bc Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 15 Aug 2007 13:34:57 +1000 Subject: nouveau: Workaround mysterious PRAMIN clobbering by the card. --- shared-core/nv04_instmem.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'shared-core/nv04_instmem.c') diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index b5569b55..fed6ff7e 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -94,6 +94,14 @@ int nv04_instmem_init(struct drm_device *dev) * the space that was reserved for RAMHT/FC/RO. */ offset = dev_priv->ramfc_offset + dev_priv->ramfc_size; + + /* On my NV4E, there's *something* clobbering the 16KiB just after + * where we setup these fixed tables. No idea what it is just yet, + * so reserve this space on all NV4X cards for now. + */ + if (dev_priv->card_type >= NV_40) + offset += 16*1024; + ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, offset, dev_priv->ramin_rsvd_vram - offset); if (ret) { -- cgit v1.2.3 From 69b11f44f0a0cfe0806e18dae2f360bc1ed8e005 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Thu, 30 Aug 2007 21:51:53 +0200 Subject: nouveau: give nv03 the last cut. --- shared-core/nv04_instmem.c | 1 - 1 file changed, 1 deletion(-) (limited to 'shared-core/nv04_instmem.c') diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index fed6ff7e..5a446450 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -70,7 +70,6 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev) case NV_11: case NV_10: case NV_04: - case NV_03: default: dev_priv->ramfc_offset = 0x11400; dev_priv->ramfc_size = nouveau_fifo_number(dev) * -- cgit v1.2.3