From b71f3f114e6f0e94e15958c0aa12e804392f9df2 Mon Sep 17 00:00:00 2001 From: Stuart Bennett Date: Tue, 24 Mar 2009 16:42:36 +0000 Subject: nouveau: use PFB_CSTATUS naming from ddx (reg introduced with nv10) NV04 had a PFB_FIFO_DATA at the same address, which we don't use, so remove it to reduce confusion --- shared-core/nouveau_reg.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'shared-core/nouveau_reg.h') diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 060abe0a..eade44e5 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -11,10 +11,6 @@ # define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002 # define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003 -#define NV04_FIFO_DATA 0x0010020c -# define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000 -# define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20 - #define NV_RAMIN 0x00700000 #define NV_RAMHT_HANDLE_OFFSET 0 @@ -131,7 +127,9 @@ #define NV04_PFB_CFG0 0x00100200 #define NV04_PFB_CFG1 0x00100204 -#define NV40_PFB_020C 0x0010020C +#define NV10_PFB_CSTATUS 0x0010020C +# define NV10_PFB_CSTATUS_RAM_AMOUNT_MB_MASK 0xfff00000 +# define NV10_PFB_CSTATUS_RAM_AMOUNT_MB_SHIFT 20 #define NV10_PFB_TILE(i) (0x00100240 + (i*16)) #define NV10_PFB_TILE__SIZE 8 #define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16)) -- cgit v1.2.3