From 4b43ee63f90c93701c9f1cdf7fefd1816b316d33 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 17 Oct 2006 12:33:49 +1100 Subject: NV40: *Now* fifo ctx switching works for me.. Ok, I lied before.. it was a fluke it worked and required magic to repeat it.. It actually helps to fill in RAMFC entries in the correct place. The code also clears RAMIN entirely instead of just the hash-table. --- shared-core/nouveau_fifo.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'shared-core/nouveau_fifo.c') diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index d015d420..5a7b8638 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -92,12 +92,15 @@ static void nouveau_fifo_init(drm_device_t* dev) ((dev_priv->objs.ht_bits - 9) << 16) | (dev_priv->objs.ht_base >> 8) ); - dev_priv->ramfc_offset=0x12000; - dev_priv->ramro_offset=0x11200; + /* RAMFC needs to be at RAMIN+0x20000 on NV40, I currently don't know + * how to move it.. + */ + dev_priv->ramfc_offset=0x20000; if (dev_priv->card_type < NV_40) NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); /* RAMIN+0x11000 0.5k */ else NV_WRITE(0x2220, 0x30002); + dev_priv->ramro_offset=0x11200; NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8); /* RAMIN+0x11200 0.5k */ NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); -- cgit v1.2.3