From f1edb7ad91d8b92057ffa02eb162e3740d05a147 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Wed, 30 Jan 2008 22:06:02 +0100 Subject: Simplify the fencing code and differentiate between flushes and waiting types. Add a "command_stream_barrier" method to the bo driver. --- shared-core/i915_drv.h | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'shared-core/i915_drv.h') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index c92758fa..3f6c8066 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -136,6 +136,8 @@ typedef struct drm_i915_private { uint32_t flush_flags; uint32_t flush_pending; uint32_t saved_flush_status; + uint32_t reported_sequence; + int reported_sequence_valid; #endif #ifdef I915_HAVE_BUFFER void *agp_iomap; @@ -290,15 +292,9 @@ extern void i915_mem_release(struct drm_device * dev, struct mem_block *heap); #ifdef I915_HAVE_FENCE /* i915_fence.c */ - - extern void i915_fence_handler(struct drm_device *dev); -extern int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class, - uint32_t flags, - uint32_t *sequence, - uint32_t *native_type); -extern void i915_poke_flush(struct drm_device *dev, uint32_t class); -extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags); +extern void i915_invalidate_reported_sequence(struct drm_device *dev); + #endif #ifdef I915_HAVE_BUFFER -- cgit v1.2.3 From 76748efae2f51409813eeb6b91b783c73cb2845e Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Tue, 5 Feb 2008 10:35:56 +0100 Subject: i915: Re-report breadcrumbs on poll to the fence manager, since a breadcrumb may actually turn up before a corresponding fence object has been placed on the fence ring. --- shared-core/i915_drv.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'shared-core/i915_drv.h') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 3f6c8066..87594670 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -136,8 +136,6 @@ typedef struct drm_i915_private { uint32_t flush_flags; uint32_t flush_pending; uint32_t saved_flush_status; - uint32_t reported_sequence; - int reported_sequence_valid; #endif #ifdef I915_HAVE_BUFFER void *agp_iomap; -- cgit v1.2.3 From 8b6c96dedd4ba5dfbfec6a7c831d566e31d28781 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 7 Feb 2008 10:48:08 -0800 Subject: i915: save/restore interrupt state On resume, if the interrupt state isn't restored correctly, we may end up with a flood of unexpected or ill-timed interrupts, which could cause the kernel to disable the interrupt or vblank events to happen at the wrong time. So save/restore them properly. --- shared-core/i915_drv.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'shared-core/i915_drv.h') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 87594670..d2faee29 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -166,6 +166,7 @@ typedef struct drm_i915_private { u32 saveVBLANK_A; u32 saveVSYNC_A; u32 saveBCLRPAT_A; + u32 savePIPEASTAT; u32 saveDSPASTRIDE; u32 saveDSPASIZE; u32 saveDSPAPOS; @@ -186,6 +187,7 @@ typedef struct drm_i915_private { u32 saveVBLANK_B; u32 saveVSYNC_B; u32 saveBCLRPAT_B; + u32 savePIPEBSTAT; u32 saveDSPBSTRIDE; u32 saveDSPBSIZE; u32 saveDSPBPOS; @@ -214,6 +216,9 @@ typedef struct drm_i915_private { u32 saveFBC_LL_BASE; u32 saveFBC_CONTROL; u32 saveFBC_CONTROL2; + u32 saveIER; + u32 saveIIR; + u32 saveIMR; u32 saveSWF0[16]; u32 saveSWF1[16]; u32 saveSWF2[3]; -- cgit v1.2.3 From 6f19473191ae543fcc199d252c5865c0734d38ad Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 7 Feb 2008 11:21:09 -0800 Subject: Fix saveGR array size Make sure we have enough room for all the GR registers or we'll end up clobbering the AR index register (which should actually be harmless unless the BIOS is making an assumption about it). --- shared-core/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'shared-core/i915_drv.h') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index d2faee29..d08fdf40 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -224,7 +224,7 @@ typedef struct drm_i915_private { u32 saveSWF2[3]; u8 saveMSR; u8 saveSR[8]; - u8 saveGR[24]; + u8 saveGR[25]; u8 saveAR_INDEX; u8 saveAR[20]; u8 saveDACMASK; -- cgit v1.2.3 From 373dbcf8b25750967e9ba24433cff872df41cb74 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kristian=20H=C3=B8gsberg?= Date: Tue, 5 Feb 2008 13:27:16 -0500 Subject: i915: Add a dri2 init path that gets the lock from the dri2 sarea. --- shared-core/i915_drv.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'shared-core/i915_drv.h') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index d08fdf40..76116df5 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -147,6 +147,10 @@ typedef struct drm_i915_private { drm_i915_vbl_swap_t vbl_swaps; unsigned int swaps_pending; + /* DRI2 sarea */ + struct drm_buffer_object *sarea_bo; + struct drm_bo_kmap_obj sarea_kmap; + /* Register state */ u8 saveLBB; u32 saveDSPACNTR; -- cgit v1.2.3 From 5d8c754bc2c720d70bbdeca6b294660105717a62 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Sat, 16 Feb 2008 19:19:29 -0800 Subject: [915]: more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE) Failing to preserve the MI_ARB_STATE register was causing FIFO underruns on the VGA output on my HP 2510p after resume. --- shared-core/i915_drv.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'shared-core/i915_drv.h') diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 76116df5..4d3ac0a5 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -223,6 +223,9 @@ typedef struct drm_i915_private { u32 saveIER; u32 saveIIR; u32 saveIMR; + u32 saveCACHE_MODE_0; + u32 saveDSPCLK_GATE_D; + u32 saveMI_ARB_STATE; u32 saveSWF0[16]; u32 saveSWF1[16]; u32 saveSWF2[3]; @@ -576,6 +579,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); */ #define DMA_FADD_S 0x20d4 +/* Memory Interface Arbitration State + */ +#define MI_ARB_STATE 0x20e4 + /* Cache mode 0 reg. * - Manipulating render cache behaviour is central * to the concept of zone rendering, tuning this reg can help avoid @@ -586,6 +593,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. */ #define Cache_Mode_0 0x2120 +#define CACHE_MODE_0 0x2120 #define CM0_MASK_SHIFT 16 #define CM0_IZ_OPT_DISABLE (1<<6) #define CM0_ZR_OPT_DISABLE (1<<5) @@ -775,6 +783,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); /** P1 value is 2 greater than this field */ # define VGA0_PD_P1_MASK (0x1f << 0) +#define DSPCLK_GATE_D 0x6200 + /* I830 CRTC registers */ #define HTOTAL_A 0x60000 #define HBLANK_A 0x60004 -- cgit v1.2.3