From 58d008883165ba35c83041fa9ed84937163d5f76 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 6 Sep 2013 15:58:56 -0400 Subject: radeon: pad CS to 8 DW Aligns the IB to 8 DWs. The aligns the IB to the CP fetch size. r6xx also require at least 4 DW alignment to avoid a hw bug. Signed-off-by: Alex Deucher --- radeon/radeon_cs_gem.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'radeon') diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c index b9631400..b87c6b13 100644 --- a/radeon/radeon_cs_gem.c +++ b/radeon/radeon_cs_gem.c @@ -425,6 +425,9 @@ static int cs_gem_emit(struct radeon_cs_int *cs) unsigned i; int r; + while (cs->cdw & 7) + radeon_cs_write_dword((struct radeon_cs *)cs, 0x80000000); + #if CS_BOF_DUMP cs_gem_dump_bof(cs); #endif -- cgit v1.2.3