From 1aebfdc1121ccb6babb3a63dc0b99d68b4860b04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 30 Sep 2012 19:20:04 +0200 Subject: radeon: fix stencil miptree allocation of combined ZS buffers on EG and SI This allows texturing with depth-stencil buffers directly without the copy to CB. The separate miptree description for stencil is added, because the stencil mipmap offsets are not really depth offsets/4 (at least for the texture units). Reviewed-by: Alex Deucher --- radeon/radeon_surface.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'radeon/radeon_surface.h') diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h index bfee8ab0..ed4b9941 100644 --- a/radeon/radeon_surface.h +++ b/radeon/radeon_surface.h @@ -54,6 +54,7 @@ #define RADEON_SURF_SCANOUT (1 << 16) #define RADEON_SURF_ZBUFFER (1 << 17) #define RADEON_SURF_SBUFFER (1 << 18) +#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19) #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) @@ -102,6 +103,7 @@ struct radeon_surface { uint32_t stencil_tile_split; uint64_t stencil_offset; struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL]; + struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL]; }; struct radeon_surface_manager *radeon_surface_manager_new(int fd); -- cgit v1.2.3