From ab87c5d0d1b5c35006ce8b99a9260e3116c732dc Mon Sep 17 00:00:00 2001 From: David Dawes Date: Thu, 14 Feb 2002 02:00:26 +0000 Subject: First pass of mesa-4-0 branch merge into trunk. --- linux/radeon_drv.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'linux/radeon_drv.h') diff --git a/linux/radeon_drv.h b/linux/radeon_drv.h index 5afea7d1..abbf7179 100644 --- a/linux/radeon_drv.h +++ b/linux/radeon_drv.h @@ -176,6 +176,8 @@ extern int radeon_cp_stipple( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ); extern int radeon_cp_indirect( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg ); +extern int radeon_cp_vertex2( struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg ); /* Register definitions, register access macros and drmAddMap constants @@ -306,9 +308,9 @@ extern int radeon_cp_indirect( struct inode *inode, struct file *filp, # define RADEON_Z_TEST_MASK (7 << 4) # define RADEON_Z_TEST_ALWAYS (7 << 4) # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) -# define RADEON_STENCIL_S_FAIL_KEEP (0 << 16) -# define RADEON_STENCIL_ZPASS_KEEP (0 << 20) -# define RADEON_STENCIL_ZFAIL_KEEP (0 << 20) +# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) +# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) +# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) # define RADEON_Z_WRITE_ENABLE (1 << 30) #define RADEON_RBBM_SOFT_RESET 0x00f0 # define RADEON_SOFT_RESET_CP (1 << 0) @@ -357,6 +359,7 @@ extern int radeon_cp_indirect( struct inode *inode, struct file *filp, #define RADEON_SE_CNTL_STATUS 0x2140 #define RADEON_SE_LINE_WIDTH 0x1db8 #define RADEON_SE_VPORT_XSCALE 0x1d98 +#define RADEON_SE_ZBIAS_FACTOR 0x1db0 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc #define RADEON_SURFACE_CNTL 0x0b00 @@ -482,6 +485,7 @@ extern int radeon_cp_indirect( struct inode *inode, struct file *filp, #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) +#define RADEON_PRIM_TYPE_MASK 0xf #define RADEON_PRIM_WALK_IND (1 << 4) #define RADEON_PRIM_WALK_LIST (2 << 4) #define RADEON_PRIM_WALK_RING (3 << 4) @@ -734,6 +738,11 @@ do { \ write &= mask; \ } while (0) +#define OUT_RING_REG( reg, val ) do { \ + OUT_RING( CP_PACKET0( reg, 0 ) ); \ + OUT_RING( val ); \ +} while (0) + #define RADEON_PERFORMANCE_BOXES 0 #endif /* __RADEON_DRV_H__ */ -- cgit v1.2.3