From 38f52402a8b7126f0c1ceccf7c1843b1a5247ef6 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 6 Apr 2007 03:03:59 +1000 Subject: nouveau: Power up all card units by default on startup. --- shared-core/nv04_mc.c | 5 +++++ shared-core/nv40_mc.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/shared-core/nv04_mc.c b/shared-core/nv04_mc.c index 2619eb71..0e23efb2 100644 --- a/shared-core/nv04_mc.c +++ b/shared-core/nv04_mc.c @@ -8,6 +8,11 @@ nv04_mc_init(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; + /* Power up everything, resetting each individual unit will + * be done later if needed. + */ + NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF); + NV_WRITE(NV03_PMC_INTR_EN_0, 0); return 0; diff --git a/shared-core/nv40_mc.c b/shared-core/nv40_mc.c index 554a2241..8dbd96fd 100644 --- a/shared-core/nv40_mc.c +++ b/shared-core/nv40_mc.c @@ -9,6 +9,11 @@ nv40_mc_init(drm_device_t *dev) drm_nouveau_private_t *dev_priv = dev->dev_private; uint32_t tmp; + /* Power up everything, resetting each individual unit will + * be done later if needed. + */ + NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF); + NV_WRITE(NV03_PMC_INTR_EN_0, 0); switch (dev_priv->chipset) { -- cgit v1.2.3 From 78034c06dfc0cd79cc47c2daa119ca3ee2a4fed4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 6 Apr 2007 03:24:39 +1000 Subject: nouveau: make a note about a bit that breaks some cards --- shared-core/nouveau_reg.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 3360fec2..ea4a2f6b 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -65,6 +65,10 @@ #define NV03_PMC_ENABLE 0x00000200 # define NV_PMC_ENABLE_PFIFO (1<< 8) # define NV_PMC_ENABLE_PGRAPH (1<<12) +/* Disabling the below bit breaks newer (G7X only?) mobile chipsets, + * the card will hang early on in the X init process. + */ +# define NV_PMC_ENABLE_UNK13 (1<<13) #define NV40_PMC_1700 0x00001700 #define NV40_PMC_1704 0x00001704 #define NV40_PMC_1708 0x00001708 -- cgit v1.2.3 From 46257c51c1e402cf04007f01a90cb423b141f89e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 1 Apr 2007 16:30:52 +1000 Subject: i915: use breadcrumb macro everywhere --- shared-core/i915_dma.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index aed3eea1..f66c08e6 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -643,7 +643,6 @@ static int i915_batchbuffer(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv; drm_i915_batchbuffer_t batch; @@ -669,7 +668,7 @@ static int i915_batchbuffer(DRM_IOCTL_ARGS) ret = i915_dispatch_batchbuffer(dev, &batch); - sarea_priv->last_dispatch = (int)hw_status[5]; + sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); return ret; } @@ -677,7 +676,6 @@ static int i915_cmdbuffer(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv; drm_i915_cmdbuffer_t cmdbuf; @@ -705,7 +703,7 @@ static int i915_cmdbuffer(DRM_IOCTL_ARGS) return ret; } - sarea_priv->last_dispatch = (int)hw_status[5]; + sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); return 0; } -- cgit v1.2.3 From b25558bb7377f6df6d457b50067a1d245f7911fd Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 7 Apr 2007 07:21:05 +1000 Subject: fixup install target, not sure what I was smokin... --- linux-core/Makefile | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/linux-core/Makefile b/linux-core/Makefile index effc2061..af29bd6a 100644 --- a/linux-core/Makefile +++ b/linux-core/Makefile @@ -238,9 +238,7 @@ drmstat: drmstat.c $(CC) $(PRGCFLAGS) $< -o $@ $(DRMSTATLIBS) install: - echo "Installing DRM modules to "$(O) - install *.ko $(O)/driver/char/drm - depmod -a + make -C $(LINUXDIR) $(GETCONFIG) SUBDIRS=`pwd` DRMSRCDIR=`pwd` modules_install else -- cgit v1.2.3 From a70f8e0ab265cc4a26ed2f9e92ab0618bd920a93 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Apr 2007 21:52:59 +1000 Subject: radeon: add support for reverse engineered xpress200m The IGPGART setup code was traced using mmio-trace on fglrx by myself and Phillip Ezolt on dri-devel. This code doesn't let the 3D driver work properly as the card has no vertex shader support. Thanks to Matthew Garrett + Ubuntu for providing me some hardware to do this work on. --- linux-core/ati_pcigart.c | 12 +++++++-- linux-core/drmP.h | 6 ++++- shared-core/drm_pciids.txt | 1 + shared-core/r128_cce.c | 2 +- shared-core/radeon_cp.c | 66 +++++++++++++++++++++++++++++++++++++++++++--- shared-core/radeon_drv.h | 19 +++++++++++++ 6 files changed, 98 insertions(+), 8 deletions(-) diff --git a/linux-core/ati_pcigart.c b/linux-core/ati_pcigart.c index bb30dd74..52bf8922 100644 --- a/linux-core/ati_pcigart.c +++ b/linux-core/ati_pcigart.c @@ -205,10 +205,18 @@ int drm_ati_pcigart_init(drm_device_t *dev, drm_ati_pcigart_info *gart_info) page_base = (u32) entry->busaddr[i]; for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { - if (gart_info->is_pcie) + switch(gart_info->gart_reg_if) { + case DRM_ATI_GART_IGP: + *pci_gart = cpu_to_le32((page_base) | 0xc); + break; + case DRM_ATI_GART_PCIE: *pci_gart = cpu_to_le32((page_base >> 8) | 0xc); - else + break; + default: + case DRM_ATI_GART_PCI: *pci_gart = cpu_to_le32(page_base); + break; + } pci_gart++; page_base += ATI_PCIGART_PAGE_SIZE; } diff --git a/linux-core/drmP.h b/linux-core/drmP.h index 648e29bc..d879c2a2 100644 --- a/linux-core/drmP.h +++ b/linux-core/drmP.h @@ -587,9 +587,13 @@ typedef struct drm_vbl_sig { #define DRM_ATI_GART_MAIN 1 #define DRM_ATI_GART_FB 2 +#define DRM_ATI_GART_PCI 1 +#define DRM_ATI_GART_PCIE 2 +#define DRM_ATI_GART_IGP 3 + typedef struct ati_pcigart_info { int gart_table_location; - int is_pcie; + int gart_reg_if; void *addr; dma_addr_t bus_addr; drm_local_map_t mapping; diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 5cea11a7..72c28627 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -98,6 +98,7 @@ 0x1002 0x5653 CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X700 M26" 0x1002 0x5834 CHIP_RS300|RADEON_IS_IGP "ATI Radeon RS300 9100 IGP" 0x1002 0x5835 CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS300 Mobility IGP" +0x1002 0x5955 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon XPRESS 200M 5955" 0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9250" 0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200" 0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200" diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c index 62859d5a..fc7bb8fc 100644 --- a/shared-core/r128_cce.c +++ b/shared-core/r128_cce.c @@ -563,7 +563,7 @@ static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init) dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE; dev_priv->gart_info.addr = NULL; dev_priv->gart_info.bus_addr = 0; - dev_priv->gart_info.is_pcie = 0; + dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { DRM_ERROR("failed to init PCI GART!\n"); dev->dev_private = (void *)dev_priv; diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index e02796e7..a741eb7f 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -824,12 +824,21 @@ static int RADEON_READ_PLL(drm_device_t * dev, int addr) return RADEON_READ(RADEON_CLOCK_CNTL_DATA); } -static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) +static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) { RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); return RADEON_READ(RADEON_PCIE_DATA); } +static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr) +{ + u32 ret; + RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f); + ret = RADEON_READ(RADEON_IGPGART_DATA); + RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f); + return ret; +} + #if RADEON_FIFO_DEBUG static void radeon_status(drm_radeon_private_t * dev_priv) { @@ -1266,7 +1275,45 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv) } } -/* Enable or disable PCI-E GART on the chip */ +/* Enable or disable IGP GART on the chip */ +static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) +{ + u32 temp, tmp; + + tmp = RADEON_READ(RADEON_AIC_CNTL); + DRM_DEBUG("setting igpgart AIC CNTL is %08X\n", tmp); + if (on) { + DRM_DEBUG("programming igpgart %08X %08lX %08X\n", + dev_priv->gart_vm_start, + (long)dev_priv->gart_info.bus_addr, + dev_priv->gart_size); + + RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000); + RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, 0x1); + RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800); + RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR, + dev_priv->gart_info.bus_addr); + + temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39); + RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp); + + RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start); + dev_priv->gart_size = 32*1024*1024; + RADEON_WRITE(RADEON_MC_AGP_LOCATION, + (((dev_priv->gart_vm_start - 1 + + dev_priv->gart_size) & 0xffff0000) | + (dev_priv->gart_vm_start >> 16))); + + temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_38); + RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, temp); + + RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E); + RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x1); + RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E); + RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x0); + } +} + static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) { u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); @@ -1301,6 +1348,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) { u32 tmp; + if (dev_priv->flags & RADEON_IS_IGPGART) { + radeon_set_igpgart(dev_priv, on); + return; + } + if (dev_priv->flags & RADEON_IS_PCIE) { radeon_set_pciegart(dev_priv, on); return; @@ -1635,8 +1687,10 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) dev_priv->gart_info.addr = dev_priv->gart_info.mapping.handle; - dev_priv->gart_info.is_pcie = - !!(dev_priv->flags & RADEON_IS_PCIE); + if (dev_priv->flags & RADEON_IS_PCIE) + dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; + else + dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; dev_priv->gart_info.gart_table_location = DRM_ATI_GART_FB; @@ -1644,6 +1698,10 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) dev_priv->gart_info.addr, dev_priv->pcigart_offset); } else { + if (dev_priv->flags & RADEON_IS_IGPGART) + dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; + else + dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; dev_priv->gart_info.addr = NULL; diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 3e56af30..646b2c56 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -145,6 +145,7 @@ enum radeon_chip_flags { RADEON_IS_PCIE = 0x00200000UL, RADEON_NEW_MEMMAP = 0x00400000UL, RADEON_IS_PCI = 0x00800000UL, + RADEON_IS_IGPGART = 0x01000000UL, }; #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ @@ -432,6 +433,16 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, #define RADEON_PCIE_TX_GART_END_LO 0x16 #define RADEON_PCIE_TX_GART_END_HI 0x17 +#define RADEON_IGPGART_INDEX 0x168 +#define RADEON_IGPGART_DATA 0x16c +#define RADEON_IGPGART_UNK_18 0x18 +#define RADEON_IGPGART_CTRL 0x2b +#define RADEON_IGPGART_BASE_ADDR 0x2c +#define RADEON_IGPGART_UNK_2E 0x2e +#define RADEON_IGPGART_UNK_38 0x38 +#define RADEON_IGPGART_UNK_39 0x39 + + #define RADEON_MPP_TB_CONFIG 0x01c0 #define RADEON_MEM_CNTL 0x0140 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 @@ -994,6 +1005,14 @@ do { \ RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ } while (0) +#define RADEON_WRITE_IGPGART( addr, val ) \ +do { \ + RADEON_WRITE( RADEON_IGPGART_INDEX, \ + ((addr) & 0x7f) | (1 << 8)); \ + RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \ + RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \ +} while (0) + #define RADEON_WRITE_PCIE( addr, val ) \ do { \ RADEON_WRITE8( RADEON_PCIE_INDEX, \ -- cgit v1.2.3 From 29f8fe80469a161c89c1a690ae2b62b3c21e4794 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Apr 2007 22:00:34 +1000 Subject: radeon: bump version for IGPGART support --- shared-core/radeon_drv.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 646b2c56..950f6828 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -96,10 +96,11 @@ * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, * new packet type) * 1.26- Add support for variable size PCI(E) gart aperture + * 1.27- Add support for IGP GART */ #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 26 +#define DRIVER_MINOR 27 #define DRIVER_PATCHLEVEL 0 /* -- cgit v1.2.3 From 2d7f9f59c3ae9dbaa516ee45ae26b32825e7bf3e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 9 Apr 2007 23:20:26 +1000 Subject: nouveau: NV46 support --- shared-core/nv40_graph.c | 189 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 188 insertions(+), 1 deletion(-) diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c index 5d5d0dc7..792734ed 100644 --- a/shared-core/nv40_graph.c +++ b/shared-core/nv40_graph.c @@ -10,6 +10,7 @@ */ #define NV40_GRCTX_SIZE (175*1024) #define NV43_GRCTX_SIZE (70*1024) +#define NV46_GRCTX_SIZE (70*1024) /* probably ~64KiB */ #define NV4A_GRCTX_SIZE (64*1024) #define NV4C_GRCTX_SIZE (25*1024) #define NV4E_GRCTX_SIZE (25*1024) @@ -274,6 +275,156 @@ nv43_graph_context_init(drm_device_t *dev, struct mem_block *ctx) INSTANCE_WR(ctx, i/4, 0x3f800000); }; +static void nv46_graph_context_init(drm_device_t *dev, struct mem_block *ctx) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int i; + + INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx)); + INSTANCE_WR(ctx, 0x00040/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00044/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x0004c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00138/4, 0x20010001); + INSTANCE_WR(ctx, 0x0013c/4, 0x0f73ef00); + INSTANCE_WR(ctx, 0x00144/4, 0x02008821); + INSTANCE_WR(ctx, 0x00174/4, 0x00000001); + INSTANCE_WR(ctx, 0x00178/4, 0x00000001); + INSTANCE_WR(ctx, 0x0017c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00180/4, 0x00000001); + INSTANCE_WR(ctx, 0x00184/4, 0x00000001); + INSTANCE_WR(ctx, 0x00188/4, 0x00000001); + INSTANCE_WR(ctx, 0x0018c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00190/4, 0x00000001); + INSTANCE_WR(ctx, 0x00194/4, 0x00000040); + INSTANCE_WR(ctx, 0x00198/4, 0x00000040); + INSTANCE_WR(ctx, 0x0019c/4, 0x00000040); + INSTANCE_WR(ctx, 0x001a4/4, 0x00000040); + INSTANCE_WR(ctx, 0x001ec/4, 0x0b0b0b0c); + INSTANCE_WR(ctx, 0x0035c/4, 0x00040000); + INSTANCE_WR(ctx, 0x0036c/4, 0x55555555); + INSTANCE_WR(ctx, 0x00370/4, 0x55555555); + INSTANCE_WR(ctx, 0x00374/4, 0x55555555); + INSTANCE_WR(ctx, 0x00378/4, 0x55555555); + INSTANCE_WR(ctx, 0x003a4/4, 0x00000008); + INSTANCE_WR(ctx, 0x003b8/4, 0x00003010); + INSTANCE_WR(ctx, 0x003dc/4, 0x00000111); + INSTANCE_WR(ctx, 0x003e0/4, 0x00000111); + INSTANCE_WR(ctx, 0x003e4/4, 0x00000111); + INSTANCE_WR(ctx, 0x003e8/4, 0x00000111); + INSTANCE_WR(ctx, 0x003ec/4, 0x00000111); + INSTANCE_WR(ctx, 0x003f0/4, 0x00000111); + INSTANCE_WR(ctx, 0x003f4/4, 0x00000111); + INSTANCE_WR(ctx, 0x003f8/4, 0x00000111); + INSTANCE_WR(ctx, 0x003fc/4, 0x00000111); + INSTANCE_WR(ctx, 0x00400/4, 0x00000111); + INSTANCE_WR(ctx, 0x00404/4, 0x00000111); + INSTANCE_WR(ctx, 0x00408/4, 0x00000111); + INSTANCE_WR(ctx, 0x0040c/4, 0x00000111); + INSTANCE_WR(ctx, 0x00410/4, 0x00000111); + INSTANCE_WR(ctx, 0x00414/4, 0x00000111); + INSTANCE_WR(ctx, 0x00418/4, 0x00000111); + INSTANCE_WR(ctx, 0x004b0/4, 0x00000111); + INSTANCE_WR(ctx, 0x004b4/4, 0x00080060); + INSTANCE_WR(ctx, 0x004d0/4, 0x00000080); + INSTANCE_WR(ctx, 0x004d4/4, 0xffff0000); + INSTANCE_WR(ctx, 0x004d8/4, 0x00000001); + INSTANCE_WR(ctx, 0x004ec/4, 0x46400000); + INSTANCE_WR(ctx, 0x004fc/4, 0xffff0000); + INSTANCE_WR(ctx, 0x00500/4, 0x88888888); + INSTANCE_WR(ctx, 0x00504/4, 0x88888888); + INSTANCE_WR(ctx, 0x00508/4, 0x88888888); + INSTANCE_WR(ctx, 0x0050c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00510/4, 0x88888888); + INSTANCE_WR(ctx, 0x00514/4, 0x88888888); + INSTANCE_WR(ctx, 0x00518/4, 0x88888888); + INSTANCE_WR(ctx, 0x0051c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00520/4, 0x88888888); + INSTANCE_WR(ctx, 0x00524/4, 0x88888888); + INSTANCE_WR(ctx, 0x00528/4, 0x88888888); + INSTANCE_WR(ctx, 0x0052c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00530/4, 0x88888888); + INSTANCE_WR(ctx, 0x00534/4, 0x88888888); + INSTANCE_WR(ctx, 0x00538/4, 0x88888888); + INSTANCE_WR(ctx, 0x0053c/4, 0x88888888); + INSTANCE_WR(ctx, 0x00550/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x00554/4, 0x0fff0000); + INSTANCE_WR(ctx, 0x0055c/4, 0x00011100); + for (i=0x00578; i<0x005b4; i+=4) + INSTANCE_WR(ctx, i/4, 0x07ff0000); + INSTANCE_WR(ctx, 0x005c0/4, 0x4b7fffff); + INSTANCE_WR(ctx, 0x005e8/4, 0x30201000); + INSTANCE_WR(ctx, 0x005ec/4, 0x70605040); + INSTANCE_WR(ctx, 0x005f0/4, 0xb8a89888); + INSTANCE_WR(ctx, 0x005f4/4, 0xf8e8d8c8); + INSTANCE_WR(ctx, 0x00608/4, 0x40100000); + INSTANCE_WR(ctx, 0x00624/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00658/4, 0x435185d6); + INSTANCE_WR(ctx, 0x0065c/4, 0x2155b699); + INSTANCE_WR(ctx, 0x00660/4, 0xfedcba98); + INSTANCE_WR(ctx, 0x00664/4, 0x00000098); + INSTANCE_WR(ctx, 0x00674/4, 0xffffffff); + INSTANCE_WR(ctx, 0x00678/4, 0x00ff7000); + INSTANCE_WR(ctx, 0x0067c/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x0068c/4, 0x00ff0000); + INSTANCE_WR(ctx, 0x006c8/4, 0x00ffff00); + for (i=0x0070c; i<=0x00748; i+=4) + INSTANCE_WR(ctx, i/4, 0x00018488); + for (i=0x0074c; i<=0x00788; i+=4) + INSTANCE_WR(ctx, i/4, 0x00028202); + for (i=0x007cc; i<=0x00808; i+=4) + INSTANCE_WR(ctx, i/4, 0x0000aae4); + for (i=0x0080c; i<=0x00848; i+=4) + INSTANCE_WR(ctx, i/4, 0x01012000); + for (i=0x0084c; i<=0x00888; i+=4) + INSTANCE_WR(ctx, i/4, 0x00080008); + for (i=0x008cc; i<=0x00908; i+=4) + INSTANCE_WR(ctx, i/4, 0x00100008); + for (i=0x0095c; i<=0x00968; i+=4) + INSTANCE_WR(ctx, i/4, 0x0001bc80); + for (i=0x0096c; i<=0x00978; i+=4) + INSTANCE_WR(ctx, i/4, 0x00000202); + for (i=0x0098c; i<=0x00998; i+=4) + INSTANCE_WR(ctx, i/4, 0x00000008); + for (i=0x009ac; i<=0x009b8; i+=4) + INSTANCE_WR(ctx, i/4, 0x00080008); + INSTANCE_WR(ctx, 0x009cc/4, 0x00000002); + INSTANCE_WR(ctx, 0x00a00/4, 0x00000421); + INSTANCE_WR(ctx, 0x00a04/4, 0x030c30c3); + INSTANCE_WR(ctx, 0x00a08/4, 0x00011001); + INSTANCE_WR(ctx, 0x00a14/4, 0x3e020200); + INSTANCE_WR(ctx, 0x00a18/4, 0x00ffffff); + INSTANCE_WR(ctx, 0x00a1c/4, 0x0c103f00); + INSTANCE_WR(ctx, 0x00a28/4, 0x00040000); + INSTANCE_WR(ctx, 0x00a60/4, 0x00008100); + INSTANCE_WR(ctx, 0x00aec/4, 0x00000001); + INSTANCE_WR(ctx, 0x00b30/4, 0x00001001); + INSTANCE_WR(ctx, 0x00b38/4, 0x00000003); + INSTANCE_WR(ctx, 0x00b3c/4, 0x00888001); + INSTANCE_WR(ctx, 0x00bc0/4, 0x00000005); + INSTANCE_WR(ctx, 0x00bcc/4, 0x0000ffff); + INSTANCE_WR(ctx, 0x00be8/4, 0x00005555); + INSTANCE_WR(ctx, 0x00bec/4, 0x00005555); + INSTANCE_WR(ctx, 0x00bf0/4, 0x00005555); + INSTANCE_WR(ctx, 0x00bf4/4, 0x00000001); + INSTANCE_WR(ctx, 0x00c2c/4, 0x00000001); + INSTANCE_WR(ctx, 0x00c30/4, 0x08e00001); + INSTANCE_WR(ctx, 0x00c34/4, 0x000e3000); + for (i=0x017f8; i<=0x01870; i+=8) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i=0x035b8; i<=0x057a8; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i=0x057b8; i<=0x05ba8; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i=0x07f38; i<=0x0a128; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i=0x0a138; i<=0x0a528; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); + for (i=0x0c8b8; i<=0x0eaa8; i+=24) + INSTANCE_WR(ctx, i/4, 0x00000001); + for (i=0x0eab8; i<=0x0eea8; i+=16) + INSTANCE_WR(ctx, i/4, 0x3f800000); +} + static void nv4a_graph_context_init(drm_device_t *dev, struct mem_block *ctx) { drm_nouveau_private_t *dev_priv = dev->dev_private; @@ -622,6 +773,10 @@ nv40_graph_context_create(drm_device_t *dev, int channel) ctx_size = NV43_GRCTX_SIZE; ctx_init = nv43_graph_context_init; break; + case 0x46: + ctx_size = NV46_GRCTX_SIZE; + ctx_init = nv46_graph_context_init; + break; case 0x4a: ctx_size = NV4A_GRCTX_SIZE; ctx_init = nv4a_graph_context_init; @@ -821,6 +976,37 @@ static uint32_t nv43_ctx_voodoo[] = { ~0 }; +static uint32_t nv46_ctx_voodoo[] = { + 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, + 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306, + 0x0040a068, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042, + 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968, + 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, + 0x004020e6, 0x007000a0, 0x00500060, 0x00200008, 0x0060000a, 0x0011814d, + 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, + 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, + 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, + 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, + 0x00500060, 0x00403f87, 0x0060000d, 0x004079e6, 0x002000f7, 0x0060000a, + 0x00200045, 0x00100620, 0x00104668, 0x0017466d, 0x0011068b, 0x00168691, + 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, 0x00200022, + 0x001006cc, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, 0x001043e1, + 0x00500060, 0x0020027f, 0x0060000a, 0x00104800, 0x00108901, 0x00104910, + 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00, 0x00108a14, + 0x00160b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, 0x0010cd08, 0x00104d80, + 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, 0x00105406, 0x00105709, + 0x00200316, 0x0060000a, 0x00300000, 0x00200080, 0x00407200, 0x00200084, + 0x00800001, 0x0020055e, 0x0060000a, 0x002037e0, 0x0040788a, 0x00201320, + 0x00800029, 0x00408900, 0x00600006, 0x004085e6, 0x00700080, 0x00200081, + 0x0060000a, 0x00104280, 0x00200316, 0x0060000a, 0x00200004, 0x00800001, + 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a068, 0x00700000, + 0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060, + 0x00600007, 0x00409388, 0x0060000f, 0x00500060, 0x00200000, 0x0060000a, + 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020, + 0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a206, 0x0040a305, + 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0 +}; + static uint32_t nv4a_ctx_voodoo[] = { 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001, 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409965, 0x00409e06, @@ -891,7 +1077,7 @@ static uint32_t nv4e_ctx_voodoo[] = { * G70 0x47 * G71 0x49 * NV45 0x48 - * G72 0x46 + * G72[M] 0x46 * G73 0x4b * C51_G7X 0x4c * C51 0x4e @@ -913,6 +1099,7 @@ nv40_graph_init(drm_device_t *dev) switch (dev_priv->chipset) { case 0x40: ctx_voodoo = nv40_ctx_voodoo; break; case 0x43: ctx_voodoo = nv43_ctx_voodoo; break; + case 0x46: ctx_voodoo = nv46_ctx_voodoo; break; case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break; case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break; default: -- cgit v1.2.3 From 059b5d90770e32ba3d6d9a62acf74b352de7f421 Mon Sep 17 00:00:00 2001 From: Oliver McFadden Date: Mon, 9 Apr 2007 23:23:40 +0000 Subject: rs480: Renamed some unknown registers. See dri-devel list. --- shared-core/radeon_cp.c | 14 +++++++------- shared-core/radeon_drv.h | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index a741eb7f..bfc2d088 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -1289,7 +1289,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) dev_priv->gart_size); RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000); - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, 0x1); + RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1); RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800); RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR, dev_priv->gart_info.bus_addr); @@ -1304,13 +1304,13 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) dev_priv->gart_size) & 0xffff0000) | (dev_priv->gart_vm_start >> 16))); - temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_38); - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_38, temp); + temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE); + RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp); - RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E); - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x1); - RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_2E); - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_2E, 0x0); + RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); + RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1); + RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); + RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0); } } diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 950f6828..00646c8f 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -439,8 +439,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, #define RADEON_IGPGART_UNK_18 0x18 #define RADEON_IGPGART_CTRL 0x2b #define RADEON_IGPGART_BASE_ADDR 0x2c -#define RADEON_IGPGART_UNK_2E 0x2e -#define RADEON_IGPGART_UNK_38 0x38 +#define RADEON_IGPGART_FLUSH 0x2e +#define RADEON_IGPGART_ENABLE 0x38 #define RADEON_IGPGART_UNK_39 0x39 -- cgit v1.2.3 From 9b7211dd6793dc62d11ad1ae980b22fa2d61f9dd Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Tue, 10 Apr 2007 23:19:29 +0200 Subject: nouveau: nv10 per channel init from ddx --- shared-core/nv10_graph.c | 99 +++++++++++++++++++++++++++++++++--------------- 1 file changed, 69 insertions(+), 30 deletions(-) diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c index db2757d7..4cc44e21 100644 --- a/shared-core/nv10_graph.c +++ b/shared-core/nv10_graph.c @@ -527,6 +527,37 @@ NV10_PGRAPH_DEBUG_4, 0x00400a04, }; +static int nv10_graph_ctx_regs_find_offset(drm_device_t *dev, int reg) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int i, j; + for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) { + if (nv10_graph_ctx_regs[i] == reg) + return i; + } + if (dev_priv->chipset>=0x17) { + for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) { + if (nv17_graph_ctx_regs[j] == reg) + return i; + } + } + return -1; +} + +static void restore_ctx_regs(drm_device_t *dev, int channel) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *fifo = &dev_priv->fifos[channel]; + int i, j; + for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) + NV_WRITE(nv10_graph_ctx_regs[i], fifo->pgraph_ctx[i]); + if (dev_priv->chipset>=0x17) { + for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) + NV_WRITE(nv17_graph_ctx_regs[j], fifo->pgraph_ctx[i]); + } + nouveau_wait_for_idle(dev); +} + void nouveau_nv10_context_switch(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; @@ -559,15 +590,8 @@ void nouveau_nv10_context_switch(drm_device_t *dev) nouveau_wait_for_idle(dev); // restore PGRAPH context - //XXX not working yet #if 1 - for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) - NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].pgraph_ctx[i]); - if (dev_priv->chipset>=0x17) { - for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) - NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].pgraph_ctx[i]); - } - nouveau_wait_for_idle(dev); + restore_ctx_regs(dev, channel); #endif NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100); @@ -582,20 +606,52 @@ void nouveau_nv10_context_switch(drm_device_t *dev) NV_WRITE(NV04_PGRAPH_FIFO,0x1); } +#define NV_WRITE_CTX(reg, val) do { \ + int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \ + if (offset > 0) \ + fifo->pgraph_ctx[offset] = val; \ + } while (0) int nv10_graph_context_create(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_fifo *fifo = &dev_priv->fifos[channel]; + uint32_t tmp, vramsz; + DRM_DEBUG("nv10_graph_context_create %d\n", channel); - memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx)); + memset(fifo->pgraph_ctx, 0, sizeof(fifo->pgraph_ctx)); + + /* per channel init from ddx */ + tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; + /*XXX the original ddx code, does this in 2 steps : + * tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; + * NV_WRITE(NV10_PGRAPH_SURFACE, tmp); + * tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100; + * NV_WRITE(NV10_PGRAPH_SURFACE, tmp); + */ + tmp |= 0x00020100; + NV_WRITE_CTX(NV10_PGRAPH_SURFACE, tmp); + + vramsz = drm_get_resource_len(dev, 0) - 1; + NV_WRITE_CTX(NV04_PGRAPH_BOFFSET0, 0); + NV_WRITE_CTX(NV04_PGRAPH_BOFFSET1, 0); + NV_WRITE_CTX(NV04_PGRAPH_BLIMIT0 , vramsz); + NV_WRITE_CTX(NV04_PGRAPH_BLIMIT1 , vramsz); + + NV_WRITE_CTX(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); + NV_WRITE_CTX(NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); - //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; - dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff; + + NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff); /* is it really needed ??? */ if (dev_priv->chipset>=0x17) { - dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV10_PGRAPH_DEBUG_4); - dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0); + NV_WRITE_CTX(NV10_PGRAPH_DEBUG_4, NV_READ(NV10_PGRAPH_DEBUG_4)); + NV_WRITE_CTX(0x004006b0, NV_READ(0x004006b0)); } + /* for the first channel init the regs */ + if (dev_priv->fifo_alloc_count == 0) + restore_ctx_regs(dev, channel); + //XXX should be saved/restored for each fifo //we supposed here we have X fifo and only one 3D fifo. @@ -606,7 +662,6 @@ int nv10_graph_context_create(drm_device_t *dev, int channel) { int nv10_graph_init(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t tmp, vramsz; int i; NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & @@ -637,23 +692,7 @@ int nv10_graph_init(drm_device_t *dev) { NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF); NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001); - /* the below don't belong here, per-channel context state */ - tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00; - NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100; - NV_WRITE(NV10_PGRAPH_SURFACE, tmp); - - vramsz = drm_get_resource_len(dev, 0) - 1; - NV_WRITE(NV04_PGRAPH_BOFFSET0, 0); - NV_WRITE(NV04_PGRAPH_BOFFSET1, 0); - NV_WRITE(NV04_PGRAPH_BLIMIT0 , vramsz); - NV_WRITE(NV04_PGRAPH_BLIMIT1 , vramsz); - - NV_WRITE(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); - NV_WRITE(NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); - return 0; - } void nv10_graph_takedown(drm_device_t *dev) -- cgit v1.2.3 From a85440c8a6cac3de4b0e50805fa30cdce40e311b Mon Sep 17 00:00:00 2001 From: Alan Hourihane Date: Thu, 12 Apr 2007 15:11:38 +0100 Subject: Remove extraneous drm_crtc.h include --- linux-core/drmP.h | 1 - 1 file changed, 1 deletion(-) diff --git a/linux-core/drmP.h b/linux-core/drmP.h index ac0bd767..0d0ec992 100644 --- a/linux-core/drmP.h +++ b/linux-core/drmP.h @@ -75,7 +75,6 @@ #include #include #include "drm.h" -#include "drm_crtc.h" #include #define __OS_HAS_AGP (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE))) -- cgit v1.2.3 From cf016891435a0aa74dc4909ed4125c7ed906b7d1 Mon Sep 17 00:00:00 2001 From: Alan Hourihane Date: Thu, 12 Apr 2007 15:12:00 +0100 Subject: Use drm_framebuffer instead of drm_crtc for fb & fbt --- linux-core/drm_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-core/drm_crtc.c b/linux-core/drm_crtc.c index 2f140dbd..ef025922 100644 --- a/linux-core/drm_crtc.c +++ b/linux-core/drm_crtc.c @@ -582,7 +582,7 @@ void drm_mode_config_cleanup(drm_device_t *dev) { struct drm_output *output, *ot; struct drm_crtc *crtc, *ct; - struct drm_crtc *fb, *fbt; + struct drm_framebuffer *fb, *fbt; list_for_each_entry_safe(output, ot, &dev->mode_config.output_list, head) { drm_output_destroy(output); } -- cgit v1.2.3