From e32fff8e9ea8d522679eaab21a9555cab134fb36 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <maraeo@gmail.com>
Date: Tue, 16 Oct 2012 02:08:02 +0200
Subject: radeon: fix tile_split of 128-bit surface formats with 8x MSAA
The calculation led to the number 8192, which is too high.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
radeon/radeon_surface.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 66c24449..eb587d24 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man,
} else {
/* tile split must be >= 256 for colorbuffer surfaces */
surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
+ if (surf->tile_split > 4096)
+ surf->tile_split = 4096;
}
} else {
/* set tile split to row size */
--
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