From b486ed7f7d89528c94f2345040324946f6eadc81 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 12 Aug 2008 13:52:35 -0400
Subject: Get legacy working finally
- extra ~ in RADEON_WRITE_P()
- re-arrange crtc setup a bit
- add debugging for tracing calls
- fix pitch calculation
---
linux-core/radeon_legacy_crtc.c | 74 ++++++++++++++++++++++---------------
linux-core/radeon_legacy_encoders.c | 38 ++++++++++++++++++-
shared-core/radeon_drv.h | 2 +-
3 files changed, 83 insertions(+), 31 deletions(-)
diff --git a/linux-core/radeon_legacy_crtc.c b/linux-core/radeon_legacy_crtc.c
index 7f7ce617..6dea4d41 100644
--- a/linux-core/radeon_legacy_crtc.c
+++ b/linux-core/radeon_legacy_crtc.c
@@ -123,42 +123,43 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct drm_radeon_private *dev_priv = dev->dev_private;
-
uint32_t mask;
+ DRM_DEBUG("\n");
+
mask = radeon_crtc->crtc_id ?
(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) :
(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS);
switch(mode) {
case DRM_MODE_DPMS_ON:
- if (radeon_crtc->crtc_id) {
+ if (radeon_crtc->crtc_id)
RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, 0, ~mask);
- } else {
+ else {
RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
}
break;
case DRM_MODE_DPMS_STANDBY:
- if (radeon_crtc->crtc_id) {
+ if (radeon_crtc->crtc_id)
RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), ~mask);
- } else {
+ else {
RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS), ~mask);
}
break;
case DRM_MODE_DPMS_SUSPEND:
- if (radeon_crtc->crtc_id) {
+ if (radeon_crtc->crtc_id)
RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), ~mask);
- } else {
+ else {
RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS), ~mask);
}
break;
case DRM_MODE_DPMS_OFF:
- if (radeon_crtc->crtc_id) {
+ if (radeon_crtc->crtc_id)
RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
- } else {
+ else {
RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~RADEON_CRTC_DISP_REQ_EN_B);
RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
}
@@ -179,6 +180,9 @@ static bool radeon_set_crtc1_base(struct drm_crtc *crtc, int x, int y)
struct drm_radeon_gem_object *obj_priv;
uint32_t base;
uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
+ uint32_t crtc_pitch;
+
+ DRM_DEBUG("\n");
radeon_fb = to_radeon_framebuffer(crtc->fb);
@@ -243,11 +247,20 @@ static bool radeon_set_crtc1_base(struct drm_crtc *crtc, int x, int y)
crtc_offset = base;
+ crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
+ ((crtc->fb->bits_per_pixel * 8) - 1)) /
+ (crtc->fb->bits_per_pixel * 8));
+ crtc_pitch |= crtc_pitch << 16;
+
+ DRM_DEBUG("mc_fb_location: 0x%x\n", dev_priv->fb_location);
+
+ RADEON_WRITE(RADEON_DISPLAY_BASE_ADDR, dev_priv->fb_location);
+
if (radeon_is_r300(dev_priv))
RADEON_WRITE(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
-
RADEON_WRITE(RADEON_CRTC_OFFSET_CNTL, crtc_offset_cntl);
RADEON_WRITE(RADEON_CRTC_OFFSET, crtc_offset);
+ RADEON_WRITE(RADEON_CRTC_PITCH, crtc_pitch);
return true;
}
@@ -267,10 +280,11 @@ static bool radeon_set_crtc1_timing(struct drm_crtc *crtc, struct drm_display_mo
uint32_t crtc_h_sync_strt_wid;
uint32_t crtc_v_total_disp;
uint32_t crtc_v_sync_strt_wid;
- uint32_t crtc_pitch;
uint32_t disp_merge_cntl;
- switch (crtc->fb->depth) {
+ DRM_DEBUG("\n");
+
+ switch (crtc->fb->bits_per_pixel) {
case 15: /* 555 */
format = 3;
@@ -302,7 +316,7 @@ static bool radeon_set_crtc1_timing(struct drm_crtc *crtc, struct drm_display_mo
: 0));
crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
- crtc_ext_cntl |= (RADEON_XCRT_CNT_EN|
+ crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
RADEON_CRTC_VSYNC_DIS |
RADEON_CRTC_HSYNC_DIS |
RADEON_CRTC_DISPLAY_DIS);
@@ -338,11 +352,6 @@ static bool radeon_set_crtc1_timing(struct drm_crtc *crtc, struct drm_display_mo
? RADEON_CRTC_V_SYNC_POL
: 0));
- crtc_pitch = (((crtc->fb->pitch * crtc->fb->bits_per_pixel) +
- ((crtc->fb->bits_per_pixel * 8) -1)) /
- (crtc->fb->bits_per_pixel * 8));
- crtc_pitch |= crtc_pitch << 16;
-
/* TODO -> Dell Server */
if (0) {
uint32_t disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
@@ -381,7 +390,6 @@ static bool radeon_set_crtc1_timing(struct drm_crtc *crtc, struct drm_display_mo
RADEON_WRITE(RADEON_CRTC_V_TOTAL_DISP, crtc_v_total_disp);
RADEON_WRITE(RADEON_CRTC_V_SYNC_STRT_WID, crtc_v_sync_strt_wid);
- RADEON_WRITE(RADEON_CRTC_PITCH, crtc_pitch);
RADEON_WRITE(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
@@ -569,7 +577,7 @@ static void radeon_set_pll1(struct drm_crtc *crtc, struct drm_display_mode *mode
RADEON_VCLK_SRC_SEL_PPLLCLK,
~(RADEON_VCLK_SRC_SEL_MASK));
- /*RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, state->vclk_ecp_cntl);*/
+ /*RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);*/
}
@@ -580,8 +588,11 @@ static bool radeon_set_crtc2_base(struct drm_crtc *crtc, int x, int y)
struct drm_radeon_private *dev_priv = dev->dev_private;
struct radeon_framebuffer *radeon_fb;
struct drm_radeon_gem_object *obj_priv;
- uint32_t crtc2_offset, crtc2_offset_cntl, crtc2_tile_x0_y0 = 0;
uint32_t base;
+ uint32_t crtc2_offset, crtc2_offset_cntl, crtc2_tile_x0_y0 = 0;
+ uint32_t crtc2_pitch;
+
+ DRM_DEBUG("\n");
radeon_fb = to_radeon_framebuffer(crtc->fb);
@@ -646,10 +657,18 @@ static bool radeon_set_crtc2_base(struct drm_crtc *crtc, int x, int y)
crtc2_offset = base;
+ crtc2_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
+ ((crtc->fb->bits_per_pixel * 8) - 1)) /
+ (crtc->fb->bits_per_pixel * 8));
+ crtc2_pitch |= crtc2_pitch << 16;
+
+ RADEON_WRITE(RADEON_DISPLAY2_BASE_ADDR, dev_priv->fb_location);
+
if (radeon_is_r300(dev_priv))
RADEON_WRITE(R300_CRTC2_TILE_X0_Y0, crtc2_tile_x0_y0);
RADEON_WRITE(RADEON_CRTC2_OFFSET_CNTL, crtc2_offset_cntl);
RADEON_WRITE(RADEON_CRTC2_OFFSET, crtc2_offset);
+ RADEON_WRITE(RADEON_CRTC2_PITCH, crtc2_pitch);
return true;
}
@@ -668,12 +687,13 @@ static bool radeon_set_crtc2_timing(struct drm_crtc *crtc, struct drm_display_mo
uint32_t crtc2_h_sync_strt_wid;
uint32_t crtc2_v_total_disp;
uint32_t crtc2_v_sync_strt_wid;
- uint32_t crtc2_pitch;
uint32_t disp2_merge_cntl;
uint32_t fp_h2_sync_strt_wid;
uint32_t fp_v2_sync_strt_wid;
- switch (crtc->fb->depth) {
+ DRM_DEBUG("\n");
+
+ switch (crtc->fb->bits_per_pixel) {
case 15: /* 555 */
format = 3;
@@ -720,11 +740,6 @@ static bool radeon_set_crtc2_timing(struct drm_crtc *crtc, struct drm_display_mo
? RADEON_CRTC2_V_SYNC_POL
: 0));
- crtc2_pitch = (((crtc->fb->pitch * crtc->fb->bits_per_pixel) +
- ((crtc->fb->bits_per_pixel * 8) -1)) /
- (crtc->fb->bits_per_pixel * 8));
- crtc2_pitch |= crtc2_pitch << 16;
-
/* check to see if TV DAC is enabled for another crtc and keep it enabled */
if (RADEON_READ(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
@@ -765,7 +780,6 @@ static bool radeon_set_crtc2_timing(struct drm_crtc *crtc, struct drm_display_mo
RADEON_WRITE(RADEON_FP_H2_SYNC_STRT_WID, fp_h2_sync_strt_wid);
RADEON_WRITE(RADEON_FP_V2_SYNC_STRT_WID, fp_v2_sync_strt_wid);
- RADEON_WRITE(RADEON_CRTC2_PITCH, crtc2_pitch);
RADEON_WRITE(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
@@ -944,6 +958,8 @@ static void radeon_crtc_mode_set(struct drm_crtc *crtc,
int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV;
int i;
+ DRM_DEBUG("\n");
+
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
diff --git a/linux-core/radeon_legacy_encoders.c b/linux-core/radeon_legacy_encoders.c
index 46cf791e..998a9f73 100644
--- a/linux-core/radeon_legacy_encoders.c
+++ b/linux-core/radeon_legacy_encoders.c
@@ -47,6 +47,7 @@ static void radeon_legacy_rmx_mode_set(struct drm_encoder *encoder,
uint32_t fp_horz_stretch, fp_vert_stretch, crtc_more_cntl, fp_horz_vert_active;
uint32_t fp_h_sync_strt_wid, fp_v_sync_strt_wid, fp_crtc_h_total_disp, fp_crtc_v_total_disp;
+ DRM_DEBUG("\n");
fp_vert_stretch = RADEON_READ(RADEON_FP_VERT_STRETCH) &
(RADEON_VERT_STRETCH_RESERVED |
@@ -199,7 +200,9 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
- switch(mode) {
+ DRM_DEBUG("\n");
+
+ switch (mode) {
case DRM_MODE_DPMS_ON:
disp_pwr_man = RADEON_READ(RADEON_DISP_PWR_MAN);
disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
@@ -250,6 +253,8 @@ static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
uint32_t lvds_pll_cntl, lvds_gen_cntl;
+ DRM_DEBUG("\n");
+
if (radeon_crtc->crtc_id == 0)
radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
@@ -319,6 +324,9 @@ struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int b
struct radeon_mode_info *mode_info = &dev_priv->mode_info;
struct radeon_encoder *radeon_encoder;
struct drm_encoder *encoder;
+
+ DRM_DEBUG("\n");
+
radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
if (!radeon_encoder) {
return NULL;
@@ -358,6 +366,8 @@ static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode
uint32_t dac_cntl = RADEON_READ(RADEON_DAC_CNTL);
uint32_t dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
+ DRM_DEBUG("\n");
+
switch(mode) {
case DRM_MODE_DPMS_ON:
crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
@@ -402,6 +412,8 @@ static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
+ DRM_DEBUG("\n");
+
if (radeon_crtc->crtc_id == 0)
radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
@@ -470,6 +482,9 @@ struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev
struct radeon_mode_info *mode_info = &dev_priv->mode_info;
struct radeon_encoder *radeon_encoder;
struct drm_encoder *encoder;
+
+ DRM_DEBUG("\n");
+
radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
if (!radeon_encoder) {
return NULL;
@@ -504,6 +519,8 @@ static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
struct drm_radeon_private *dev_priv = dev->dev_private;
uint32_t fp_gen_cntl = RADEON_READ(RADEON_FP_GEN_CNTL);
+ DRM_DEBUG("\n");
+
switch(mode) {
case DRM_MODE_DPMS_ON:
fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
@@ -539,6 +556,8 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
int i;
+ DRM_DEBUG("\n");
+
if (radeon_crtc->crtc_id == 0)
radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
@@ -631,6 +650,9 @@ struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, i
struct radeon_mode_info *mode_info = &dev_priv->mode_info;
struct radeon_encoder *radeon_encoder;
struct drm_encoder *encoder;
+
+ DRM_DEBUG("\n");
+
radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
if (!radeon_encoder) {
return NULL;
@@ -662,6 +684,8 @@ static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
struct drm_radeon_private *dev_priv = dev->dev_private;
uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
+ DRM_DEBUG("\n");
+
switch(mode) {
case DRM_MODE_DPMS_ON:
fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
@@ -698,6 +722,8 @@ static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
+ DRM_DEBUG("\n");
+
if (radeon_crtc->crtc_id == 0)
radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
@@ -762,6 +788,9 @@ struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, i
struct radeon_mode_info *mode_info = &dev_priv->mode_info;
struct radeon_encoder *radeon_encoder;
struct drm_encoder *encoder;
+
+ DRM_DEBUG("\n");
+
radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
if (!radeon_encoder) {
return NULL;
@@ -793,6 +822,8 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
struct drm_radeon_private *dev_priv = dev->dev_private;
uint32_t fp2_gen_cntl, crtc2_gen_cntl, tv_master_cntl, tv_dac_cntl;
+ DRM_DEBUG("\n");
+
if (dev_priv->chip_family == CHIP_R200)
fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
else {
@@ -876,6 +907,8 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
uint32_t tv_dac_cntl, gpiopad_a, dac2_cntl, disp_output_cntl, fp2_gen_cntl;
uint32_t disp_hw_debug;
+ DRM_DEBUG("\n");
+
if (radeon_crtc->crtc_id == 0)
radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
@@ -981,6 +1014,9 @@ struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int
struct radeon_mode_info *mode_info = &dev_priv->mode_info;
struct radeon_encoder *radeon_encoder;
struct drm_encoder *encoder;
+
+ DRM_DEBUG("\n");
+
radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
if (!radeon_encoder) {
return NULL;
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index fb266093..2b8d7f6e 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -1283,7 +1283,7 @@ extern void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint
#define RADEON_WRITE_P(reg, val, mask) \
do { \
uint32_t tmp = RADEON_READ(reg); \
- tmp &= ~(mask); \
+ tmp &= (mask); \
tmp |= ((val) & ~(mask)); \
RADEON_WRITE(reg, tmp); \
} while(0)
--
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