From ade2ad2d66ac341a12eca37bcb30d40199eb4e02 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 7 Mar 2013 09:49:53 -0500 Subject: radeonsi: make sure tile_split field are not garbage Signed-off-by: Jerome Glisse --- radeon/radeon_surface.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index d52f4574..5935c231 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -1063,7 +1063,7 @@ static int si_surface_init_linear_aligned(struct radeon_surface_manager *surf_ma for (i = start_level; i <= surf->last_level; i++) { surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED; si_surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, - zalign, slice_align, offset); + zalign, slice_align, offset); /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if ((i == 0)) { @@ -1150,6 +1150,12 @@ static int si_surface_init(struct radeon_surface_manager *surf_man, /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; + /* those are already handled by the kernel tile mode array but we still + * need value that won't be rejected by kernel set tiling function + */ + surf->tile_split = 0; + surf->stencil_tile_split = 0; + if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { /* zbuffer only support 1D or 2D tiled surface */ switch (mode) { -- cgit v1.2.3