From a46104674f129e873b8dfa29cf8aac9c67bd77be Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 10 Aug 2007 13:54:26 +1000 Subject: nouveau/nv50: demagic instmem setup. --- shared-core/nouveau_drv.h | 3 +- shared-core/nouveau_fifo.c | 2 - shared-core/nouveau_object.c | 50 ++++++--- shared-core/nouveau_reg.h | 10 ++ shared-core/nv04_fifo.c | 2 +- shared-core/nv10_fifo.c | 2 +- shared-core/nv40_fifo.c | 2 +- shared-core/nv50_fifo.c | 37 +++---- shared-core/nv50_instmem.c | 246 ++++++++++++++++++++++++++----------------- 9 files changed, 217 insertions(+), 137 deletions(-) diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 4d5c7f7e..e3d0ff4c 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -393,7 +393,8 @@ extern int nouveau_gpuobj_new_ref(struct drm_device *, struct nouveau_channel *ref_chan, uint32_t handle, int size, int align, uint32_t flags, struct nouveau_gpuobj_ref **); -extern int nouveau_gpuobj_new_fake(struct drm_device *, uint32_t offset, +extern int nouveau_gpuobj_new_fake(struct drm_device *, + uint32_t p_offset, uint32_t b_offset, uint32_t size, uint32_t flags, struct nouveau_gpuobj **, struct nouveau_gpuobj_ref**); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 22bced14..f0c2a556 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -285,8 +285,6 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, * When there are no more contexts, you lost */ for(channel=0; channelcard_type == NV_50) && (channel == 0)) - continue; if (dev_priv->fifos[channel] == NULL) break; } diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index d4142e44..e0cb334f 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -72,6 +72,8 @@ nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle) uint32_t hash = 0; int i; + DRM_DEBUG("ch%d handle=0x%08x\n", channel, handle); + for (i=32;i>0;i-=dev_priv->ramht_bits) { hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1)); handle >>= dev_priv->ramht_bits; @@ -80,7 +82,7 @@ nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle) hash ^= channel << (dev_priv->ramht_bits - 4); hash <<= 3; - DRM_DEBUG("ch%d handle=0x%08x hash=0x%08x\n", channel, handle, hash); + DRM_DEBUG("hash=0x%08x\n", hash); return hash; } @@ -286,7 +288,7 @@ nouveau_gpuobj_init(struct drm_device *dev) if (dev_priv->card_type < NV_50) { if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset, - dev_priv->ramht_size, + ~0, dev_priv->ramht_size, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ALLOW_NO_REFS, &dev_priv->ramht, NULL))) @@ -346,7 +348,13 @@ nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) if (gpuobj->dtor) gpuobj->dtor(dev, gpuobj); - engine->instmem.clear(dev, gpuobj); + if (gpuobj->im_backing) { + if (gpuobj->flags & NVOBJ_FLAG_FAKE) + drm_free(gpuobj->im_backing, + sizeof(*gpuobj->im_backing), DRM_MEM_DRIVER); + else + engine->instmem.clear(dev, gpuobj); + } if (gpuobj->im_pramin) { if (gpuobj->flags & NVOBJ_FLAG_FAKE) @@ -525,7 +533,8 @@ nouveau_gpuobj_ref_find(struct nouveau_channel *chan, uint32_t handle, } int -nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size, +nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t p_offset, + uint32_t b_offset, uint32_t size, uint32_t flags, struct nouveau_gpuobj **pgpuobj, struct nouveau_gpuobj_ref **pref) { @@ -533,8 +542,8 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size, struct nouveau_gpuobj *gpuobj = NULL; int i; - DRM_DEBUG("offset=0x%08x size=0x%08x flags=0x%08x\n", - offset, size, flags); + DRM_DEBUG("p_offset=0x%08x b_offset=0x%08x size=0x%08x flags=0x%08x\n", + p_offset, b_offset, size, flags); gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER); if (!gpuobj) @@ -545,14 +554,27 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t offset, uint32_t size, list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); - gpuobj->im_pramin = drm_calloc(1, sizeof(struct mem_block), - DRM_MEM_DRIVER); - if (!gpuobj->im_pramin) { - nouveau_gpuobj_del(dev, &gpuobj); - return -ENOMEM; + if (p_offset != ~0) { + gpuobj->im_pramin = drm_calloc(1, sizeof(struct mem_block), + DRM_MEM_DRIVER); + if (!gpuobj->im_pramin) { + nouveau_gpuobj_del(dev, &gpuobj); + return -ENOMEM; + } + gpuobj->im_pramin->start = p_offset; + gpuobj->im_pramin->size = size; + } + + if (b_offset != ~0) { + gpuobj->im_backing = drm_calloc(1, sizeof(struct mem_block), + DRM_MEM_DRIVER); + if (!gpuobj->im_backing) { + nouveau_gpuobj_del(dev, &gpuobj); + return -ENOMEM; + } + gpuobj->im_backing->start = b_offset; + gpuobj->im_backing->size = size; } - gpuobj->im_pramin->start = offset; - gpuobj->im_pramin->size = size; if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { for (i = 0; i < gpuobj->im_pramin->size; i += 4) @@ -962,7 +984,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200; vm_offset += chan->ramin->gpuobj->im_pramin->start; - if ((ret = nouveau_gpuobj_new_fake(dev, vm_offset, 0x4000, + if ((ret = nouveau_gpuobj_new_fake(dev, vm_offset, ~0, 0x4000, 0, &chan->vm_pd, NULL))) return ret; for (i=0; i<0x4000; i+=8) { diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 47d54b2a..65614627 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -80,6 +80,16 @@ #define NV40_PMC_1708 0x00001708 #define NV40_PMC_170C 0x0000170C +/* probably PMC ? */ +#define NV50_PUNK_BAR0_PRAMIN 0x00001700 +#define NV50_PUNK_BAR_CFG_BASE 0x00001704 +#define NV50_PUNK_BAR_CFG_BASE_VALID (1<<30) +#define NV50_PUNK_BAR1_CTXDMA 0x00001708 +#define NV50_PUNK_BAR1_CTXDMA_VALID (1<<31) +#define NV50_PUNK_BAR3_CTXDMA 0x0000170C +#define NV50_PUNK_BAR3_CTXDMA_VALID (1<<31) +#define NV50_PUNK_UNK1710 0x00001710 + #define NV04_PTIMER_INTR_0 0x00009100 #define NV04_PTIMER_INTR_EN_0 0x00009140 #define NV04_PTIMER_NUMERATOR 0x00009200 diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c index 4d61f4fe..d750ced8 100644 --- a/shared-core/nv04_fifo.c +++ b/shared-core/nv04_fifo.c @@ -42,7 +42,7 @@ nv04_fifo_create_context(struct nouveau_channel *chan) struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; - if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), + if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0, NV04_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c index a056460d..c86725d2 100644 --- a/shared-core/nv10_fifo.c +++ b/shared-core/nv10_fifo.c @@ -43,7 +43,7 @@ nv10_fifo_create_context(struct nouveau_channel *chan) struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; - if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), + if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0, NV10_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c index f04c2882..eb160ee2 100644 --- a/shared-core/nv40_fifo.c +++ b/shared-core/nv40_fifo.c @@ -43,7 +43,7 @@ nv40_fifo_create_context(struct nouveau_channel *chan) struct drm_nouveau_private *dev_priv = dev->dev_private; int ret; - if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), + if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0, NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index f915d332..71b89d6d 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -30,7 +30,6 @@ typedef struct { struct nouveau_gpuobj_ref *thingo; - struct nouveau_gpuobj_ref *dummyctx; } nv50_fifo_priv; #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) @@ -47,7 +46,7 @@ nv50_fifo_init_thingo(struct drm_device *dev) INSTANCE_WR(thingo->gpuobj, 0, 0x7e); INSTANCE_WR(thingo->gpuobj, 1, 0x7e); - for (i = 0; i fifos[i]) { INSTANCE_WR(thingo->gpuobj, fi, i); fi++; @@ -60,7 +59,7 @@ nv50_fifo_init_thingo(struct drm_device *dev) } static int -nv50_fifo_channel_enable(struct drm_device *dev, int channel) +nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_channel *chan = dev_priv->fifos[channel]; @@ -83,7 +82,7 @@ nv50_fifo_channel_enable(struct drm_device *dev, int channel) NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED); } - nv50_fifo_init_thingo(dev); + if (!nt) nv50_fifo_init_thingo(dev); return 0; } @@ -156,18 +155,9 @@ static int nv50_fifo_init_regs(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv; - int ret; DRM_DEBUG("\n"); - if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 0x1000, - 0x1000, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ZERO_FREE, - &priv->dummyctx))) - return ret; - NV_WRITE(0x2500, 0); NV_WRITE(0x3250, 0); NV_WRITE(0x3220, 0); @@ -175,13 +165,9 @@ nv50_fifo_init_regs(struct drm_device *dev) NV_WRITE(0x3210, 0); NV_WRITE(0x3270, 0); - if (IS_G80) { - NV_WRITE(0x2600, (priv->dummyctx->instance>>8) | (1<<31)); - NV_WRITE(0x27fc, (priv->dummyctx->instance>>8) | (1<<31)); - } else { - NV_WRITE(0x2600, (priv->dummyctx->instance>>12) | (1<<31)); - NV_WRITE(0x27fc, (priv->dummyctx->instance>>12) | (1<<31)); - } + /* Enable dummy channels setup by nv50_instmem.c */ + nv50_fifo_channel_enable(dev, 0, 1); + nv50_fifo_channel_enable(dev, 127, 1); return 0; } @@ -209,6 +195,7 @@ nv50_fifo_init(struct drm_device *dev) DRM_ERROR("error creating thingo: %d\n", ret); return ret; } + nv50_fifo_init_context_table(dev); nv50_fifo_init_regs__nv(dev); @@ -230,7 +217,6 @@ nv50_fifo_takedown(struct drm_device *dev) return; nouveau_gpuobj_ref_del(dev, &priv->thingo); - nouveau_gpuobj_ref_del(dev, &priv->dummyctx); dev_priv->Engine.fifo.priv = NULL; drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); @@ -248,7 +234,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan) if (IS_G80) { uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start; - if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, 0x100, + if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, ~0, 0x100, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, &ramfc, &chan->ramfc))) @@ -285,7 +271,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan) INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12); } - if ((ret = nv50_fifo_channel_enable(dev, chan->id))) { + if ((ret = nv50_fifo_channel_enable(dev, chan->id, 0))) { DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret); nouveau_gpuobj_ref_del(dev, &chan->ramfc); return ret; @@ -302,6 +288,11 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan) DRM_DEBUG("ch%d\n", chan->id); nv50_fifo_channel_disable(dev, chan->id, 0); + + /* Dummy channel, also used on ch 127 */ + if (chan->id == 0) + nv50_fifo_channel_disable(dev, 127, 0); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); } diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c index c26b1db5..1eeb54df 100644 --- a/shared-core/nv50_instmem.c +++ b/shared-core/nv50_instmem.c @@ -31,118 +31,162 @@ typedef struct { uint32_t save1700[5]; /* 0x1700->0x1710 */ + + struct nouveau_gpuobj_ref *pramin_pt; + struct nouveau_gpuobj_ref *pramin_bar; } nv50_instmem_priv; #define NV50_INSTMEM_PAGE_SHIFT 12 #define NV50_INSTMEM_PAGE_SIZE (1 << NV50_INSTMEM_PAGE_SHIFT) -#define NV50_INSTMEM_RSVD_SIZE (64 * 1024) #define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3) +/*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN + */ +#define BAR0_WI32(g,o,v) do { \ + uint32_t offset; \ + if ((g)->im_backing) { \ + offset = (g)->im_backing->start; \ + } else { \ + offset = chan->ramin->gpuobj->im_backing->start; \ + offset += (g)->im_pramin->start; \ + } \ + offset += (o); \ + NV_WRITE(NV_RAMIN + (offset & 0xfffff), (v)); \ +} while(0) + int nv50_instmem_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_channel *chan; + uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size; nv50_instmem_priv *priv; - uint32_t rv, pt, pts, cb, cb0, cb1, unk, as; - uint32_t i, v; - int ret; + int ret, i; + uint32_t v; priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER); if (!priv) return -ENOMEM; dev_priv->Engine.instmem.priv = priv; - /* Save current state */ - for (i = 0x1700; i <= 0x1710; i+=4) - priv->save1700[(i-0x1700)/4] = NV_READ(i); - - as = dev_priv->ramin->size; - rv = nouveau_mem_fb_amount(dev) - (1*1024*1024); - pt = rv + 0xd0000; - pts = NV50_INSTMEM_PT_SIZE(as); - cb = rv + 0xc8000; - if ((dev_priv->chipset & 0xf0) != 0x50) { - unk = cb + 0x4200; - cb0 = cb + 0x4240; - cb1 = cb + 0x278; - } else { - unk = cb + 0x5400; - cb0 = cb + 0x5440; - cb1 = cb + 0x1478; - } - - DRM_DEBUG("PRAMIN config:\n"); - DRM_DEBUG(" Rsvd VRAM base: 0x%08x\n", rv); - DRM_DEBUG(" Aperture size: %i MiB\n", as >> 20); - DRM_DEBUG(" PT base: 0x%08x\n", pt); - DRM_DEBUG(" PT size: %d KiB\n", pts >> 10); - DRM_DEBUG(" BIOS image: 0x%08x\n", (NV_READ(0x619f04)&~0xff)<<8); - DRM_DEBUG(" Config base: 0x%08x\n", cb); - DRM_DEBUG(" ctxdma Config0: 0x%08x\n", cb0); - DRM_DEBUG(" Config1: 0x%08x\n", cb1); - - /* Map first MiB of reserved vram into BAR0 PRAMIN aperture */ - NV_WRITE(0x1700, (rv>>16)); - /* Poke some regs.. */ - NV_WRITE(0x1704, (cb>>12)); - NV_WRITE(0x1710, (((unk-cb)>>4))|(1<<31)); - NV_WRITE(0x1704, (cb>>12)|(1<<30)); - - /* CB0, some DMA object, NFI what it points at... Needed however, - * or the PRAMIN aperture doesn't operate as expected. + /* Reserve the last MiB of VRAM, we should probably try to avoid + * setting up the below tables over the top of the VBIOS image at + * some point. */ - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x00, 0x7fc00000); - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x04, 0xe1ffffff); - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x08, 0xe0000000); - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x0c, 0x01000001); - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x10, 0x00000000); - NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x14, 0x00000000); - - /* CB1, points at PRAMIN PT */ - NV_WRITE(NV_RAMIN + (cb1 - rv) + 0, pt | 0x63); - NV_WRITE(NV_RAMIN + (cb1 - rv) + 4, 0x00000000); - - /* Zero PRAMIN page table */ - v = NV_RAMIN + (pt - rv); - for (i = v; i < v + pts; i += 8) { - NV_WRITE(i + 0x00, 0x00000009); - NV_WRITE(i + 0x04, 0x00000000); - } + dev_priv->ramin_rsvd_vram = 1 << 20; + c_offset = nouveau_mem_fb_amount(dev) - dev_priv->ramin_rsvd_vram; + c_size = 128 << 10; + c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200; + c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20; + c_base = c_vmpd + 0x4000; + pt_size = NV50_INSTMEM_PT_SIZE(dev_priv->ramin->size); + + DRM_DEBUG(" Rsvd VRAM base: 0x%08x\n", c_offset); + DRM_DEBUG(" VBIOS image: 0x%08x\n", (NV_READ(0x619f04)&~0xff)<<8); + DRM_DEBUG(" Aperture size: %d MiB\n", + (uint32_t)dev_priv->ramin->size >> 20); + DRM_DEBUG(" PT size: %d KiB\n", pt_size >> 10); + + NV_WRITE(NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16)); + + /* Create a fake channel, and use it as our "dummy" channels 0/127. + * The main reason for creating a channel is so we can use the gpuobj + * code. However, it's probably worth noting that NVIDIA also setup + * their channels 0/127 with the same values they configure here. + * So, there may be some other reason for doing this. + * + * Have to create the entire channel manually, as the real channel + * creation code assumes we have PRAMIN access, and we don't until + * we're done here. + */ + chan = drm_calloc(1, sizeof(*chan), DRM_MEM_DRIVER); + if (!chan) + return -ENOMEM; + chan->id = 0; + chan->dev = dev; + chan->file_priv = (struct drm_file *)-2; + dev_priv->fifos[0] = dev_priv->fifos[127] = chan; - /* Map page table into PRAMIN aperture */ - for (i = pt; i < pt + pts; i += 0x1000) { - uint32_t pte = NV_RAMIN + (pt-rv) + (((i-pt) >> 12) << 3); - DRM_DEBUG("PRAMIN PTE = 0x%08x @ 0x%08x\n", i, pte); - NV_WRITE(pte + 0x00, i | 1); - NV_WRITE(pte + 0x04, 0x00000000); - } + /* Channel's PRAMIN object + heap */ + if ((ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, 128<<10, 0, + NULL, &chan->ramin))) + return ret; - /* Points at CB0 */ - NV_WRITE(0x170c, (((cb0 - cb)>>4)|(1<<31))); + if (nouveau_mem_init_heap(&chan->ramin_heap, c_base, c_size - c_base)) + return -ENOMEM; + + /* RAMFC + zero channel's PRAMIN up to start of VM pagedir */ + if ((ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc, + 0x4000, 0, NULL, &chan->ramfc))) + return ret; + + for (i = 0; i < c_vmpd; i += 4) + BAR0_WI32(chan->ramin->gpuobj, i, 0); + + /* VM page directory */ + if ((ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd, + 0x4000, 0, &chan->vm_pd, NULL))) + return ret; + for (i = 0; i < 0x4000; i += 8) { + BAR0_WI32(chan->vm_pd, i + 0x00, 0x00000000); + BAR0_WI32(chan->vm_pd, i + 0x04, 0x00000000); + } - /* Confirm it all worked, should be able to read back the page table's - * PTEs from the PRAMIN BAR + /* PRAMIN page table, cheat and map into VM at 0x0000000000. + * We map the entire fake channel into the start of the PRAMIN BAR */ - NV_WRITE(0x1700, pt >> 16); - if (NV_READ(0x700000) != NV_RI32(0)) { - DRM_ERROR("Failed to init PRAMIN page table\n"); - return -EINVAL; + if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000, + 0, &priv->pramin_pt))) + return ret; + + for (i = 0, v = c_offset; i < pt_size; i+=8, v+=0x1000) { + if (v < (c_offset + c_size)) + BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1); + else + BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009); + BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000); } - /* Create a heap to manage PRAMIN aperture allocations */ - ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, pts, as-pts); - if (ret) { - DRM_ERROR("Failed to init PRAMIN heap\n"); - return -ENOMEM; + BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63); + BAR0_WI32(chan->vm_pd, 0x04, 0x00000000); + + /* DMA object for PRAMIN BAR */ + if ((ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0, + &priv->pramin_bar))) + return ret; + BAR0_WI32(priv->pramin_bar->gpuobj, 0x00, 0x7fc00000); + BAR0_WI32(priv->pramin_bar->gpuobj, 0x04, dev_priv->ramin->size - 1); + BAR0_WI32(priv->pramin_bar->gpuobj, 0x08, 0x00000000); + BAR0_WI32(priv->pramin_bar->gpuobj, 0x0c, 0x00000000); + BAR0_WI32(priv->pramin_bar->gpuobj, 0x10, 0x00000000); + BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000); + + /* Poke the relevant regs, and pray it works :) */ + NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12)); + NV_WRITE(NV50_PUNK_UNK1710, 0); + NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) | + NV50_PUNK_BAR_CFG_BASE_VALID); + NV_WRITE(NV50_PUNK_BAR1_CTXDMA, 0); + NV_WRITE(NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) | + NV50_PUNK_BAR3_CTXDMA_VALID); + + /* Assume that praying isn't enough, check that we can re-read the + * entire fake channel back from the PRAMIN BAR */ + for (i = 0; i < c_size; i+=4) { + if (NV_READ(NV_RAMIN + i) != NV_RI32(i)) { + DRM_ERROR("Error reading back PRAMIN at 0x%08x\n", i); + return -EINVAL; + } } - DRM_DEBUG("NV50: PRAMIN setup ok\n"); - /* Don't alloc the last MiB of VRAM, probably too much, but be safe - * at least for now. - */ - dev_priv->ramin_rsvd_vram = 1*1024*1024; + /* Global PRAMIN heap */ + if (nouveau_mem_init_heap(&dev_priv->ramin_heap, + c_size, dev_priv->ramin->size - c_size)) { + dev_priv->ramin_heap = NULL; + DRM_ERROR("Failed to init RAMIN heap\n"); + } - /*XXX: probably incorrect, but needed to make hash func "work" */ + /*XXX: incorrect, but needed to make hash func "work" */ dev_priv->ramht_offset = 0x10000; dev_priv->ramht_bits = 9; dev_priv->ramht_size = (1 << dev_priv->ramht_bits); @@ -154,8 +198,11 @@ nv50_instmem_takedown(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv; + struct nouveau_channel *chan = dev_priv->fifos[0]; int i; + DRM_DEBUG("\n"); + if (!priv) return; @@ -163,6 +210,20 @@ nv50_instmem_takedown(struct drm_device *dev) for (i = 0x1700; i <= 0x1710; i+=4) NV_WRITE(i, priv->save1700[(i-0x1700)/4]); + nouveau_gpuobj_ref_del(dev, &priv->pramin_bar); + nouveau_gpuobj_ref_del(dev, &priv->pramin_pt); + + /* Destroy dummy channel */ + if (chan) { + nouveau_gpuobj_del(dev, &chan->vm_pd); + nouveau_gpuobj_ref_del(dev, &chan->ramfc); + nouveau_gpuobj_ref_del(dev, &chan->ramin); + nouveau_mem_takedown(&chan->ramin_heap); + + dev_priv->fifos[0] = dev_priv->fifos[127] = NULL; + drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER); + } + dev_priv->Engine.instmem.priv = NULL; drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER); } @@ -205,6 +266,7 @@ int nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { struct drm_nouveau_private *dev_priv = dev->dev_private; + nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv; uint32_t pte, pte_end, vram; if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound) @@ -217,19 +279,14 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; vram = gpuobj->im_backing->start; - if (pte == pte_end) { - DRM_ERROR("WARNING: badness in bind() pte calc\n"); - pte_end++; - } - DRM_DEBUG("pramin=0x%llx, pte=%d, pte_end=%d\n", gpuobj->im_pramin->start, pte, pte_end); DRM_DEBUG("first vram page: 0x%llx\n", gpuobj->im_backing->start); while (pte < pte_end) { - NV_WI32(pte + 0, vram | 1); - NV_WI32(pte + 4, 0x00000000); + INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 0)/4, vram | 1); + INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000); pte += 8; vram += NV50_INSTMEM_PAGE_SIZE; @@ -243,6 +300,7 @@ int nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) { struct drm_nouveau_private *dev_priv = dev->dev_private; + nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv; uint32_t pte, pte_end; if (gpuobj->im_bound == 0) @@ -251,8 +309,8 @@ nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) pte = (gpuobj->im_pramin->start >> 12) << 3; pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte; while (pte < pte_end) { - NV_WI32(pte + 0, 0x00000000); - NV_WI32(pte + 4, 0x00000000); + INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 0)/4, 0x00000009); + INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000); pte += 8; } -- cgit v1.2.3