From 9f9a8f1382711a05ec000b639d971b619d8bc305 Mon Sep 17 00:00:00 2001 From: Jon Smirl Date: Thu, 30 Sep 2004 21:12:10 +0000 Subject: Lindent of core build. Drivers checked for no binary diffs. A few files weren't Lindent's because their comments didn't convert very well. A bunch of other minor clean up with no code implact included. --- linux-core/ati_pcigart.c | 103 +- linux-core/drmP.h | 931 ++- linux-core/drm_agpsupport.c | 155 +- linux-core/drm_auth.c | 69 +- linux-core/drm_bufs.c | 1014 +-- linux-core/drm_compat.h | 45 +- linux-core/drm_context.c | 299 +- linux-core/drm_core.h | 1 - linux-core/drm_dma.c | 90 +- linux-core/drm_drawable.c | 8 +- linux-core/drm_drv.c | 436 +- linux-core/drm_fops.c | 276 +- linux-core/drm_init.c | 37 +- linux-core/drm_ioctl.c | 151 +- linux-core/drm_irq.c | 167 +- linux-core/drm_lock.c | 180 +- linux-core/drm_memory.c | 48 +- linux-core/drm_memory.h | 70 +- linux-core/drm_memory_debug.c | 175 +- linux-core/drm_memory_debug.h | 225 +- linux-core/drm_os_linux.h | 20 +- linux-core/drm_pci.c | 43 +- linux-core/drm_proc.c | 274 +- linux-core/drm_scatter.c | 182 +- linux-core/drm_stub.c | 126 +- linux-core/drm_sysfs.c | 20 +- linux-core/drm_vm.c | 386 +- linux-core/ffb_context.c | 285 +- linux-core/ffb_drv.c | 14 +- linux-core/ffb_drv.h | 8 +- linux-core/i810_dma.c | 1073 ++- linux-core/i810_drm.h | 79 +- linux-core/i810_drv.c | 89 +- linux-core/i810_drv.h | 71 +- linux-core/i830_dma.c | 1315 ++-- linux-core/i830_drm.h | 118 +- linux-core/i830_drv.c | 88 +- linux-core/i830_drv.h | 109 +- linux-core/i830_irq.c | 145 +- linux-core/i915_drv.c | 83 +- linux-core/mach64_drv.c | 74 +- linux-core/mga_drv.c | 77 +- linux-core/r128_drv.c | 92 +- linux-core/radeon_drv.c | 111 +- linux-core/radeon_i2c.c | 38 +- linux-core/radeon_i2c.h | 14 +- linux-core/savage_dma.c | 45 +- linux-core/savage_drm.h | 119 +- linux-core/savage_drv.c | 60 +- linux-core/savage_drv.h | 36 +- linux-core/sis_drv.c | 68 +- linux-core/tdfx_drv.c | 52 +- shared-core/drm.h | 298 +- shared-core/drm_sarea.h | 30 +- shared-core/i915_dma.c | 18 +- shared-core/i915_drv.h | 14 +- shared-core/i915_irq.c | 4 +- shared-core/i915_mem.c | 12 +- shared-core/mach64_dma.c | 1243 ++-- shared-core/mach64_drm.h | 25 +- shared-core/mach64_drv.h | 420 +- shared-core/mach64_irq.c | 92 +- shared-core/mach64_state.c | 746 +- shared-core/mga_dma.c | 525 +- shared-core/mga_drm.h | 117 +- shared-core/mga_drv.h | 86 +- shared-core/mga_irq.c | 53 +- shared-core/mga_state.c | 908 ++- shared-core/mga_ucode.h | 16070 ++++++++++++++++++++-------------------- shared-core/mga_warp.c | 185 +- shared-core/r128_cce.c | 588 +- shared-core/r128_drm.h | 32 +- shared-core/r128_drv.h | 97 +- shared-core/r128_irq.c | 53 +- shared-core/r128_state.c | 1352 ++-- shared-core/radeon_cp.c | 1905 +++-- shared-core/radeon_drm.h | 269 +- shared-core/radeon_drv.h | 182 +- shared-core/radeon_irq.c | 145 +- shared-core/radeon_mem.c | 152 +- shared-core/radeon_state.c | 2077 +++--- shared-core/sis_drm.h | 2 +- shared-core/sis_drv.h | 22 +- shared-core/sis_ds.c | 113 +- shared-core/sis_ds.h | 50 +- shared-core/sis_mm.c | 120 +- shared-core/tdfx_drv.h | 4 - shared-core/via_3d_reg.h | 62 +- shared-core/via_dma.c | 288 +- shared-core/via_drm.h | 168 +- shared-core/via_drv.c | 76 +- shared-core/via_drv.h | 54 +- shared-core/via_ds.c | 586 +- shared-core/via_ds.h | 61 +- shared-core/via_irq.c | 190 +- shared-core/via_map.c | 86 +- shared-core/via_mm.c | 481 +- shared-core/via_mm.h | 22 +- 98 files changed, 19846 insertions(+), 20031 deletions(-) diff --git a/linux-core/ati_pcigart.c b/linux-core/ati_pcigart.c index e338fe15..19d03592 100644 --- a/linux-core/ati_pcigart.c +++ b/linux-core/ati_pcigart.c @@ -52,48 +52,47 @@ # define ATI_MAX_PCIGART_PAGES 8192 /**< 32 MB aperture, 4K pages */ # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ -static unsigned long drm_ati_alloc_pcigart_table( void ) +static unsigned long drm_ati_alloc_pcigart_table(void) { unsigned long address; struct page *page; int i; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - address = __get_free_pages( GFP_KERNEL, ATI_PCIGART_TABLE_ORDER ); - if ( address == 0UL ) { + address = __get_free_pages(GFP_KERNEL, ATI_PCIGART_TABLE_ORDER); + if (address == 0UL) { return 0; } - page = virt_to_page( address ); + page = virt_to_page(address); - for ( i = 0 ; i < ATI_PCIGART_TABLE_PAGES ; i++, page++ ) { + for (i = 0; i < ATI_PCIGART_TABLE_PAGES; i++, page++) { get_page(page); - SetPageReserved( page ); + SetPageReserved(page); } - DRM_DEBUG( "%s: returning 0x%08lx\n", __FUNCTION__, address ); + DRM_DEBUG("%s: returning 0x%08lx\n", __FUNCTION__, address); return address; } -static void drm_ati_free_pcigart_table( unsigned long address ) +static void drm_ati_free_pcigart_table(unsigned long address) { struct page *page; int i; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - page = virt_to_page( address ); + page = virt_to_page(address); - for ( i = 0 ; i < ATI_PCIGART_TABLE_PAGES ; i++, page++ ) { + for (i = 0; i < ATI_PCIGART_TABLE_PAGES; i++, page++) { __put_page(page); - ClearPageReserved( page ); + ClearPageReserved(page); } - free_pages( address, ATI_PCIGART_TABLE_ORDER ); + free_pages(address, ATI_PCIGART_TABLE_ORDER); } -int drm_ati_pcigart_init( drm_device_t *dev, - unsigned long *addr, - dma_addr_t *bus_addr) +int drm_ati_pcigart_init(drm_device_t * dev, + unsigned long *addr, dma_addr_t * bus_addr) { drm_sg_mem_t *entry = dev->sg; unsigned long address = 0; @@ -101,48 +100,48 @@ int drm_ati_pcigart_init( drm_device_t *dev, u32 *pci_gart, page_base, bus_address = 0; int i, j, ret = 0; - if ( !entry ) { - DRM_ERROR( "no scatter/gather memory!\n" ); + if (!entry) { + DRM_ERROR("no scatter/gather memory!\n"); goto done; } address = drm_ati_alloc_pcigart_table(); - if ( !address ) { - DRM_ERROR( "cannot allocate PCI GART page!\n" ); + if (!address) { + DRM_ERROR("cannot allocate PCI GART page!\n"); goto done; } - if ( !dev->pdev ) { - DRM_ERROR( "PCI device unknown!\n" ); + if (!dev->pdev) { + DRM_ERROR("PCI device unknown!\n"); goto done; } bus_address = pci_map_single(dev->pdev, (void *)address, - ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, - PCI_DMA_TODEVICE); + ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, + PCI_DMA_TODEVICE); if (bus_address == 0) { - DRM_ERROR( "unable to map PCIGART pages!\n" ); - drm_ati_free_pcigart_table( address ); + DRM_ERROR("unable to map PCIGART pages!\n"); + drm_ati_free_pcigart_table(address); address = 0; goto done; } - pci_gart = (u32 *)address; + pci_gart = (u32 *) address; - pages = ( entry->pages <= ATI_MAX_PCIGART_PAGES ) - ? entry->pages : ATI_MAX_PCIGART_PAGES; + pages = (entry->pages <= ATI_MAX_PCIGART_PAGES) + ? entry->pages : ATI_MAX_PCIGART_PAGES; - memset( pci_gart, 0, ATI_MAX_PCIGART_PAGES * sizeof(u32) ); + memset(pci_gart, 0, ATI_MAX_PCIGART_PAGES * sizeof(u32)); - for ( i = 0 ; i < pages ; i++ ) { + for (i = 0; i < pages; i++) { /* we need to support large memory configurations */ entry->busaddr[i] = pci_map_single(dev->pdev, - page_address( entry->pagelist[i] ), - PAGE_SIZE, - PCI_DMA_TODEVICE); + page_address(entry-> + pagelist[i]), + PAGE_SIZE, PCI_DMA_TODEVICE); if (entry->busaddr[i] == 0) { - DRM_ERROR( "unable to map PCIGART pages!\n" ); - drm_ati_pcigart_cleanup( dev, address, bus_address ); + DRM_ERROR("unable to map PCIGART pages!\n"); + drm_ati_pcigart_cleanup(dev, address, bus_address); address = 0; bus_address = 0; goto done; @@ -150,7 +149,7 @@ int drm_ati_pcigart_init( drm_device_t *dev, page_base = (u32) entry->busaddr[i]; for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { - *pci_gart++ = cpu_to_le32( page_base ); + *pci_gart++ = cpu_to_le32(page_base); page_base += ATI_PCIGART_PAGE_SIZE; } } @@ -158,48 +157,48 @@ int drm_ati_pcigart_init( drm_device_t *dev, ret = 1; #if defined(__i386__) || defined(__x86_64__) - asm volatile ( "wbinvd" ::: "memory" ); + asm volatile ("wbinvd":::"memory"); #else mb(); #endif -done: + done: *addr = address; *bus_addr = bus_address; return ret; } -int drm_ati_pcigart_cleanup( drm_device_t *dev, - unsigned long addr, - dma_addr_t bus_addr) +int drm_ati_pcigart_cleanup(drm_device_t * dev, + unsigned long addr, dma_addr_t bus_addr) { drm_sg_mem_t *entry = dev->sg; unsigned long pages; int i; /* we need to support large memory configurations */ - if ( !entry ) { - DRM_ERROR( "no scatter/gather memory!\n" ); + if (!entry) { + DRM_ERROR("no scatter/gather memory!\n"); return 0; } - if ( bus_addr ) { + if (bus_addr) { pci_unmap_single(dev->pdev, bus_addr, ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, PCI_DMA_TODEVICE); - pages = ( entry->pages <= ATI_MAX_PCIGART_PAGES ) - ? entry->pages : ATI_MAX_PCIGART_PAGES; + pages = (entry->pages <= ATI_MAX_PCIGART_PAGES) + ? entry->pages : ATI_MAX_PCIGART_PAGES; - for ( i = 0 ; i < pages ; i++ ) { - if ( !entry->busaddr[i] ) break; + for (i = 0; i < pages; i++) { + if (!entry->busaddr[i]) + break; pci_unmap_single(dev->pdev, entry->busaddr[i], PAGE_SIZE, PCI_DMA_TODEVICE); } } - if ( addr ) { - drm_ati_free_pcigart_table( addr ); + if (addr) { + drm_ati_free_pcigart_table(addr); } return 1; diff --git a/linux-core/drmP.h b/linux-core/drmP.h index 0d121243..feba8f9d 100644 --- a/linux-core/drmP.h +++ b/linux-core/drmP.h @@ -1,7 +1,7 @@ /** - * \file drmP.h + * \file drmP.h * Private header for Direct Rendering Manager - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -34,14 +34,13 @@ #ifndef _DRM_P_H_ #define _DRM_P_H_ - #ifdef __KERNEL__ #ifdef __alpha__ /* add include of current.h so that "current" is defined * before static inline funcs in wait.h. Doing this so we * can build the DRM (part of PI DRI). 4/21/2000 S + B */ #include -#endif /* __alpha__ */ +#endif /* __alpha__ */ #include #include #include @@ -57,7 +56,7 @@ #include #include #if defined(__alpha__) || defined(__powerpc__) -#include /* For pte_wrprotect */ +#include /* For pte_wrprotect */ #endif #include #include @@ -150,13 +149,11 @@ #define DRM_MEM_CTXLIST 21 #define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8) - -/*@}*/ +/*@}*/ #include "drm_compat.h" - /***********************************************************************/ /** \name Macros to make printk easier */ /*@{*/ @@ -184,7 +181,7 @@ /** * Debug output. - * + * * \param fmt printf() like format string. * \param arg arguments */ @@ -193,7 +190,7 @@ do { \ if ( drm_flags & DRM_FLAG_DEBUG ) \ printk(KERN_DEBUG \ - "[" DRM_NAME ":%s] " fmt , \ + "[" DRM_NAME ":%s] " fmt , \ __FUNCTION__ , ##arg); \ } while (0) #else @@ -212,7 +209,6 @@ /*@}*/ - /***********************************************************************/ /** \name Internal types and structures */ /*@{*/ @@ -265,7 +261,7 @@ do { \ if ( copy_to_user( name, value, len ) ) \ return -EFAULT; \ } - + /** * Ioctl function type. * @@ -274,22 +270,22 @@ do { \ * \param cmd command. * \param arg argument. */ -typedef int drm_ioctl_t( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); +typedef int drm_ioctl_t(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); typedef struct drm_ioctl_desc { - drm_ioctl_t *func; - int auth_needed; - int root_only; + drm_ioctl_t *func; + int auth_needed; + int root_only; } drm_ioctl_desc_t; typedef struct drm_devstate { - pid_t owner; /**< X server pid holding x_lock */ + pid_t owner; /**< X server pid holding x_lock */ } drm_devstate_t; typedef struct drm_magic_entry { - drm_magic_t magic; - struct drm_file *priv; + drm_magic_t magic; + struct drm_file *priv; struct drm_magic_entry *next; } drm_magic_entry_t; @@ -300,111 +296,110 @@ typedef struct drm_magic_head { typedef struct drm_vma_entry { struct vm_area_struct *vma; - struct drm_vma_entry *next; - pid_t pid; + struct drm_vma_entry *next; + pid_t pid; } drm_vma_entry_t; /** * DMA buffer. */ typedef struct drm_buf { - int idx; /**< Index into master buflist */ - int total; /**< Buffer size */ - int order; /**< log-base-2(total) */ - int used; /**< Amount of buffer in use (for DMA) */ - unsigned long offset; /**< Byte offset (used internally) */ - void *address; /**< Address of buffer */ - unsigned long bus_address; /**< Bus address of buffer */ - struct drm_buf *next; /**< Kernel-only: used for free list */ - __volatile__ int waiting; /**< On kernel DMA queue */ - __volatile__ int pending; /**< On hardware DMA queue */ + int idx; /**< Index into master buflist */ + int total; /**< Buffer size */ + int order; /**< log-base-2(total) */ + int used; /**< Amount of buffer in use (for DMA) */ + unsigned long offset; /**< Byte offset (used internally) */ + void *address; /**< Address of buffer */ + unsigned long bus_address; /**< Bus address of buffer */ + struct drm_buf *next; /**< Kernel-only: used for free list */ + __volatile__ int waiting; /**< On kernel DMA queue */ + __volatile__ int pending; /**< On hardware DMA queue */ wait_queue_head_t dma_wait; /**< Processes waiting */ - struct file *filp; /**< Pointer to holding file descr */ - int context; /**< Kernel queue for this buffer */ - int while_locked;/**< Dispatch this buffer while locked */ + struct file *filp; /**< Pointer to holding file descr */ + int context; /**< Kernel queue for this buffer */ + int while_locked; /**< Dispatch this buffer while locked */ enum { - DRM_LIST_NONE = 0, - DRM_LIST_FREE = 1, - DRM_LIST_WAIT = 2, - DRM_LIST_PEND = 3, - DRM_LIST_PRIO = 4, + DRM_LIST_NONE = 0, + DRM_LIST_FREE = 1, + DRM_LIST_WAIT = 2, + DRM_LIST_PEND = 3, + DRM_LIST_PRIO = 4, DRM_LIST_RECLAIM = 5 - } list; /**< Which list we're on */ + } list; /**< Which list we're on */ - int dev_priv_size; /**< Size of buffer private storage */ - void *dev_private; /**< Per-buffer private storage */ + int dev_priv_size; /**< Size of buffer private storage */ + void *dev_private; /**< Per-buffer private storage */ } drm_buf_t; - /** bufs is one longer than it has to be */ typedef struct drm_waitlist { - int count; /**< Number of possible buffers */ - drm_buf_t **bufs; /**< List of pointers to buffers */ - drm_buf_t **rp; /**< Read pointer */ - drm_buf_t **wp; /**< Write pointer */ - drm_buf_t **end; /**< End pointer */ - spinlock_t read_lock; - spinlock_t write_lock; + int count; /**< Number of possible buffers */ + drm_buf_t **bufs; /**< List of pointers to buffers */ + drm_buf_t **rp; /**< Read pointer */ + drm_buf_t **wp; /**< Write pointer */ + drm_buf_t **end; /**< End pointer */ + spinlock_t read_lock; + spinlock_t write_lock; } drm_waitlist_t; typedef struct drm_freelist { - int initialized; /**< Freelist in use */ - atomic_t count; /**< Number of free buffers */ - drm_buf_t *next; /**< End pointer */ + int initialized; /**< Freelist in use */ + atomic_t count; /**< Number of free buffers */ + drm_buf_t *next; /**< End pointer */ wait_queue_head_t waiting; /**< Processes waiting on free bufs */ - int low_mark; /**< Low water mark */ - int high_mark; /**< High water mark */ - atomic_t wfh; /**< If waiting for high mark */ - spinlock_t lock; + int low_mark; /**< Low water mark */ + int high_mark; /**< High water mark */ + atomic_t wfh; /**< If waiting for high mark */ + spinlock_t lock; } drm_freelist_t; /** * Buffer entry. There is one of this for each buffer size order. */ typedef struct drm_buf_entry { - int buf_size; /**< size */ - int buf_count; /**< number of buffers */ - drm_buf_t *buflist; /**< buffer list */ - int seg_count; - int page_order; - unsigned long *seglist; - - drm_freelist_t freelist; + int buf_size; /**< size */ + int buf_count; /**< number of buffers */ + drm_buf_t *buflist; /**< buffer list */ + int seg_count; + int page_order; + unsigned long *seglist; + + drm_freelist_t freelist; } drm_buf_entry_t; /** File private data */ typedef struct drm_file { - int authenticated; - int minor; - pid_t pid; - uid_t uid; - drm_magic_t magic; - unsigned long ioctl_count; - struct drm_file *next; - struct drm_file *prev; + int authenticated; + int minor; + pid_t pid; + uid_t uid; + drm_magic_t magic; + unsigned long ioctl_count; + struct drm_file *next; + struct drm_file *prev; struct drm_device *dev; - int remove_auth_on_close; - unsigned long lock_count; - void *driver_priv; + int remove_auth_on_close; + unsigned long lock_count; + void *driver_priv; } drm_file_t; /** Wait queue */ typedef struct drm_queue { - atomic_t use_count; /**< Outstanding uses (+1) */ - atomic_t finalization; /**< Finalization in progress */ - atomic_t block_count; /**< Count of processes waiting */ - atomic_t block_read; /**< Queue blocked for reads */ + atomic_t use_count; /**< Outstanding uses (+1) */ + atomic_t finalization; /**< Finalization in progress */ + atomic_t block_count; /**< Count of processes waiting */ + atomic_t block_read; /**< Queue blocked for reads */ wait_queue_head_t read_queue; /**< Processes waiting on block_read */ - atomic_t block_write; /**< Queue blocked for writes */ + atomic_t block_write; /**< Queue blocked for writes */ wait_queue_head_t write_queue; /**< Processes waiting on block_write */ #if 1 - atomic_t total_queued; /**< Total queued statistic */ - atomic_t total_flushed;/**< Total flushes statistic */ - atomic_t total_locks; /**< Total locks statistics */ + atomic_t total_queued; /**< Total queued statistic */ + atomic_t total_flushed; /**< Total flushes statistic */ + atomic_t total_locks; /**< Total locks statistics */ #endif - drm_ctx_flags_t flags; /**< Context preserving and 2D-only */ - drm_waitlist_t waitlist; /**< Pending buffers */ + drm_ctx_flags_t flags; /**< Context preserving and 2D-only */ + drm_waitlist_t waitlist; /**< Pending buffers */ wait_queue_head_t flush_queue; /**< Processes waiting until flush */ } drm_queue_t; @@ -412,10 +407,10 @@ typedef struct drm_queue { * Lock data. */ typedef struct drm_lock_data { - drm_hw_lock_t *hw_lock; /**< Hardware lock */ - struct file *filp; /**< File descr of lock holder (0=kernel) */ + drm_hw_lock_t *hw_lock; /**< Hardware lock */ + struct file *filp; /**< File descr of lock holder (0=kernel) */ wait_queue_head_t lock_queue; /**< Queue of blocked processes */ - unsigned long lock_time; /**< Time of last lock in jiffies */ + unsigned long lock_time; /**< Time of last lock in jiffies */ } drm_lock_data_t; /** @@ -423,35 +418,35 @@ typedef struct drm_lock_data { */ typedef struct drm_device_dma { - drm_buf_entry_t bufs[DRM_MAX_ORDER+1]; /**< buffers, grouped by their size order */ - int buf_count; /**< total number of buffers */ - drm_buf_t **buflist; /**< Vector of pointers into drm_device_dma::bufs */ - int seg_count; - int page_count; /**< number of pages */ - unsigned long *pagelist; /**< page list */ - unsigned long byte_count; + drm_buf_entry_t bufs[DRM_MAX_ORDER + 1]; /**< buffers, grouped by their size order */ + int buf_count; /**< total number of buffers */ + drm_buf_t **buflist; /**< Vector of pointers into drm_device_dma::bufs */ + int seg_count; + int page_count; /**< number of pages */ + unsigned long *pagelist; /**< page list */ + unsigned long byte_count; enum { _DRM_DMA_USE_AGP = 0x01, - _DRM_DMA_USE_SG = 0x02 + _DRM_DMA_USE_SG = 0x02 } flags; /** \name DMA support */ - /*@{*/ - drm_buf_t *this_buffer; /**< Buffer being sent */ - drm_buf_t *next_buffer; /**< Selected buffer to send */ - drm_queue_t *next_queue; /**< Queue from which buffer selected*/ + /*@{ */ + drm_buf_t *this_buffer; /**< Buffer being sent */ + drm_buf_t *next_buffer; /**< Selected buffer to send */ + drm_queue_t *next_queue; /**< Queue from which buffer selected*/ wait_queue_head_t waiting; /**< Processes waiting on free bufs */ - /*@}*/ + /*@} */ } drm_device_dma_t; -/** +/** * AGP memory entry. Stored as a doubly linked list. */ typedef struct drm_agp_mem { - unsigned long handle; /**< handle */ - DRM_AGP_MEM *memory; - unsigned long bound; /**< address */ - int pages; + unsigned long handle; /**< handle */ + DRM_AGP_MEM *memory; + unsigned long bound; /**< address */ + int pages; struct drm_agp_mem *prev; /**< previous entry */ struct drm_agp_mem *next; /**< next entry */ } drm_agp_mem_t; @@ -462,30 +457,30 @@ typedef struct drm_agp_mem { * \sa drm_agp_init)() and drm_device::agp. */ typedef struct drm_agp_head { - DRM_AGP_KERN agp_info; /**< AGP device information */ - drm_agp_mem_t *memory; /**< memory entries */ - unsigned long mode; /**< AGP mode */ - int enabled; /**< whether the AGP bus as been enabled */ - int acquired; /**< whether the AGP device has been acquired */ - unsigned long base; - int agp_mtrr; - int cant_use_aperture; - unsigned long page_mask; + DRM_AGP_KERN agp_info; /**< AGP device information */ + drm_agp_mem_t *memory; /**< memory entries */ + unsigned long mode; /**< AGP mode */ + int enabled; /**< whether the AGP bus as been enabled */ + int acquired; /**< whether the AGP device has been acquired */ + unsigned long base; + int agp_mtrr; + int cant_use_aperture; + unsigned long page_mask; } drm_agp_head_t; /** * Scatter-gather memory. */ typedef struct drm_sg_mem { - unsigned long handle; - void *virtual; - int pages; - struct page **pagelist; - dma_addr_t *busaddr; + unsigned long handle; + void *virtual; + int pages; + struct page **pagelist; + dma_addr_t *busaddr; } drm_sg_mem_t; typedef struct drm_sigdata { - int context; + int context; drm_hw_lock_t *lock; } drm_sigdata_t; @@ -493,8 +488,8 @@ typedef struct drm_sigdata { * Mappings list */ typedef struct drm_map_list { - struct list_head head; /**< list head */ - drm_map_t *map; /**< mapping */ + struct list_head head; /**< list head */ + drm_map_t *map; /**< mapping */ } drm_map_list_t; typedef drm_map_t drm_local_map_t; @@ -503,56 +498,55 @@ typedef drm_map_t drm_local_map_t; * Context handle list */ typedef struct drm_ctx_list { - struct list_head head; /**< list head */ - drm_context_t handle; /**< context handle */ - drm_file_t *tag; /**< associated fd private data */ + struct list_head head; /**< list head */ + drm_context_t handle; /**< context handle */ + drm_file_t *tag; /**< associated fd private data */ } drm_ctx_list_t; - typedef struct drm_vbl_sig { - struct list_head head; - unsigned int sequence; - struct siginfo info; - struct task_struct *task; + struct list_head head; + unsigned int sequence; + struct siginfo info; + struct task_struct *task; } drm_vbl_sig_t; - -/** +/** * DRM device functions structure */ struct drm_device; struct drm_driver_fn { - int (*preinit)(struct drm_device *, unsigned long flags); - void (*prerelease)(struct drm_device *, struct file *filp); - void (*pretakedown)(struct drm_device *); - int (*postcleanup)(struct drm_device *); - int (*presetup)(struct drm_device *); - int (*postsetup)(struct drm_device *); - int (*dma_ioctl)( DRM_IOCTL_ARGS ); + int (*preinit) (struct drm_device *, unsigned long flags); + void (*prerelease) (struct drm_device *, struct file * filp); + void (*pretakedown) (struct drm_device *); + int (*postcleanup) (struct drm_device *); + int (*presetup) (struct drm_device *); + int (*postsetup) (struct drm_device *); + int (*dma_ioctl) (DRM_IOCTL_ARGS); /* these are opposites at the moment */ - int (*open_helper)(struct drm_device *, drm_file_t *); - void (*free_filp_priv)(struct drm_device *, drm_file_t *); - - void (*release)(struct drm_device *, struct file *filp); - void (*dma_ready)(struct drm_device *); - int (*dma_quiescent)(struct drm_device *); - int (*context_ctor)(struct drm_device *dev, int context); - int (*context_dtor)(struct drm_device *dev, int context); - int (*kernel_context_switch)(struct drm_device *dev, int old, int new); - int (*kernel_context_switch_unlock)(struct drm_device *dev); - int (*vblank_wait)(struct drm_device *dev, unsigned int *sequence); + int (*open_helper) (struct drm_device *, drm_file_t *); + void (*free_filp_priv) (struct drm_device *, drm_file_t *); + + void (*release) (struct drm_device *, struct file * filp); + void (*dma_ready) (struct drm_device *); + int (*dma_quiescent) (struct drm_device *); + int (*context_ctor) (struct drm_device * dev, int context); + int (*context_dtor) (struct drm_device * dev, int context); + int (*kernel_context_switch) (struct drm_device * dev, int old, + int new); + int (*kernel_context_switch_unlock) (struct drm_device * dev); + int (*vblank_wait) (struct drm_device * dev, unsigned int *sequence); /* these have to be filled in */ - int (*postinit)(struct drm_device *, unsigned long flags); - irqreturn_t (*irq_handler)( DRM_IRQ_ARGS ); - void (*irq_preinstall)(struct drm_device *dev); - void (*irq_postinstall)(struct drm_device *dev); - void (*irq_uninstall)(struct drm_device *dev); - void (*reclaim_buffers)(struct file *filp); - unsigned long (*get_map_ofs)(drm_map_t *map); - unsigned long (*get_reg_ofs)(struct drm_device *dev); - void (*set_version)(struct drm_device *dev, drm_set_version_t *sv); - int (*version)(drm_version_t *version); + int (*postinit) (struct drm_device *, unsigned long flags); + irqreturn_t(*irq_handler) (DRM_IRQ_ARGS); + void (*irq_preinstall) (struct drm_device * dev); + void (*irq_postinstall) (struct drm_device * dev); + void (*irq_uninstall) (struct drm_device * dev); + void (*reclaim_buffers) (struct file * filp); + unsigned long (*get_map_ofs) (drm_map_t * map); + unsigned long (*get_reg_ofs) (struct drm_device * dev); + void (*set_version) (struct drm_device * dev, drm_set_version_t * sv); + int (*version) (drm_version_t * version); /* variables */ u32 driver_features; int dev_priv_size; @@ -562,124 +556,123 @@ struct drm_driver_fn { struct file_operations fops; }; - /** * DRM device structure. */ typedef struct drm_device { - const char *name; /**< Simple driver name */ - char *unique; /**< Unique identifier: e.g., busid */ - int unique_len; /**< Length of unique field */ - dev_t device; /**< Device number for mknod */ - char *devname; /**< For /proc/interrupts */ - int minor; /**< Minor device number */ - int if_version; /**< Highest interface version set */ + const char *name; /**< Simple driver name */ + char *unique; /**< Unique identifier: e.g., busid */ + int unique_len; /**< Length of unique field */ + dev_t device; /**< Device number for mknod */ + char *devname; /**< For /proc/interrupts */ + int minor; /**< Minor device number */ + int if_version; /**< Highest interface version set */ - int blocked; /**< Blocked due to VC switch? */ + int blocked; /**< Blocked due to VC switch? */ /** \name Locks */ - /*@{*/ - spinlock_t count_lock; /**< For inuse, drm_device::open_count, drm_device::buf_use */ - struct semaphore struct_sem; /**< For others */ - /*@}*/ + /*@{ */ + spinlock_t count_lock; /**< For inuse, drm_device::open_count, drm_device::buf_use */ + struct semaphore struct_sem; /**< For others */ + /*@} */ /** \name Usage Counters */ - /*@{*/ - int open_count; /**< Outstanding files open */ - atomic_t ioctl_count; /**< Outstanding IOCTLs pending */ - atomic_t vma_count; /**< Outstanding vma areas open */ - int buf_use; /**< Buffers in use -- cannot alloc */ - atomic_t buf_alloc; /**< Buffer allocation in progress */ - /*@}*/ + /*@{ */ + int open_count; /**< Outstanding files open */ + atomic_t ioctl_count; /**< Outstanding IOCTLs pending */ + atomic_t vma_count; /**< Outstanding vma areas open */ + int buf_use; /**< Buffers in use -- cannot alloc */ + atomic_t buf_alloc; /**< Buffer allocation in progress */ + /*@} */ /** \name Performance counters */ - /*@{*/ - unsigned long counters; - drm_stat_type_t types[15]; - atomic_t counts[15]; - /*@}*/ + /*@{ */ + unsigned long counters; + drm_stat_type_t types[15]; + atomic_t counts[15]; + /*@} */ /** \name Authentication */ - /*@{*/ - drm_file_t *file_first; /**< file list head */ - drm_file_t *file_last; /**< file list tail */ - drm_magic_head_t magiclist[DRM_HASH_SIZE]; /**< magic hash table */ - /*@}*/ + /*@{ */ + drm_file_t *file_first; /**< file list head */ + drm_file_t *file_last; /**< file list tail */ + drm_magic_head_t magiclist[DRM_HASH_SIZE]; /**< magic hash table */ + /*@} */ /** \name Memory management */ - /*@{*/ - drm_map_list_t *maplist; /**< Linked list of regions */ - int map_count; /**< Number of mappable regions */ + /*@{ */ + drm_map_list_t *maplist; /**< Linked list of regions */ + int map_count; /**< Number of mappable regions */ /** \name Context handle management */ - /*@{*/ - drm_ctx_list_t *ctxlist; /**< Linked list of context handles */ - int ctx_count; /**< Number of context handles */ - struct semaphore ctxlist_sem; /**< For ctxlist */ + /*@{ */ + drm_ctx_list_t *ctxlist; /**< Linked list of context handles */ + int ctx_count; /**< Number of context handles */ + struct semaphore ctxlist_sem; /**< For ctxlist */ - drm_map_t **context_sareas; /**< per-context SAREA's */ - int max_context; + drm_map_t **context_sareas; /**< per-context SAREA's */ + int max_context; - drm_vma_entry_t *vmalist; /**< List of vmas (for debugging) */ - drm_lock_data_t lock; /**< Information on hardware lock */ - /*@}*/ + drm_vma_entry_t *vmalist; /**< List of vmas (for debugging) */ + drm_lock_data_t lock; /**< Information on hardware lock */ + /*@} */ /** \name DMA queues (contexts) */ - /*@{*/ - int queue_count; /**< Number of active DMA queues */ - int queue_reserved; /**< Number of reserved DMA queues */ - int queue_slots; /**< Actual length of queuelist */ - drm_queue_t **queuelist; /**< Vector of pointers to DMA queues */ - drm_device_dma_t *dma; /**< Optional pointer for DMA support */ - /*@}*/ + /*@{ */ + int queue_count; /**< Number of active DMA queues */ + int queue_reserved; /**< Number of reserved DMA queues */ + int queue_slots; /**< Actual length of queuelist */ + drm_queue_t **queuelist; /**< Vector of pointers to DMA queues */ + drm_device_dma_t *dma; /**< Optional pointer for DMA support */ + /*@} */ /** \name Context support */ - /*@{*/ - int irq; /**< Interrupt used by board */ - int irq_enabled; /**< True if irq handler is enabled */ + /*@{ */ + int irq; /**< Interrupt used by board */ + int irq_enabled; /**< True if irq handler is enabled */ __volatile__ long context_flag; /**< Context swapping flag */ __volatile__ long interrupt_flag; /**< Interruption handler flag */ __volatile__ long dma_flag; /**< DMA dispatch flag */ struct timer_list timer; /**< Timer for delaying ctx switch */ - wait_queue_head_t context_wait; /**< Processes waiting on ctx switch */ - int last_checked; /**< Last context checked for DMA */ - int last_context; /**< Last current context */ - unsigned long last_switch; /**< jiffies at last context switch */ - /*@}*/ - + wait_queue_head_t context_wait; /**< Processes waiting on ctx switch */ + int last_checked; /**< Last context checked for DMA */ + int last_context; /**< Last current context */ + unsigned long last_switch; /**< jiffies at last context switch */ + /*@} */ + #if !HAS_WORKQUEUE - struct tq_struct tq; + struct tq_struct tq; #else - struct work_struct work; + struct work_struct work; #endif /** \name VBLANK IRQ support */ - /*@{*/ - - wait_queue_head_t vbl_queue; /**< VBLANK wait queue */ - atomic_t vbl_received; - spinlock_t vbl_lock; - drm_vbl_sig_t vbl_sigs; /**< signal list to send on VBLANK */ - unsigned int vbl_pending; - - /*@}*/ - cycles_t ctx_start; - cycles_t lck_start; - - char buf[DRM_BSZ]; /**< Output buffer */ - char *buf_rp; /**< Read pointer */ - char *buf_wp; /**< Write pointer */ - char *buf_end; /**< End pointer */ + /*@{ */ + + wait_queue_head_t vbl_queue; /**< VBLANK wait queue */ + atomic_t vbl_received; + spinlock_t vbl_lock; + drm_vbl_sig_t vbl_sigs; /**< signal list to send on VBLANK */ + unsigned int vbl_pending; + + /*@} */ + cycles_t ctx_start; + cycles_t lck_start; + + char buf[DRM_BSZ]; /**< Output buffer */ + char *buf_rp; /**< Read pointer */ + char *buf_wp; /**< Write pointer */ + char *buf_end; /**< End pointer */ struct fasync_struct *buf_async;/**< Processes waiting for SIGIO */ wait_queue_head_t buf_readers; /**< Processes waiting to read */ wait_queue_head_t buf_writers; /**< Processes waiting to ctx switch */ - drm_agp_head_t *agp; /**< AGP data */ + drm_agp_head_t *agp; /**< AGP data */ - struct pci_dev *pdev; /**< PCI device structure */ - int pci_domain; /**< PCI bus domain number */ - int pci_bus; /**< PCI bus number */ - int pci_slot; /**< PCI slot number */ - int pci_func; /**< PCI function number */ + struct pci_dev *pdev; /**< PCI device structure */ + int pci_domain; /**< PCI bus domain number */ + int pci_bus; /**< PCI bus number */ + int pci_slot; /**< PCI slot number */ + int pci_func; /**< PCI function number */ #ifdef __alpha__ #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) struct pci_controler *hose; @@ -687,14 +680,14 @@ typedef struct drm_device { struct pci_controller *hose; #endif #endif - drm_sg_mem_t *sg; /**< Scatter gather memory */ - unsigned long *ctx_bitmap; /**< context bitmap */ - void *dev_private; /**< device private data */ - drm_sigdata_t sigdata; /**< For block_all_signals */ - sigset_t sigmask; - + drm_sg_mem_t *sg; /**< Scatter gather memory */ + unsigned long *ctx_bitmap; /**< context bitmap */ + void *dev_private; /**< device private data */ + drm_sigdata_t sigdata; /**< For block_all_signals */ + sigset_t sigmask; + struct drm_driver_fn *fn_tbl; - drm_local_map_t *agp_buffer_map; + drm_local_map_t *agp_buffer_map; } drm_device_t; typedef struct drm_minor { @@ -704,10 +697,11 @@ typedef struct drm_minor { DRM_MINOR_SECONDARY, } class; drm_device_t *dev; - struct proc_dir_entry *dev_root; /**< proc directory entry */ + struct proc_dir_entry *dev_root; /**< proc directory entry */ } drm_minor_t; -static __inline__ int drm_core_check_feature(struct drm_device *dev, int feature) +static __inline__ int drm_core_check_feature(struct drm_device *dev, + int feature) { return ((dev->fn_tbl->driver_features & feature) ? 1 : 0); } @@ -715,7 +709,7 @@ static __inline__ int drm_core_check_feature(struct drm_device *dev, int feature #if __OS_HAS_AGP static inline int drm_core_has_AGP(struct drm_device *dev) { - return drm_core_check_feature(dev, DRIVER_USE_AGP); + return drm_core_check_feature(dev, DRIVER_USE_AGP); } #else #define drm_core_has_AGP(dev) (0) @@ -724,7 +718,7 @@ static inline int drm_core_has_AGP(struct drm_device *dev) #if __OS_HAS_MTRR static inline int drm_core_has_MTRR(struct drm_device *dev) { - return drm_core_check_feature(dev, DRIVER_USE_MTRR); + return drm_core_check_feature(dev, DRIVER_USE_MTRR); } #else #define drm_core_has_MTRR(dev) (0) @@ -735,270 +729,271 @@ static inline int drm_core_has_MTRR(struct drm_device *dev) /*@{*/ /* Misc. support (drm_init.h) */ -extern int drm_flags; -extern void drm_parse_options( char *s ); -extern int drm_cpu_valid( void ); +extern int drm_flags; +extern void drm_parse_options(char *s); +extern int drm_cpu_valid(void); /* Driver support (drm_drv.h) */ -extern int drm_fb_loaded; -extern int __devinit drm_init(struct pci_driver *driver, struct pci_device_id* pciidlist, - struct drm_driver_fn *driver_fn); -extern void __exit drm_exit (struct pci_driver *driver); -extern void __exit drm_cleanup_pci(struct pci_dev *pdev); -extern int drm_version(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_takedown( drm_device_t *dev ); +extern int drm_fb_loaded; +extern int __devinit drm_init(struct pci_driver *driver, + struct pci_device_id *pciidlist, + struct drm_driver_fn *driver_fn); +extern void __exit drm_exit(struct pci_driver *driver); +extern void __exit drm_cleanup_pci(struct pci_dev *pdev); +extern int drm_version(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_takedown(drm_device_t * dev); /* Device support (drm_fops.h) */ -extern int drm_open(struct inode *inode, struct file *filp); -extern int drm_stub_open(struct inode *inode, struct file *filp); -extern int drm_open_helper(struct inode *inode, struct file *filp, - drm_device_t *dev); -extern int drm_fasync(int fd, struct file *filp, int on); -extern int drm_release(struct inode *inode, struct file *filp); +extern int drm_open(struct inode *inode, struct file *filp); +extern int drm_stub_open(struct inode *inode, struct file *filp); +extern int drm_open_helper(struct inode *inode, struct file *filp, + drm_device_t * dev); +extern int drm_fasync(int fd, struct file *filp, int on); +extern int drm_release(struct inode *inode, struct file *filp); /* Mapping support (drm_vm.h) */ -extern void drm_vm_open(struct vm_area_struct *vma); -extern void drm_vm_close(struct vm_area_struct *vma); -extern void drm_vm_shm_close(struct vm_area_struct *vma); -extern int drm_mmap_dma(struct file *filp, - struct vm_area_struct *vma); -extern int drm_mmap(struct file *filp, struct vm_area_struct *vma); +extern void drm_vm_open(struct vm_area_struct *vma); +extern void drm_vm_close(struct vm_area_struct *vma); +extern void drm_vm_shm_close(struct vm_area_struct *vma); +extern int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma); +extern int drm_mmap(struct file *filp, struct vm_area_struct *vma); +extern unsigned long drm_core_get_map_ofs(drm_map_t * map); +extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev); /* Memory management support (drm_memory.h) */ #include "drm_memory.h" -extern void drm_mem_init(void); -extern int drm_mem_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); -extern void *drm_calloc(size_t nmemb, size_t size, int area); -extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, - int area); +extern void drm_mem_init(void); +extern int drm_mem_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +extern void *drm_calloc(size_t nmemb, size_t size, int area); +extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area); extern unsigned long drm_alloc_pages(int order, int area); -extern void drm_free_pages(unsigned long address, int order, - int area); -extern DRM_AGP_MEM *drm_alloc_agp(int pages, u32 type); -extern int drm_free_agp(DRM_AGP_MEM *handle, int pages); -extern int drm_bind_agp(DRM_AGP_MEM *handle, unsigned int start); -extern int drm_unbind_agp(DRM_AGP_MEM *handle); +extern void drm_free_pages(unsigned long address, int order, int area); +extern DRM_AGP_MEM *drm_alloc_agp(int pages, u32 type); +extern int drm_free_agp(DRM_AGP_MEM * handle, int pages); +extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start); +extern int drm_unbind_agp(DRM_AGP_MEM * handle); /* Misc. IOCTL support (drm_ioctl.h) */ -extern int drm_irq_by_busid(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_getunique(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_setunique(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_getmap(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_getclient(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_getstats(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_setversion(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_noop(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); +extern int drm_irq_by_busid(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getunique(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_setunique(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getclient(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getstats(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_setversion(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_noop(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); /* Context IOCTL support (drm_context.h) */ -extern int drm_resctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_addctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_modctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_getctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_switchctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_newctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_rmctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); - -extern int drm_context_switch(drm_device_t *dev, int old, int new); -extern int drm_context_switch_complete(drm_device_t *dev, int new); - -extern int drm_ctxbitmap_init( drm_device_t *dev ); -extern void drm_ctxbitmap_cleanup( drm_device_t *dev ); -extern void drm_ctxbitmap_free( drm_device_t *dev, int ctx_handle ); - -extern int drm_setsareactx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_getsareactx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); +extern int drm_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +extern int drm_context_switch(drm_device_t * dev, int old, int new); +extern int drm_context_switch_complete(drm_device_t * dev, int new); + +extern int drm_ctxbitmap_init(drm_device_t * dev); +extern void drm_ctxbitmap_cleanup(drm_device_t * dev); +extern void drm_ctxbitmap_free(drm_device_t * dev, int ctx_handle); + +extern int drm_setsareactx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getsareactx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); /* Drawable IOCTL support (drm_drawable.h) */ -extern int drm_adddraw(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_rmdraw(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); - +extern int drm_adddraw(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_rmdraw(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); /* Authentication IOCTL support (drm_auth.h) */ -extern int drm_add_magic(drm_device_t *dev, drm_file_t *priv, - drm_magic_t magic); -extern int drm_remove_magic(drm_device_t *dev, drm_magic_t magic); -extern int drm_getmagic(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_authmagic(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); +extern int drm_add_magic(drm_device_t * dev, drm_file_t * priv, + drm_magic_t magic); +extern int drm_remove_magic(drm_device_t * dev, drm_magic_t magic); +extern int drm_getmagic(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_authmagic(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); /* Locking IOCTL support (drm_lock.h) */ -extern int drm_lock(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_unlock(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_lock_take(__volatile__ unsigned int *lock, - unsigned int context); -extern int drm_lock_transfer(drm_device_t *dev, - __volatile__ unsigned int *lock, - unsigned int context); -extern int drm_lock_free(drm_device_t *dev, - __volatile__ unsigned int *lock, - unsigned int context); -extern int drm_notifier(void *priv); +extern int drm_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context); +extern int drm_lock_transfer(drm_device_t * dev, + __volatile__ unsigned int *lock, + unsigned int context); +extern int drm_lock_free(drm_device_t * dev, + __volatile__ unsigned int *lock, unsigned int context); +extern int drm_notifier(void *priv); /* Buffer management support (drm_bufs.h) */ -extern int drm_addmap( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_rmmap( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_initmap( drm_device_t *dev, unsigned int offset, - unsigned int size, int type, int flags ); -extern int drm_addbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_infobufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_markbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_freebufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_mapbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); +extern int drm_addmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_rmmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_initmap(drm_device_t * dev, unsigned int offset, + unsigned int size, int type, int flags); +extern int drm_addbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_infobufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_markbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_freebufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_mapbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); /* DMA support (drm_dma.h) */ -extern int drm_dma_setup(drm_device_t *dev); -extern void drm_dma_takedown(drm_device_t *dev); -extern void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf); -extern void drm_core_reclaim_buffers( struct file *filp ); +extern int drm_dma_setup(drm_device_t * dev); +extern void drm_dma_takedown(drm_device_t * dev); +extern void drm_free_buffer(drm_device_t * dev, drm_buf_t * buf); +extern void drm_core_reclaim_buffers(struct file *filp); /* IRQ support (drm_irq.h) */ -extern int drm_control( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_irq_install( drm_device_t *dev ); -extern int drm_irq_uninstall( drm_device_t *dev ); -extern irqreturn_t drm_irq_handler( DRM_IRQ_ARGS ); -extern void drm_driver_irq_preinstall( drm_device_t *dev ); -extern void drm_driver_irq_postinstall( drm_device_t *dev ); -extern void drm_driver_irq_uninstall( drm_device_t *dev ); - -extern int drm_wait_vblank(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_vblank_wait(drm_device_t *dev, unsigned int *vbl_seq); -extern void drm_vbl_send_signals( drm_device_t *dev ); - +extern int drm_control(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_irq_install(drm_device_t * dev); +extern int drm_irq_uninstall(drm_device_t * dev); +extern irqreturn_t drm_irq_handler(DRM_IRQ_ARGS); +extern void drm_driver_irq_preinstall(drm_device_t * dev); +extern void drm_driver_irq_postinstall(drm_device_t * dev); +extern void drm_driver_irq_uninstall(drm_device_t * dev); + +extern int drm_wait_vblank(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_vblank_wait(drm_device_t * dev, unsigned int *vbl_seq); +extern void drm_vbl_send_signals(drm_device_t * dev); /* AGP/GART support (drm_agpsupport.h) */ extern const drm_agp_t *drm_agp; extern drm_agp_head_t *drm_agp_init(void); -extern int drm_agp_acquire(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern void drm_agp_do_release(void); -extern int drm_agp_release(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_enable(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_info(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_alloc(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_free(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_unbind(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_bind(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern DRM_AGP_MEM *drm_agp_allocate_memory(size_t pages, u32 type); -extern int drm_agp_free_memory(DRM_AGP_MEM *handle); -extern int drm_agp_bind_memory(DRM_AGP_MEM *handle, off_t start); -extern int drm_agp_unbind_memory(DRM_AGP_MEM *handle); +extern int drm_agp_acquire(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern void drm_agp_do_release(void); +extern int drm_agp_release(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_enable(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_info(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_alloc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_free(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_unbind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_bind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern DRM_AGP_MEM *drm_agp_allocate_memory(size_t pages, u32 type); +extern int drm_agp_free_memory(DRM_AGP_MEM * handle); +extern int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start); +extern int drm_agp_unbind_memory(DRM_AGP_MEM * handle); /* Stub support (drm_stub.h) */ -extern int drm_probe(struct pci_dev *pdev, const struct pci_device_id *ent, - struct drm_driver_fn *driver_fn); -extern int drm_put_minor(drm_device_t *dev); -extern int drm_get_secondary_minor(drm_device_t *dev, drm_minor_t **sec_minor); -extern int drm_put_secondary_minor(drm_minor_t *sec_minor); -extern unsigned int cards_limit; -extern drm_minor_t *drm_minors; +extern int drm_probe(struct pci_dev *pdev, const struct pci_device_id *ent, + struct drm_driver_fn *driver_fn); +extern int drm_put_minor(drm_device_t * dev); +extern int drm_get_secondary_minor(drm_device_t * dev, + drm_minor_t ** sec_minor); +extern int drm_put_secondary_minor(drm_minor_t * sec_minor); +extern unsigned int cards_limit; +extern drm_minor_t *drm_minors; extern struct drm_sysfs_class *drm_class; extern struct proc_dir_entry *drm_proc_root; /* Proc support (drm_proc.h) */ -extern int drm_proc_init(drm_device_t *dev, - int minor, - struct proc_dir_entry *root, - struct proc_dir_entry **dev_root); -extern int drm_proc_cleanup(int minor, - struct proc_dir_entry *root, - struct proc_dir_entry *dev_root); +extern int drm_proc_init(drm_device_t * dev, + int minor, + struct proc_dir_entry *root, + struct proc_dir_entry **dev_root); +extern int drm_proc_cleanup(int minor, + struct proc_dir_entry *root, + struct proc_dir_entry *dev_root); /* Scatter Gather Support (drm_scatter.h) */ -extern void drm_sg_cleanup(drm_sg_mem_t *entry); -extern int drm_sg_alloc(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_sg_free(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); - - /* ATI PCIGART support (ati_pcigart.h) */ -extern int drm_ati_pcigart_init(drm_device_t *dev, - unsigned long *addr, - dma_addr_t *bus_addr); -extern int drm_ati_pcigart_cleanup(drm_device_t *dev, - unsigned long addr, - dma_addr_t bus_addr); - -extern void *drm_pci_alloc(drm_device_t *dev, size_t size, - size_t align, dma_addr_t maxaddr, - dma_addr_t *busaddr); -extern void drm_pci_free(drm_device_t *dev, size_t size, - void *vaddr, dma_addr_t busaddr); - - /* sysfs support (drm_sysfs.c) */ +extern void drm_sg_cleanup(drm_sg_mem_t * entry); +extern int drm_sg_alloc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_sg_free(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* ATI PCIGART support (ati_pcigart.h) */ +extern int drm_ati_pcigart_init(drm_device_t * dev, + unsigned long *addr, dma_addr_t * bus_addr); +extern int drm_ati_pcigart_cleanup(drm_device_t * dev, + unsigned long addr, dma_addr_t bus_addr); + +extern void *drm_pci_alloc(drm_device_t * dev, size_t size, + size_t align, dma_addr_t maxaddr, + dma_addr_t * busaddr); +extern void drm_pci_free(drm_device_t * dev, size_t size, + void *vaddr, dma_addr_t busaddr); + + /* sysfs support (drm_sysfs.c) */ struct drm_sysfs_class; -extern struct drm_sysfs_class *drm_sysfs_create(struct module *owner, char *name); -extern void drm_sysfs_destroy(struct drm_sysfs_class *cs); +extern struct drm_sysfs_class *drm_sysfs_create(struct module *owner, + char *name); +extern void drm_sysfs_destroy(struct drm_sysfs_class *cs); extern struct class_device *drm_sysfs_device_add(struct drm_sysfs_class *cs, - dev_t dev, struct device *device, const char *fmt, ...); -extern void drm_sysfs_device_remove(dev_t dev); - + dev_t dev, + struct device *device, + const char *fmt, ...); +extern void drm_sysfs_device_remove(dev_t dev); /* Inline replacements for DRM_IOREMAP macros */ -static __inline__ void drm_core_ioremap(struct drm_map *map, struct drm_device *dev) +static __inline__ void drm_core_ioremap(struct drm_map *map, + struct drm_device *dev) { - map->handle = drm_ioremap( map->offset, map->size, dev ); + map->handle = drm_ioremap(map->offset, map->size, dev); } -static __inline__ void drm_core_ioremap_nocache(struct drm_map *map, struct drm_device *dev) +static __inline__ void drm_core_ioremap_nocache(struct drm_map *map, + struct drm_device *dev) { map->handle = drm_ioremap_nocache(map->offset, map->size, dev); } -static __inline__ void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev) +static __inline__ void drm_core_ioremapfree(struct drm_map *map, + struct drm_device *dev) { - if ( map->handle && map->size ) - drm_ioremapfree( map->handle, map->size, dev ); + if (map->handle && map->size) + drm_ioremapfree(map->handle, map->size, dev); } -static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev, unsigned long offset) +static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev, + unsigned long offset) { struct list_head *_list; - list_for_each( _list, &dev->maplist->head ) { - drm_map_list_t *_entry = list_entry( _list, drm_map_list_t, head ); - if ( _entry->map && - _entry->map->offset == offset ) { + list_for_each(_list, &dev->maplist->head) { + drm_map_list_t *_entry = + list_entry(_list, drm_map_list_t, head); + if (_entry->map && _entry->map->offset == offset) { return _entry->map; } } @@ -1028,7 +1023,5 @@ extern void drm_free(void *pt, size_t size, int area); /*@}*/ -extern unsigned long drm_core_get_map_ofs(drm_map_t *map); -extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev); -#endif /* __KERNEL__ */ +#endif /* __KERNEL__ */ #endif diff --git a/linux-core/drm_agpsupport.c b/linux-core/drm_agpsupport.c index bdb57a97..d43d82d8 100644 --- a/linux-core/drm_agpsupport.c +++ b/linux-core/drm_agpsupport.c @@ -1,7 +1,7 @@ /** - * \file drm_agpsupport.h + * \file drm_agpsupport.h * DRM support for AGP/GART backend - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -54,28 +54,28 @@ const drm_agp_t *drm_agp = NULL; * drm_agp_info structure with the information in drm_agp_head::agp_info. */ int drm_agp_info(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - DRM_AGP_KERN *kern; - drm_agp_info_t info; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + DRM_AGP_KERN *kern; + drm_agp_info_t info; if (!dev->agp || !dev->agp->acquired || !drm_agp->copy_info) return -EINVAL; - kern = &dev->agp->agp_info; + kern = &dev->agp->agp_info; info.agp_version_major = kern->version.major; info.agp_version_minor = kern->version.minor; - info.mode = kern->mode; - info.aperture_base = kern->aper_base; - info.aperture_size = kern->aper_size * 1024 * 1024; - info.memory_allowed = kern->max_memory << PAGE_SHIFT; - info.memory_used = kern->current_memory << PAGE_SHIFT; - info.id_vendor = kern->device->vendor; - info.id_device = kern->device->device; - - if (copy_to_user((drm_agp_info_t __user *)arg, &info, sizeof(info))) + info.mode = kern->mode; + info.aperture_base = kern->aper_base; + info.aperture_size = kern->aper_size * 1024 * 1024; + info.memory_allowed = kern->max_memory << PAGE_SHIFT; + info.memory_used = kern->current_memory << PAGE_SHIFT; + info.id_vendor = kern->device->vendor; + info.id_device = kern->device->device; + + if (copy_to_user((drm_agp_info_t __user *) arg, &info, sizeof(info))) return -EFAULT; return 0; } @@ -87,17 +87,17 @@ int drm_agp_info(struct inode *inode, struct file *filp, * \param filp file pointer. * \param cmd command. * \param arg user argument. - * \return zero on success or a negative number on failure. + * \return zero on success or a negative number on failure. * * Verifies the AGP device hasn't been acquired before and calls * drm_agp->acquire(). */ int drm_agp_acquire(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - int retcode; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode; if (!dev->agp) return -ENODEV; @@ -106,7 +106,7 @@ int drm_agp_acquire(struct inode *inode, struct file *filp, if (!drm_agp->acquire) return -EINVAL; #ifndef VMAP_4_ARGS - if ( dev->agp->cant_use_aperture ) + if (dev->agp->cant_use_aperture) return -EINVAL; #endif if ((retcode = drm_agp->acquire())) @@ -127,10 +127,10 @@ int drm_agp_acquire(struct inode *inode, struct file *filp, * Verifies the AGP device has been acquired and calls drm_agp->release(). */ int drm_agp_release(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; if (!dev->agp || !dev->agp->acquired || !drm_agp->release) return -EINVAL; @@ -153,7 +153,7 @@ void drm_agp_do_release(void) /** * Enable the AGP bus. - * + * * \param inode device inode. * \param filp file pointer. * \param cmd command. @@ -164,21 +164,21 @@ void drm_agp_do_release(void) * drm_agp->enable(). */ int drm_agp_enable(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_agp_mode_t mode; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_agp_mode_t mode; if (!dev->agp || !dev->agp->acquired || !drm_agp->enable) return -EINVAL; - if (copy_from_user(&mode, (drm_agp_mode_t __user *)arg, sizeof(mode))) + if (copy_from_user(&mode, (drm_agp_mode_t __user *) arg, sizeof(mode))) return -EFAULT; - dev->agp->mode = mode.mode; + dev->agp->mode = mode.mode; drm_agp->enable(mode.mode); - dev->agp->base = dev->agp->agp_info.aper_base; + dev->agp->base = dev->agp->agp_info.aper_base; dev->agp->enabled = 1; return 0; } @@ -191,20 +191,20 @@ int drm_agp_enable(struct inode *inode, struct file *filp, * \param cmd command. * \param arg pointer to a drm_agp_buffer structure. * \return zero on success or a negative number on failure. - * + * * Verifies the AGP device is present and has been acquired, allocates the * memory via alloc_agp() and creates a drm_agp_mem entry for it. */ int drm_agp_alloc(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_agp_buffer_t request; - drm_agp_mem_t *entry; - DRM_AGP_MEM *memory; - unsigned long pages; - u32 type; + drm_agp_mem_t *entry; + DRM_AGP_MEM *memory; + unsigned long pages; + u32 type; drm_agp_buffer_t __user *argp = (void __user *)arg; if (!dev->agp || !dev->agp->acquired) @@ -214,7 +214,7 @@ int drm_agp_alloc(struct inode *inode, struct file *filp, if (!(entry = drm_alloc(sizeof(*entry), DRM_MEM_AGPLISTS))) return -ENOMEM; - memset(entry, 0, sizeof(*entry)); + memset(entry, 0, sizeof(*entry)); pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE; type = (u32) request.type; @@ -224,21 +224,21 @@ int drm_agp_alloc(struct inode *inode, struct file *filp, return -ENOMEM; } - entry->handle = (unsigned long)memory->key + 1; - entry->memory = memory; - entry->bound = 0; - entry->pages = pages; - entry->prev = NULL; - entry->next = dev->agp->memory; + entry->handle = (unsigned long)memory->key + 1; + entry->memory = memory; + entry->bound = 0; + entry->pages = pages; + entry->prev = NULL; + entry->next = dev->agp->memory; if (dev->agp->memory) dev->agp->memory->prev = entry; dev->agp->memory = entry; - request.handle = entry->handle; + request.handle = entry->handle; request.physical = memory->physical; if (copy_to_user(argp, &request, sizeof(request))) { - dev->agp->memory = entry->next; + dev->agp->memory = entry->next; dev->agp->memory->prev = NULL; drm_free_agp(memory, pages); drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); @@ -253,11 +253,11 @@ int drm_agp_alloc(struct inode *inode, struct file *filp, * \param dev DRM device structure. * \param handle AGP memory handle. * \return pointer to the drm_agp_mem structure associated with \p handle. - * + * * Walks through drm_agp_head::memory until finding a matching handle. */ -static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t *dev, - unsigned long handle) +static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t * dev, + unsigned long handle) { drm_agp_mem_t *entry; @@ -281,17 +281,18 @@ static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t *dev, * entry and passes it to the unbind_agp() function. */ int drm_agp_unbind(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_agp_binding_t request; - drm_agp_mem_t *entry; + drm_agp_mem_t *entry; int ret; if (!dev->agp || !dev->agp->acquired) return -EINVAL; - if (copy_from_user(&request, (drm_agp_binding_t __user *)arg, sizeof(request))) + if (copy_from_user + (&request, (drm_agp_binding_t __user *) arg, sizeof(request))) return -EFAULT; if (!(entry = drm_agp_lookup_entry(dev, request.handle))) return -EINVAL; @@ -299,7 +300,7 @@ int drm_agp_unbind(struct inode *inode, struct file *filp, return -EINVAL; ret = drm_unbind_agp(entry->memory); if (ret == 0) - entry->bound = 0; + entry->bound = 0; return ret; } @@ -317,18 +318,19 @@ int drm_agp_unbind(struct inode *inode, struct file *filp, * it to bind_agp() function. */ int drm_agp_bind(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_agp_binding_t request; - drm_agp_mem_t *entry; - int retcode; - int page; + drm_agp_mem_t *entry; + int retcode; + int page; if (!dev->agp || !dev->agp->acquired || !drm_agp->bind_memory) return -EINVAL; - if (copy_from_user(&request, (drm_agp_binding_t __user *)arg, sizeof(request))) + if (copy_from_user + (&request, (drm_agp_binding_t __user *) arg, sizeof(request))) return -EFAULT; if (!(entry = drm_agp_lookup_entry(dev, request.handle))) return -EINVAL; @@ -358,16 +360,17 @@ int drm_agp_bind(struct inode *inode, struct file *filp, * and unlinks from the doubly linked list it's inserted in. */ int drm_agp_free(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_agp_buffer_t request; - drm_agp_mem_t *entry; + drm_agp_mem_t *entry; if (!dev->agp || !dev->agp->acquired) return -EINVAL; - if (copy_from_user(&request, (drm_agp_buffer_t __user *)arg, sizeof(request))) + if (copy_from_user + (&request, (drm_agp_buffer_t __user *) arg, sizeof(request))) return -EFAULT; if (!(entry = drm_agp_lookup_entry(dev, request.handle))) return -EINVAL; @@ -430,7 +433,7 @@ DRM_AGP_MEM *drm_agp_allocate_memory(size_t pages, u32 type) } /** Calls drm_agp->free_memory() */ -int drm_agp_free_memory(DRM_AGP_MEM *handle) +int drm_agp_free_memory(DRM_AGP_MEM * handle) { if (!handle || !drm_agp->free_memory) return 0; @@ -439,7 +442,7 @@ int drm_agp_free_memory(DRM_AGP_MEM *handle) } /** Calls drm_agp->bind_memory() */ -int drm_agp_bind_memory(DRM_AGP_MEM *handle, off_t start) +int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start) { if (!handle || !drm_agp->bind_memory) return -EINVAL; @@ -447,11 +450,11 @@ int drm_agp_bind_memory(DRM_AGP_MEM *handle, off_t start) } /** Calls drm_agp->unbind_memory() */ -int drm_agp_unbind_memory(DRM_AGP_MEM *handle) +int drm_agp_unbind_memory(DRM_AGP_MEM * handle) { if (!handle || !drm_agp->unbind_memory) return -EINVAL; return drm_agp->unbind_memory(handle); } -#endif /* __OS_HAS_AGP */ +#endif /* __OS_HAS_AGP */ diff --git a/linux-core/drm_auth.c b/linux-core/drm_auth.c index 84c39f74..a949500f 100644 --- a/linux-core/drm_auth.c +++ b/linux-core/drm_auth.c @@ -1,5 +1,5 @@ /** - * \file drm_auth.h + * \file drm_auth.h * IOCTLs for authentication * * \author Rickard E. (Rik) Faith @@ -46,7 +46,7 @@ */ static int drm_hash_magic(drm_magic_t magic) { - return magic & (DRM_HASH_SIZE-1); + return magic & (DRM_HASH_SIZE - 1); } /** @@ -59,11 +59,11 @@ static int drm_hash_magic(drm_magic_t magic) * the one with matching magic number, while holding the drm_device::struct_sem * lock. */ -static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic) +static drm_file_t *drm_find_file(drm_device_t * dev, drm_magic_t magic) { - drm_file_t *retval = NULL; + drm_file_t *retval = NULL; drm_magic_entry_t *pt; - int hash = drm_hash_magic(magic); + int hash = drm_hash_magic(magic); down(&dev->struct_sem); for (pt = dev->magiclist[hash].head; pt; pt = pt->next) { @@ -78,7 +78,7 @@ static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic) /** * Adds a magic number. - * + * * \param dev DRM device. * \param priv file private data. * \param magic magic number. @@ -87,28 +87,29 @@ static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic) * associated the magic number hash key in drm_device::magiclist, while holding * the drm_device::struct_sem lock. */ -int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic) +int drm_add_magic(drm_device_t * dev, drm_file_t * priv, drm_magic_t magic) { - int hash; + int hash; drm_magic_entry_t *entry; DRM_DEBUG("%d\n", magic); - hash = drm_hash_magic(magic); - entry = drm_alloc(sizeof(*entry), DRM_MEM_MAGIC); - if (!entry) return -ENOMEM; + hash = drm_hash_magic(magic); + entry = drm_alloc(sizeof(*entry), DRM_MEM_MAGIC); + if (!entry) + return -ENOMEM; memset(entry, 0, sizeof(*entry)); entry->magic = magic; - entry->priv = priv; - entry->next = NULL; + entry->priv = priv; + entry->next = NULL; down(&dev->struct_sem); if (dev->magiclist[hash].tail) { dev->magiclist[hash].tail->next = entry; - dev->magiclist[hash].tail = entry; + dev->magiclist[hash].tail = entry; } else { - dev->magiclist[hash].head = entry; - dev->magiclist[hash].tail = entry; + dev->magiclist[hash].head = entry; + dev->magiclist[hash].tail = entry; } up(&dev->struct_sem); @@ -117,19 +118,18 @@ int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic) /** * Remove a magic number. - * + * * \param dev DRM device. * \param magic magic number. * * Searches and unlinks the entry in drm_device::magiclist with the magic * number hash key, while holding the drm_device::struct_sem lock. */ -int drm_remove_magic(drm_device_t *dev, drm_magic_t magic) +int drm_remove_magic(drm_device_t * dev, drm_magic_t magic) { drm_magic_entry_t *prev = NULL; drm_magic_entry_t *pt; - int hash; - + int hash; DRM_DEBUG("%d\n", magic); hash = drm_hash_magic(magic); @@ -171,21 +171,22 @@ int drm_remove_magic(drm_device_t *dev, drm_magic_t magic) * filp. */ int drm_getmagic(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { static drm_magic_t sequence = 0; - static spinlock_t lock = SPIN_LOCK_UNLOCKED; - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_auth_t auth; + static spinlock_t lock = SPIN_LOCK_UNLOCKED; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_auth_t auth; - /* Find unique magic */ + /* Find unique magic */ if (priv->magic) { auth.magic = priv->magic; } else { do { spin_lock(&lock); - if (!sequence) ++sequence; /* reserve 0 */ + if (!sequence) + ++sequence; /* reserve 0 */ auth.magic = sequence++; spin_unlock(&lock); } while (drm_find_file(dev, auth.magic)); @@ -194,7 +195,7 @@ int drm_getmagic(struct inode *inode, struct file *filp, } DRM_DEBUG("%u\n", auth.magic); - if (copy_to_user((drm_auth_t __user *)arg, &auth, sizeof(auth))) + if (copy_to_user((drm_auth_t __user *) arg, &auth, sizeof(auth))) return -EFAULT; return 0; } @@ -211,14 +212,14 @@ int drm_getmagic(struct inode *inode, struct file *filp, * Checks if \p filp is associated with the magic number passed in \arg. */ int drm_authmagic(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_auth_t auth; - drm_file_t *file; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_auth_t auth; + drm_file_t *file; - if (copy_from_user(&auth, (drm_auth_t __user *)arg, sizeof(auth))) + if (copy_from_user(&auth, (drm_auth_t __user *) arg, sizeof(auth))) return -EFAULT; DRM_DEBUG("%u\n", auth.magic); if ((file = drm_find_file(dev, auth.magic))) { diff --git a/linux-core/drm_bufs.c b/linux-core/drm_bufs.c index 602dd3f8..ca5aacae 100644 --- a/linux-core/drm_bufs.c +++ b/linux-core/drm_bufs.c @@ -1,7 +1,7 @@ /** - * \file drm_bufs.h + * \file drm_bufs.h * Generic buffer template - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -41,59 +41,55 @@ * type. Adds the map to the map list drm_device::maplist. Adds MTRR's where * applicable and if supported by the kernel. */ -int drm_initmap( drm_device_t *dev, unsigned int offset, unsigned int size, int type, int flags ) +int drm_initmap(drm_device_t * dev, unsigned int offset, unsigned int size, + int type, int flags) { drm_map_t *map; drm_map_list_t *list; DRM_DEBUG("\n"); - if ( (offset & (~PAGE_MASK)) || (size & (~PAGE_MASK)) ) + if ((offset & (~PAGE_MASK)) || (size & (~PAGE_MASK))) return -EINVAL; #if !defined(__sparc__) && !defined(__alpha__) - if ( offset + size < offset || offset < virt_to_phys(high_memory) ) + if (offset + size < offset || offset < virt_to_phys(high_memory)) return -EINVAL; #endif - if ( !(list = drm_alloc( sizeof(*list), DRM_MEM_MAPS ))) + if (!(list = drm_alloc(sizeof(*list), DRM_MEM_MAPS))) return -ENOMEM; memset(list, 0, sizeof(*list)); - - if ( !(map = drm_alloc( sizeof(*map), DRM_MEM_MAPS ))) { + + if (!(map = drm_alloc(sizeof(*map), DRM_MEM_MAPS))) { drm_free(list, sizeof(*list), DRM_MEM_MAPS); return -ENOMEM; } - *map = (drm_map_t){ - .offset = offset, - .size = size, - .type = type, - .flags = flags, - .mtrr = -1, - .handle = 0, - }; + *map = (drm_map_t) { + .offset = offset,.size = size,.type = type,.flags = + flags,.mtrr = -1,.handle = 0,}; list->map = map; - DRM_DEBUG( "initmap offset = 0x%08lx, size = 0x%08lx, type = %d\n", - map->offset, map->size, map->type ); + DRM_DEBUG("initmap offset = 0x%08lx, size = 0x%08lx, type = %d\n", + map->offset, map->size, map->type); #ifdef __alpha__ map->offset += dev->hose->mem_space->start; #endif if (drm_core_has_MTRR(dev)) { - if ( map->type == _DRM_FRAME_BUFFER || - (map->flags & _DRM_WRITE_COMBINING) ) { - map->mtrr = mtrr_add( map->offset, map->size, - MTRR_TYPE_WRCOMB, 1 ); + if (map->type == _DRM_FRAME_BUFFER || + (map->flags & _DRM_WRITE_COMBINING)) { + map->mtrr = mtrr_add(map->offset, map->size, + MTRR_TYPE_WRCOMB, 1); } } if (map->type == _DRM_REGISTERS) - map->handle = drm_ioremap( map->offset, map->size, dev ); + map->handle = drm_ioremap(map->offset, map->size, dev); down(&dev->struct_sem); list_add(&list->head, &dev->maplist->head); up(&dev->struct_sem); - + dev->fn_tbl->permanent_maps = 1; DRM_DEBUG("finished\n"); @@ -114,8 +110,8 @@ EXPORT_SYMBOL(drm_initmap); * type. Adds the map to the map list drm_device::maplist. Adds MTRR's where * applicable and if supported by the kernel. */ -int drm_addmap( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_addmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -123,14 +119,15 @@ int drm_addmap( struct inode *inode, struct file *filp, drm_map_t __user *argp = (void __user *)arg; drm_map_list_t *list; - if ( !(filp->f_mode & 3) ) return -EACCES; /* Require read/write */ + if (!(filp->f_mode & 3)) + return -EACCES; /* Require read/write */ - map = drm_alloc( sizeof(*map), DRM_MEM_MAPS ); - if ( !map ) + map = drm_alloc(sizeof(*map), DRM_MEM_MAPS); + if (!map) return -ENOMEM; - if ( copy_from_user( map, argp, sizeof(*map) ) ) { - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + if (copy_from_user(map, argp, sizeof(*map))) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EFAULT; } @@ -138,86 +135,97 @@ int drm_addmap( struct inode *inode, struct file *filp, * book keeping information about shared memory to allow for removal * when processes fork. */ - if ( (map->flags & _DRM_REMOVABLE) && map->type != _DRM_SHM ) { - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + if ((map->flags & _DRM_REMOVABLE) && map->type != _DRM_SHM) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EINVAL; } - DRM_DEBUG( "offset = 0x%08lx, size = 0x%08lx, type = %d\n", - map->offset, map->size, map->type ); - if ( (map->offset & (~PAGE_MASK)) || (map->size & (~PAGE_MASK)) ) { - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + DRM_DEBUG("offset = 0x%08lx, size = 0x%08lx, type = %d\n", + map->offset, map->size, map->type); + if ((map->offset & (~PAGE_MASK)) || (map->size & (~PAGE_MASK))) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EINVAL; } - map->mtrr = -1; + map->mtrr = -1; map->handle = NULL; - switch ( map->type ) { + switch (map->type) { case _DRM_REGISTERS: - case _DRM_FRAME_BUFFER: { - /* after all the drivers switch to permanent mapping this should just return an error */ - struct list_head *_list; - - /* If permanent maps are implemented, maps must match */ - if (dev->fn_tbl->permanent_maps) { - DRM_DEBUG( "Looking for: offset = 0x%08lx, size = 0x%08lx, type = %d\n", - map->offset, map->size, map->type ); - list_for_each( _list, &dev->maplist->head ) { - drm_map_list_t *_entry = list_entry( _list, drm_map_list_t, head ); - DRM_DEBUG( "Checking: offset = 0x%08lx, size = 0x%08lx, type = %d\n", - _entry->map->offset, _entry->map->size, _entry->map->type ); - if ( _entry->map && map->type == _entry->map->type && - map->offset == _entry->map->offset ) { - _entry->map->size = map->size; - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); - map = _entry->map; - DRM_DEBUG( "Found existing: offset = 0x%08lx, size = 0x%08lx, type = %d\n", - map->offset, map->size, map->type ); - goto found_it; + case _DRM_FRAME_BUFFER:{ + /* after all the drivers switch to permanent mapping this should just return an error */ + struct list_head *_list; + + /* If permanent maps are implemented, maps must match */ + if (dev->fn_tbl->permanent_maps) { + DRM_DEBUG + ("Looking for: offset = 0x%08lx, size = 0x%08lx, type = %d\n", + map->offset, map->size, map->type); + list_for_each(_list, &dev->maplist->head) { + drm_map_list_t *_entry = + list_entry(_list, drm_map_list_t, + head); + DRM_DEBUG + ("Checking: offset = 0x%08lx, size = 0x%08lx, type = %d\n", + _entry->map->offset, + _entry->map->size, + _entry->map->type); + if (_entry->map + && map->type == _entry->map->type + && map->offset == + _entry->map->offset) { + _entry->map->size = map->size; + drm_free(map, sizeof(*map), + DRM_MEM_MAPS); + map = _entry->map; + DRM_DEBUG + ("Found existing: offset = 0x%08lx, size = 0x%08lx, type = %d\n", + map->offset, map->size, + map->type); + goto found_it; + } } + /* addmap didn't match an existing permanent map, that's an error */ + return -EINVAL; } - /* addmap didn't match an existing permanent map, that's an error */ - return -EINVAL; - } #if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) - if ( map->offset + map->size < map->offset || - map->offset < virt_to_phys(high_memory) ) { - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); - return -EINVAL; - } + if (map->offset + map->size < map->offset || + map->offset < virt_to_phys(high_memory)) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + return -EINVAL; + } #endif #ifdef __alpha__ - map->offset += dev->hose->mem_space->start; + map->offset += dev->hose->mem_space->start; #endif - if (drm_core_has_MTRR(dev)) { - if ( map->type == _DRM_FRAME_BUFFER || - (map->flags & _DRM_WRITE_COMBINING) ) { - map->mtrr = mtrr_add( map->offset, map->size, - MTRR_TYPE_WRCOMB, 1 ); + if (drm_core_has_MTRR(dev)) { + if (map->type == _DRM_FRAME_BUFFER || + (map->flags & _DRM_WRITE_COMBINING)) { + map->mtrr = + mtrr_add(map->offset, map->size, + MTRR_TYPE_WRCOMB, 1); + } } + if (map->type == _DRM_REGISTERS) + map->handle = + drm_ioremap(map->offset, map->size, dev); + break; } - if (map->type == _DRM_REGISTERS) - map->handle = drm_ioremap( map->offset, map->size, - dev ); - break; - } case _DRM_SHM: map->handle = vmalloc_32(map->size); - DRM_DEBUG( "%lu %d %p\n", - map->size, get_order( map->size ), map->handle ); - if ( !map->handle ) { - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + DRM_DEBUG("%lu %d %p\n", + map->size, get_order(map->size), map->handle); + if (!map->handle) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -ENOMEM; } map->offset = (unsigned long)map->handle; - if ( map->flags & _DRM_CONTAINS_LOCK ) { + if (map->flags & _DRM_CONTAINS_LOCK) { /* Prevent a 2nd X Server from creating a 2nd lock */ if (dev->lock.hw_lock != NULL) { - vfree( map->handle ); - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + vfree(map->handle); + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EBUSY; } - dev->sigdata.lock = - dev->lock.hw_lock = map->handle; /* Pointer to lock */ + dev->sigdata.lock = dev->lock.hw_lock = map->handle; /* Pointer to lock */ } break; case _DRM_AGP: @@ -226,7 +234,7 @@ int drm_addmap( struct inode *inode, struct file *filp, map->offset += dev->hose->mem_space->start; #endif map->offset += dev->agp->base; - map->mtrr = dev->agp->agp_mtrr; /* for getmap */ + map->mtrr = dev->agp->agp_mtrr; /* for getmap */ } break; case _DRM_SCATTER_GATHER: @@ -238,12 +246,12 @@ int drm_addmap( struct inode *inode, struct file *filp, break; default: - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EINVAL; } list = drm_alloc(sizeof(*list), DRM_MEM_MAPS); - if(!list) { + if (!list) { drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EINVAL; } @@ -252,20 +260,18 @@ int drm_addmap( struct inode *inode, struct file *filp, down(&dev->struct_sem); list_add(&list->head, &dev->maplist->head); - up(&dev->struct_sem); -found_it: - if ( copy_to_user( argp, map, sizeof(*map) ) ) + up(&dev->struct_sem); + found_it: + if (copy_to_user(argp, map, sizeof(*map))) return -EFAULT; - if ( map->type != _DRM_SHM ) { - if ( copy_to_user( &argp->handle, - &map->offset, - sizeof(map->offset) ) ) + if (map->type != _DRM_SHM) { + if (copy_to_user(&argp->handle, + &map->offset, sizeof(map->offset))) return -EFAULT; } return 0; } - /** * Remove a map private from list and deallocate resources if the mapping * isn't in use. @@ -283,10 +289,10 @@ found_it: * \sa addmap(). */ int drm_rmmap(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; struct list_head *list; drm_map_list_t *r_list = NULL; drm_vma_entry_t *pt, *prev; @@ -294,30 +300,30 @@ int drm_rmmap(struct inode *inode, struct file *filp, drm_map_t request; int found_maps = 0; - if (copy_from_user(&request, (drm_map_t __user *)arg, - sizeof(request))) { + if (copy_from_user(&request, (drm_map_t __user *) arg, sizeof(request))) { return -EFAULT; } - + down(&dev->struct_sem); list = &dev->maplist->head; list_for_each(list, &dev->maplist->head) { r_list = list_entry(list, drm_map_list_t, head); - if(r_list->map && - r_list->map->handle == request.handle && - r_list->map->flags & _DRM_REMOVABLE) break; + if (r_list->map && + r_list->map->handle == request.handle && + r_list->map->flags & _DRM_REMOVABLE) + break; } /* List has wrapped around to the head pointer, or its empty we didn't * find anything. */ - if(list == (&dev->maplist->head)) { + if (list == (&dev->maplist->head)) { up(&dev->struct_sem); return -EINVAL; } map = r_list->map; - + /* Register and framebuffer maps are permanent */ if ((map->type == _DRM_REGISTERS) || (map->type == _DRM_FRAME_BUFFER)) { up(&dev->struct_sem); @@ -327,14 +333,15 @@ int drm_rmmap(struct inode *inode, struct file *filp, drm_free(list, sizeof(*list), DRM_MEM_MAPS); for (pt = dev->vmalist, prev = NULL; pt; prev = pt, pt = pt->next) { - if (pt->vma->vm_private_data == map) found_maps++; + if (pt->vma->vm_private_data == map) + found_maps++; } - if(!found_maps) { + if (!found_maps) { switch (map->type) { case _DRM_REGISTERS: case _DRM_FRAME_BUFFER: - break; /* Can't get here, make compiler happy */ + break; /* Can't get here, make compiler happy */ case _DRM_SHM: vfree(map->handle); break; @@ -356,7 +363,7 @@ int drm_rmmap(struct inode *inode, struct file *filp, * * Frees any pages and buffers associated with the given entry. */ -static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry) +static void drm_cleanup_buf_error(drm_device_t * dev, drm_buf_entry_t * entry) { int i; @@ -364,30 +371,27 @@ static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry) for (i = 0; i < entry->seg_count; i++) { if (entry->seglist[i]) { drm_free_pages(entry->seglist[i], - entry->page_order, - DRM_MEM_DMA); + entry->page_order, DRM_MEM_DMA); } } drm_free(entry->seglist, - entry->seg_count * - sizeof(*entry->seglist), - DRM_MEM_SEGS); + entry->seg_count * + sizeof(*entry->seglist), DRM_MEM_SEGS); entry->seg_count = 0; } - if (entry->buf_count) { - for (i = 0; i < entry->buf_count; i++) { + if (entry->buf_count) { + for (i = 0; i < entry->buf_count; i++) { if (entry->buflist[i].dev_private) { drm_free(entry->buflist[i].dev_private, - entry->buflist[i].dev_priv_size, - DRM_MEM_BUFS); + entry->buflist[i].dev_priv_size, + DRM_MEM_BUFS); } } drm_free(entry->buflist, - entry->buf_count * - sizeof(*entry->buflist), - DRM_MEM_BUFS); + entry->buf_count * + sizeof(*entry->buflist), DRM_MEM_BUFS); entry->buf_count = 0; } @@ -402,13 +406,13 @@ static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry) * \param cmd command. * \param arg pointer to a drm_buf_desc_t request. * \return zero on success or a negative number on failure. - * + * * After some sanity checks creates a drm_buf structure for each buffer and * reallocates the buffer list of the same size order to accommodate the new * buffers. */ -int drm_addbufs_agp( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_addbufs_agp(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -429,153 +433,152 @@ int drm_addbufs_agp( struct inode *inode, struct file *filp, drm_buf_t **temp_buflist; drm_buf_desc_t __user *argp = (void __user *)arg; - if ( !dma ) return -EINVAL; + if (!dma) + return -EINVAL; - if ( copy_from_user( &request, argp, - sizeof(request) ) ) + if (copy_from_user(&request, argp, sizeof(request))) return -EFAULT; count = request.count; - order = get_order( request.size ); + order = get_order(request.size); size = 1 << order; - alignment = (request.flags & _DRM_PAGE_ALIGN) - ? PAGE_ALIGN(size) : size; + alignment = (request.flags & _DRM_PAGE_ALIGN) + ? PAGE_ALIGN(size) : size; page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; total = PAGE_SIZE << page_order; byte_count = 0; agp_offset = dev->agp->base + request.agp_start; - DRM_DEBUG( "count: %d\n", count ); - DRM_DEBUG( "order: %d\n", order ); - DRM_DEBUG( "size: %d\n", size ); - DRM_DEBUG( "agp_offset: %lu\n", agp_offset ); - DRM_DEBUG( "alignment: %d\n", alignment ); - DRM_DEBUG( "page_order: %d\n", page_order ); - DRM_DEBUG( "total: %d\n", total ); + DRM_DEBUG("count: %d\n", count); + DRM_DEBUG("order: %d\n", order); + DRM_DEBUG("size: %d\n", size); + DRM_DEBUG("agp_offset: %lu\n", agp_offset); + DRM_DEBUG("alignment: %d\n", alignment); + DRM_DEBUG("page_order: %d\n", page_order); + DRM_DEBUG("total: %d\n", total); - if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; - if ( dev->queue_count ) return -EBUSY; /* Not while in use */ + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) + return -EINVAL; + if (dev->queue_count) + return -EBUSY; /* Not while in use */ - spin_lock( &dev->count_lock ); - if ( dev->buf_use ) { - spin_unlock( &dev->count_lock ); + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); return -EBUSY; } - atomic_inc( &dev->buf_alloc ); - spin_unlock( &dev->count_lock ); + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); - down( &dev->struct_sem ); + down(&dev->struct_sem); entry = &dma->bufs[order]; - if ( entry->buf_count ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); - return -ENOMEM; /* May only call once for each order */ + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; /* May only call once for each order */ } if (count < 0 || count > 4096) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -EINVAL; } - entry->buflist = drm_alloc( count * sizeof(*entry->buflist), - DRM_MEM_BUFS ); - if ( !entry->buflist ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); entry->buf_size = size; entry->page_order = page_order; offset = 0; - while ( entry->buf_count < count ) { - buf = &entry->buflist[entry->buf_count]; - buf->idx = dma->buf_count + entry->buf_count; - buf->total = alignment; - buf->order = order; - buf->used = 0; + while (entry->buf_count < count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; - buf->offset = (dma->byte_count + offset); + buf->offset = (dma->byte_count + offset); buf->bus_address = agp_offset + offset; buf->address = (void *)(agp_offset + offset); - buf->next = NULL; + buf->next = NULL; buf->waiting = 0; buf->pending = 0; - init_waitqueue_head( &buf->dma_wait ); - buf->filp = NULL; + init_waitqueue_head(&buf->dma_wait); + buf->filp = NULL; buf->dev_priv_size = dev->fn_tbl->dev_priv_size; - buf->dev_private = drm_alloc( buf->dev_priv_size, - DRM_MEM_BUFS ); - if(!buf->dev_private) { + buf->dev_private = drm_alloc(buf->dev_priv_size, DRM_MEM_BUFS); + if (!buf->dev_private) { /* Set count correctly so we free the proper amount. */ entry->buf_count = count; - drm_cleanup_buf_error(dev,entry); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( buf->dev_private, 0, buf->dev_priv_size ); + memset(buf->dev_private, 0, buf->dev_priv_size); - DRM_DEBUG( "buffer %d @ %p\n", - entry->buf_count, buf->address ); + DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address); offset += alignment; entry->buf_count++; byte_count += PAGE_SIZE << page_order; } - DRM_DEBUG( "byte_count: %d\n", byte_count ); + DRM_DEBUG("byte_count: %d\n", byte_count); - temp_buflist = drm_realloc( dma->buflist, - dma->buf_count * sizeof(*dma->buflist), - (dma->buf_count + entry->buf_count) - * sizeof(*dma->buflist), - DRM_MEM_BUFS ); - if(!temp_buflist) { + temp_buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), DRM_MEM_BUFS); + if (!temp_buflist) { /* Free the entry because it isn't valid */ - drm_cleanup_buf_error(dev,entry); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } dma->buflist = temp_buflist; - for ( i = 0 ; i < entry->buf_count ; i++ ) { + for (i = 0; i < entry->buf_count; i++) { dma->buflist[i + dma->buf_count] = &entry->buflist[i]; } dma->buf_count += entry->buf_count; dma->byte_count += byte_count; - DRM_DEBUG( "dma->buf_count : %d\n", dma->buf_count ); - DRM_DEBUG( "entry->buf_count : %d\n", entry->buf_count ); + DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count); + DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count); - up( &dev->struct_sem ); + up(&dev->struct_sem); request.count = entry->buf_count; request.size = size; - if ( copy_to_user( argp, &request, sizeof(request) ) ) + if (copy_to_user(argp, &request, sizeof(request))) return -EFAULT; dma->flags = _DRM_DMA_USE_AGP; - atomic_dec( &dev->buf_alloc ); + atomic_dec(&dev->buf_alloc); return 0; } -#endif /* __OS_HAS_AGP */ +#endif /* __OS_HAS_AGP */ -int drm_addbufs_pci( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_addbufs_pci(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; + drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_device_dma_t *dma = dev->dma; drm_buf_desc_t request; @@ -596,183 +599,179 @@ int drm_addbufs_pci( struct inode *inode, struct file *filp, drm_buf_t **temp_buflist; drm_buf_desc_t __user *argp = (void __user *)arg; - if (!drm_core_check_feature(dev, DRIVER_PCI_DMA)) return -EINVAL; + if (!drm_core_check_feature(dev, DRIVER_PCI_DMA)) + return -EINVAL; - if ( !dma ) return -EINVAL; + if (!dma) + return -EINVAL; - if ( copy_from_user( &request, argp, sizeof(request) ) ) + if (copy_from_user(&request, argp, sizeof(request))) return -EFAULT; count = request.count; - order = get_order( request.size ); + order = get_order(request.size); size = 1 << order; - DRM_DEBUG( "count=%d, size=%d (%d), order=%d, queue_count=%d\n", - request.count, request.size, size, - order, dev->queue_count ); + DRM_DEBUG("count=%d, size=%d (%d), order=%d, queue_count=%d\n", + request.count, request.size, size, order, dev->queue_count); - if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; - if ( dev->queue_count ) return -EBUSY; /* Not while in use */ + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) + return -EINVAL; + if (dev->queue_count) + return -EBUSY; /* Not while in use */ alignment = (request.flags & _DRM_PAGE_ALIGN) - ? PAGE_ALIGN(size) : size; + ? PAGE_ALIGN(size) : size; page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; total = PAGE_SIZE << page_order; - spin_lock( &dev->count_lock ); - if ( dev->buf_use ) { - spin_unlock( &dev->count_lock ); + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); return -EBUSY; } - atomic_inc( &dev->buf_alloc ); - spin_unlock( &dev->count_lock ); + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); - down( &dev->struct_sem ); + down(&dev->struct_sem); entry = &dma->bufs[order]; - if ( entry->buf_count ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; /* May only call once for each order */ } if (count < 0 || count > 4096) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -EINVAL; } - entry->buflist = drm_alloc( count * sizeof(*entry->buflist), - DRM_MEM_BUFS ); - if ( !entry->buflist ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); - - entry->seglist = drm_alloc( count * sizeof(*entry->seglist), - DRM_MEM_SEGS ); - if ( !entry->seglist ) { - drm_free( entry->buflist, - count * sizeof(*entry->buflist), - DRM_MEM_BUFS ); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); + + entry->seglist = drm_alloc(count * sizeof(*entry->seglist), + DRM_MEM_SEGS); + if (!entry->seglist) { + drm_free(entry->buflist, + count * sizeof(*entry->buflist), DRM_MEM_BUFS); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( entry->seglist, 0, count * sizeof(*entry->seglist) ); + memset(entry->seglist, 0, count * sizeof(*entry->seglist)); /* Keep the original pagelist until we know all the allocations * have succeeded */ - temp_pagelist = drm_alloc( (dma->page_count + (count << page_order)) - * sizeof(*dma->pagelist), - DRM_MEM_PAGES ); + temp_pagelist = drm_alloc((dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), DRM_MEM_PAGES); if (!temp_pagelist) { - drm_free( entry->buflist, - count * sizeof(*entry->buflist), - DRM_MEM_BUFS ); - drm_free( entry->seglist, - count * sizeof(*entry->seglist), - DRM_MEM_SEGS ); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_free(entry->buflist, + count * sizeof(*entry->buflist), DRM_MEM_BUFS); + drm_free(entry->seglist, + count * sizeof(*entry->seglist), DRM_MEM_SEGS); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } memcpy(temp_pagelist, - dma->pagelist, - dma->page_count * sizeof(*dma->pagelist)); - DRM_DEBUG( "pagelist: %d entries\n", - dma->page_count + (count << page_order) ); + dma->pagelist, dma->page_count * sizeof(*dma->pagelist)); + DRM_DEBUG("pagelist: %d entries\n", + dma->page_count + (count << page_order)); - entry->buf_size = size; + entry->buf_size = size; entry->page_order = page_order; byte_count = 0; page_count = 0; - while ( entry->buf_count < count ) { - page = drm_alloc_pages( page_order, DRM_MEM_DMA ); - if ( !page ) { + while (entry->buf_count < count) { + page = drm_alloc_pages(page_order, DRM_MEM_DMA); + if (!page) { /* Set count correctly so we free the proper amount. */ entry->buf_count = count; entry->seg_count = count; - drm_cleanup_buf_error(dev,entry); - drm_free( temp_pagelist, - (dma->page_count + (count << page_order)) - * sizeof(*dma->pagelist), - DRM_MEM_PAGES ); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + drm_free(temp_pagelist, + (dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), DRM_MEM_PAGES); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } entry->seglist[entry->seg_count++] = page; - for ( i = 0 ; i < (1 << page_order) ; i++ ) { - DRM_DEBUG( "page %d @ 0x%08lx\n", - dma->page_count + page_count, - page + PAGE_SIZE * i ); + for (i = 0; i < (1 << page_order); i++) { + DRM_DEBUG("page %d @ 0x%08lx\n", + dma->page_count + page_count, + page + PAGE_SIZE * i); temp_pagelist[dma->page_count + page_count++] - = page + PAGE_SIZE * i; + = page + PAGE_SIZE * i; } - for ( offset = 0 ; - offset + size <= total && entry->buf_count < count ; - offset += alignment, ++entry->buf_count ) { - buf = &entry->buflist[entry->buf_count]; - buf->idx = dma->buf_count + entry->buf_count; - buf->total = alignment; - buf->order = order; - buf->used = 0; - buf->offset = (dma->byte_count + byte_count + offset); + for (offset = 0; + offset + size <= total && entry->buf_count < count; + offset += alignment, ++entry->buf_count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + buf->offset = (dma->byte_count + byte_count + offset); buf->address = (void *)(page + offset); buf->bus_address = virt_to_bus(buf->address); - buf->next = NULL; + buf->next = NULL; buf->waiting = 0; buf->pending = 0; - init_waitqueue_head( &buf->dma_wait ); - buf->filp = NULL; + init_waitqueue_head(&buf->dma_wait); + buf->filp = NULL; buf->dev_priv_size = dev->fn_tbl->dev_priv_size; - buf->dev_private = drm_alloc( dev->fn_tbl->dev_priv_size, - DRM_MEM_BUFS ); - if(!buf->dev_private) { + buf->dev_private = drm_alloc(dev->fn_tbl->dev_priv_size, + DRM_MEM_BUFS); + if (!buf->dev_private) { /* Set count correctly so we free the proper amount. */ entry->buf_count = count; entry->seg_count = count; - drm_cleanup_buf_error(dev,entry); - drm_free( temp_pagelist, - (dma->page_count + (count << page_order)) - * sizeof(*dma->pagelist), - DRM_MEM_PAGES ); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + drm_free(temp_pagelist, + (dma->page_count + + (count << page_order)) + * sizeof(*dma->pagelist), + DRM_MEM_PAGES); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( buf->dev_private, 0, buf->dev_priv_size ); + memset(buf->dev_private, 0, buf->dev_priv_size); - DRM_DEBUG( "buffer %d @ %p\n", - entry->buf_count, buf->address ); + DRM_DEBUG("buffer %d @ %p\n", + entry->buf_count, buf->address); } byte_count += PAGE_SIZE << page_order; } - temp_buflist = drm_realloc( dma->buflist, - dma->buf_count * sizeof(*dma->buflist), - (dma->buf_count + entry->buf_count) - * sizeof(*dma->buflist), - DRM_MEM_BUFS ); + temp_buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), DRM_MEM_BUFS); if (!temp_buflist) { /* Free the entry because it isn't valid */ - drm_cleanup_buf_error(dev,entry); - drm_free( temp_pagelist, - (dma->page_count + (count << page_order)) - * sizeof(*dma->pagelist), - DRM_MEM_PAGES ); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + drm_free(temp_pagelist, + (dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), DRM_MEM_PAGES); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } dma->buflist = temp_buflist; - for ( i = 0 ; i < entry->buf_count ; i++ ) { + for (i = 0; i < entry->buf_count; i++) { dma->buflist[i + dma->buf_count] = &entry->buflist[i]; } @@ -781,8 +780,8 @@ int drm_addbufs_pci( struct inode *inode, struct file *filp, */ if (dma->page_count) { drm_free(dma->pagelist, - dma->page_count * sizeof(*dma->pagelist), - DRM_MEM_PAGES); + dma->page_count * sizeof(*dma->pagelist), + DRM_MEM_PAGES); } dma->pagelist = temp_pagelist; @@ -791,21 +790,21 @@ int drm_addbufs_pci( struct inode *inode, struct file *filp, dma->page_count += entry->seg_count << page_order; dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order); - up( &dev->struct_sem ); + up(&dev->struct_sem); request.count = entry->buf_count; request.size = size; - if ( copy_to_user( argp, &request, sizeof(request) ) ) + if (copy_to_user(argp, &request, sizeof(request))) return -EFAULT; - atomic_dec( &dev->buf_alloc ); + atomic_dec(&dev->buf_alloc); return 0; } -int drm_addbufs_sg( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_addbufs_sg(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -826,147 +825,149 @@ int drm_addbufs_sg( struct inode *inode, struct file *filp, int i; drm_buf_t **temp_buflist; - if (!drm_core_check_feature(dev, DRIVER_SG)) return -EINVAL; - - if ( !dma ) return -EINVAL; + if (!drm_core_check_feature(dev, DRIVER_SG)) + return -EINVAL; - if ( copy_from_user( &request, argp, sizeof(request) ) ) + if (!dma) + return -EINVAL; + + if (copy_from_user(&request, argp, sizeof(request))) return -EFAULT; count = request.count; - order = get_order( request.size ); + order = get_order(request.size); size = 1 << order; - alignment = (request.flags & _DRM_PAGE_ALIGN) - ? PAGE_ALIGN(size) : size; + alignment = (request.flags & _DRM_PAGE_ALIGN) + ? PAGE_ALIGN(size) : size; page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; total = PAGE_SIZE << page_order; byte_count = 0; agp_offset = request.agp_start; - DRM_DEBUG( "count: %d\n", count ); - DRM_DEBUG( "order: %d\n", order ); - DRM_DEBUG( "size: %d\n", size ); - DRM_DEBUG( "agp_offset: %lu\n", agp_offset ); - DRM_DEBUG( "alignment: %d\n", alignment ); - DRM_DEBUG( "page_order: %d\n", page_order ); - DRM_DEBUG( "total: %d\n", total ); + DRM_DEBUG("count: %d\n", count); + DRM_DEBUG("order: %d\n", order); + DRM_DEBUG("size: %d\n", size); + DRM_DEBUG("agp_offset: %lu\n", agp_offset); + DRM_DEBUG("alignment: %d\n", alignment); + DRM_DEBUG("page_order: %d\n", page_order); + DRM_DEBUG("total: %d\n", total); - if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; - if ( dev->queue_count ) return -EBUSY; /* Not while in use */ + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) + return -EINVAL; + if (dev->queue_count) + return -EBUSY; /* Not while in use */ - spin_lock( &dev->count_lock ); - if ( dev->buf_use ) { - spin_unlock( &dev->count_lock ); + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); return -EBUSY; } - atomic_inc( &dev->buf_alloc ); - spin_unlock( &dev->count_lock ); + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); - down( &dev->struct_sem ); + down(&dev->struct_sem); entry = &dma->bufs[order]; - if ( entry->buf_count ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); - return -ENOMEM; /* May only call once for each order */ + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; /* May only call once for each order */ } if (count < 0 || count > 4096) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -EINVAL; } - entry->buflist = drm_alloc( count * sizeof(*entry->buflist), - DRM_MEM_BUFS ); - if ( !entry->buflist ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); entry->buf_size = size; entry->page_order = page_order; offset = 0; - while ( entry->buf_count < count ) { - buf = &entry->buflist[entry->buf_count]; - buf->idx = dma->buf_count + entry->buf_count; - buf->total = alignment; - buf->order = order; - buf->used = 0; + while (entry->buf_count < count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; - buf->offset = (dma->byte_count + offset); + buf->offset = (dma->byte_count + offset); buf->bus_address = agp_offset + offset; buf->address = (void *)(agp_offset + offset + dev->sg->handle); - buf->next = NULL; + buf->next = NULL; buf->waiting = 0; buf->pending = 0; - init_waitqueue_head( &buf->dma_wait ); - buf->filp = NULL; + init_waitqueue_head(&buf->dma_wait); + buf->filp = NULL; buf->dev_priv_size = dev->fn_tbl->dev_priv_size; - buf->dev_private = drm_alloc( dev->fn_tbl->dev_priv_size, - DRM_MEM_BUFS ); - if(!buf->dev_private) { + buf->dev_private = drm_alloc(dev->fn_tbl->dev_priv_size, + DRM_MEM_BUFS); + if (!buf->dev_private) { /* Set count correctly so we free the proper amount. */ entry->buf_count = count; - drm_cleanup_buf_error(dev,entry); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( buf->dev_private, 0, buf->dev_priv_size ); + memset(buf->dev_private, 0, buf->dev_priv_size); - DRM_DEBUG( "buffer %d @ %p\n", - entry->buf_count, buf->address ); + DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address); offset += alignment; entry->buf_count++; byte_count += PAGE_SIZE << page_order; } - DRM_DEBUG( "byte_count: %d\n", byte_count ); + DRM_DEBUG("byte_count: %d\n", byte_count); - temp_buflist = drm_realloc( dma->buflist, - dma->buf_count * sizeof(*dma->buflist), - (dma->buf_count + entry->buf_count) - * sizeof(*dma->buflist), - DRM_MEM_BUFS ); - if(!temp_buflist) { + temp_buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), DRM_MEM_BUFS); + if (!temp_buflist) { /* Free the entry because it isn't valid */ - drm_cleanup_buf_error(dev,entry); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } dma->buflist = temp_buflist; - for ( i = 0 ; i < entry->buf_count ; i++ ) { + for (i = 0; i < entry->buf_count; i++) { dma->buflist[i + dma->buf_count] = &entry->buflist[i]; } dma->buf_count += entry->buf_count; dma->byte_count += byte_count; - DRM_DEBUG( "dma->buf_count : %d\n", dma->buf_count ); - DRM_DEBUG( "entry->buf_count : %d\n", entry->buf_count ); + DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count); + DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count); - up( &dev->struct_sem ); + up(&dev->struct_sem); request.count = entry->buf_count; request.size = size; - if ( copy_to_user( argp, &request, sizeof(request) ) ) + if (copy_to_user(argp, &request, sizeof(request))) return -EFAULT; dma->flags = _DRM_DMA_USE_SG; - atomic_dec( &dev->buf_alloc ); + atomic_dec(&dev->buf_alloc); return 0; } @@ -984,32 +985,31 @@ int drm_addbufs_sg( struct inode *inode, struct file *filp, * addbufs_sg() or addbufs_pci() for AGP, scatter-gather or consistent * PCI memory respectively. */ -int drm_addbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_addbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_buf_desc_t request; drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; - + if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) return -EINVAL; - if ( copy_from_user( &request, (drm_buf_desc_t __user *)arg, - sizeof(request) ) ) + if (copy_from_user(&request, (drm_buf_desc_t __user *) arg, + sizeof(request))) return -EFAULT; #if __OS_HAS_AGP - if ( request.flags & _DRM_AGP_BUFFER ) - return drm_addbufs_agp( inode, filp, cmd, arg ); + if (request.flags & _DRM_AGP_BUFFER) + return drm_addbufs_agp(inode, filp, cmd, arg); else #endif - if ( request.flags & _DRM_SG_BUFFER ) - return drm_addbufs_sg( inode, filp, cmd, arg ); + if (request.flags & _DRM_SG_BUFFER) + return drm_addbufs_sg(inode, filp, cmd, arg); else - return drm_addbufs_pci( inode, filp, cmd, arg ); + return drm_addbufs_pci(inode, filp, cmd, arg); } - /** * Get information about the buffer mappings. * @@ -1027,8 +1027,8 @@ int drm_addbufs( struct inode *inode, struct file *filp, * lock, preventing of allocating more buffers after this call. Information * about each requested buffer is then copied into user space. */ -int drm_infobufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_infobufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -1041,58 +1041,61 @@ int drm_infobufs( struct inode *inode, struct file *filp, if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) return -EINVAL; - if ( !dma ) return -EINVAL; + if (!dma) + return -EINVAL; - spin_lock( &dev->count_lock ); - if ( atomic_read( &dev->buf_alloc ) ) { - spin_unlock( &dev->count_lock ); + spin_lock(&dev->count_lock); + if (atomic_read(&dev->buf_alloc)) { + spin_unlock(&dev->count_lock); return -EBUSY; } ++dev->buf_use; /* Can't allocate more after this call */ - spin_unlock( &dev->count_lock ); + spin_unlock(&dev->count_lock); - if ( copy_from_user( &request, argp, sizeof(request) ) ) + if (copy_from_user(&request, argp, sizeof(request))) return -EFAULT; - for ( i = 0, count = 0 ; i < DRM_MAX_ORDER + 1 ; i++ ) { - if ( dma->bufs[i].buf_count ) ++count; + for (i = 0, count = 0; i < DRM_MAX_ORDER + 1; i++) { + if (dma->bufs[i].buf_count) + ++count; } - DRM_DEBUG( "count = %d\n", count ); + DRM_DEBUG("count = %d\n", count); - if ( request.count >= count ) { - for ( i = 0, count = 0 ; i < DRM_MAX_ORDER + 1 ; i++ ) { - if ( dma->bufs[i].buf_count ) { - drm_buf_desc_t __user *to = &request.list[count]; + if (request.count >= count) { + for (i = 0, count = 0; i < DRM_MAX_ORDER + 1; i++) { + if (dma->bufs[i].buf_count) { + drm_buf_desc_t __user *to = + &request.list[count]; drm_buf_entry_t *from = &dma->bufs[i]; drm_freelist_t *list = &dma->bufs[i].freelist; - if ( copy_to_user( &to->count, - &from->buf_count, - sizeof(from->buf_count) ) || - copy_to_user( &to->size, - &from->buf_size, - sizeof(from->buf_size) ) || - copy_to_user( &to->low_mark, - &list->low_mark, - sizeof(list->low_mark) ) || - copy_to_user( &to->high_mark, - &list->high_mark, - sizeof(list->high_mark) ) ) + if (copy_to_user(&to->count, + &from->buf_count, + sizeof(from->buf_count)) || + copy_to_user(&to->size, + &from->buf_size, + sizeof(from->buf_size)) || + copy_to_user(&to->low_mark, + &list->low_mark, + sizeof(list->low_mark)) || + copy_to_user(&to->high_mark, + &list->high_mark, + sizeof(list->high_mark))) return -EFAULT; - DRM_DEBUG( "%d %d %d %d %d\n", - i, - dma->bufs[i].buf_count, - dma->bufs[i].buf_size, - dma->bufs[i].freelist.low_mark, - dma->bufs[i].freelist.high_mark ); + DRM_DEBUG("%d %d %d %d %d\n", + i, + dma->bufs[i].buf_count, + dma->bufs[i].buf_size, + dma->bufs[i].freelist.low_mark, + dma->bufs[i].freelist.high_mark); ++count; } } } request.count = count; - if ( copy_to_user( argp, &request, sizeof(request) ) ) + if (copy_to_user(argp, &request, sizeof(request))) return -EFAULT; return 0; @@ -1112,8 +1115,8 @@ int drm_infobufs( struct inode *inode, struct file *filp, * * \note This ioctl is deprecated and mostly never used. */ -int drm_markbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_markbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -1125,44 +1128,45 @@ int drm_markbufs( struct inode *inode, struct file *filp, if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) return -EINVAL; - if ( !dma ) return -EINVAL; + if (!dma) + return -EINVAL; - if ( copy_from_user( &request, - (drm_buf_desc_t __user *)arg, - sizeof(request) ) ) + if (copy_from_user(&request, + (drm_buf_desc_t __user *) arg, sizeof(request))) return -EFAULT; - DRM_DEBUG( "%d, %d, %d\n", - request.size, request.low_mark, request.high_mark ); - order = get_order( request.size ); - if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; + DRM_DEBUG("%d, %d, %d\n", + request.size, request.low_mark, request.high_mark); + order = get_order(request.size); + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) + return -EINVAL; entry = &dma->bufs[order]; - if ( request.low_mark < 0 || request.low_mark > entry->buf_count ) + if (request.low_mark < 0 || request.low_mark > entry->buf_count) return -EINVAL; - if ( request.high_mark < 0 || request.high_mark > entry->buf_count ) + if (request.high_mark < 0 || request.high_mark > entry->buf_count) return -EINVAL; - entry->freelist.low_mark = request.low_mark; + entry->freelist.low_mark = request.low_mark; entry->freelist.high_mark = request.high_mark; return 0; } /** - * Unreserve the buffers in list, previously reserved using drmDMA. + * Unreserve the buffers in list, previously reserved using drmDMA. * * \param inode device inode. * \param filp file pointer. * \param cmd command. * \param arg pointer to a drm_buf_free structure. * \return zero on success or a negative number on failure. - * + * * Calls free_buffer() for each used buffer. * This function is primarily used for debugging. */ -int drm_freebufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_freebufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -1175,31 +1179,29 @@ int drm_freebufs( struct inode *inode, struct file *filp, if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) return -EINVAL; - if ( !dma ) return -EINVAL; + if (!dma) + return -EINVAL; - if ( copy_from_user( &request, - (drm_buf_free_t __user *)arg, - sizeof(request) ) ) + if (copy_from_user(&request, + (drm_buf_free_t __user *) arg, sizeof(request))) return -EFAULT; - DRM_DEBUG( "%d\n", request.count ); - for ( i = 0 ; i < request.count ; i++ ) { - if ( copy_from_user( &idx, - &request.list[i], - sizeof(idx) ) ) + DRM_DEBUG("%d\n", request.count); + for (i = 0; i < request.count; i++) { + if (copy_from_user(&idx, &request.list[i], sizeof(idx))) return -EFAULT; - if ( idx < 0 || idx >= dma->buf_count ) { - DRM_ERROR( "Index %d (of %d max)\n", - idx, dma->buf_count - 1 ); + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("Index %d (of %d max)\n", + idx, dma->buf_count - 1); return -EINVAL; } buf = dma->buflist[idx]; - if ( buf->filp != filp ) { - DRM_ERROR( "Process %d freeing buffer not owned\n", - current->pid ); + if (buf->filp != filp) { + DRM_ERROR("Process %d freeing buffer not owned\n", + current->pid); return -EINVAL; } - drm_free_buffer( dev, buf ); + drm_free_buffer(dev, buf); } return 0; @@ -1218,8 +1220,8 @@ int drm_freebufs( struct inode *inode, struct file *filp, * about each buffer into user space. The PCI buffers are already mapped on the * addbufs_pci() call. */ -int drm_mapbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_mapbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -1235,100 +1237,98 @@ int drm_mapbufs( struct inode *inode, struct file *filp, if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) return -EINVAL; - if ( !dma ) return -EINVAL; + if (!dma) + return -EINVAL; - spin_lock( &dev->count_lock ); - if ( atomic_read( &dev->buf_alloc ) ) { - spin_unlock( &dev->count_lock ); + spin_lock(&dev->count_lock); + if (atomic_read(&dev->buf_alloc)) { + spin_unlock(&dev->count_lock); return -EBUSY; } dev->buf_use++; /* Can't allocate more after this call */ - spin_unlock( &dev->count_lock ); + spin_unlock(&dev->count_lock); - if ( copy_from_user( &request, argp, sizeof(request) ) ) + if (copy_from_user(&request, argp, sizeof(request))) return -EFAULT; - if ( request.count >= dma->buf_count ) { - if ((drm_core_has_AGP(dev) && (dma->flags & _DRM_DMA_USE_AGP)) || - (drm_core_check_feature(dev, DRIVER_SG) && (dma->flags & _DRM_DMA_USE_SG))) { + if (request.count >= dma->buf_count) { + if ((drm_core_has_AGP(dev) && (dma->flags & _DRM_DMA_USE_AGP)) + || (drm_core_check_feature(dev, DRIVER_SG) + && (dma->flags & _DRM_DMA_USE_SG))) { drm_map_t *map = dev->agp_buffer_map; - if ( !map ) { + if (!map) { retcode = -EINVAL; goto done; } - #if LINUX_VERSION_CODE <= 0x020402 - down( ¤t->mm->mmap_sem ); + down(¤t->mm->mmap_sem); #else - down_write( ¤t->mm->mmap_sem ); + down_write(¤t->mm->mmap_sem); #endif - virtual = do_mmap( filp, 0, map->size, - PROT_READ | PROT_WRITE, - MAP_SHARED, - (unsigned long)map->offset ); + virtual = do_mmap(filp, 0, map->size, + PROT_READ | PROT_WRITE, + MAP_SHARED, + (unsigned long)map->offset); #if LINUX_VERSION_CODE <= 0x020402 - up( ¤t->mm->mmap_sem ); + up(¤t->mm->mmap_sem); #else - up_write( ¤t->mm->mmap_sem ); + up_write(¤t->mm->mmap_sem); #endif } else { #if LINUX_VERSION_CODE <= 0x020402 - down( ¤t->mm->mmap_sem ); + down(¤t->mm->mmap_sem); #else - down_write( ¤t->mm->mmap_sem ); + down_write(¤t->mm->mmap_sem); #endif - virtual = do_mmap( filp, 0, dma->byte_count, - PROT_READ | PROT_WRITE, - MAP_SHARED, 0 ); + virtual = do_mmap(filp, 0, dma->byte_count, + PROT_READ | PROT_WRITE, + MAP_SHARED, 0); #if LINUX_VERSION_CODE <= 0x020402 - up( ¤t->mm->mmap_sem ); + up(¤t->mm->mmap_sem); #else - up_write( ¤t->mm->mmap_sem ); + up_write(¤t->mm->mmap_sem); #endif } - if ( virtual > -1024UL ) { + if (virtual > -1024UL) { /* Real error */ retcode = (signed long)virtual; goto done; } request.virtual = (void __user *)virtual; - for ( i = 0 ; i < dma->buf_count ; i++ ) { - if ( copy_to_user( &request.list[i].idx, - &dma->buflist[i]->idx, - sizeof(request.list[0].idx) ) ) { + for (i = 0; i < dma->buf_count; i++) { + if (copy_to_user(&request.list[i].idx, + &dma->buflist[i]->idx, + sizeof(request.list[0].idx))) { retcode = -EFAULT; goto done; } - if ( copy_to_user( &request.list[i].total, - &dma->buflist[i]->total, - sizeof(request.list[0].total) ) ) { + if (copy_to_user(&request.list[i].total, + &dma->buflist[i]->total, + sizeof(request.list[0].total))) { retcode = -EFAULT; goto done; } - if ( copy_to_user( &request.list[i].used, - &zero, - sizeof(zero) ) ) { + if (copy_to_user(&request.list[i].used, + &zero, sizeof(zero))) { retcode = -EFAULT; goto done; } - address = virtual + dma->buflist[i]->offset; /* *** */ - if ( copy_to_user( &request.list[i].address, - &address, - sizeof(address) ) ) { + address = virtual + dma->buflist[i]->offset; /* *** */ + if (copy_to_user(&request.list[i].address, + &address, sizeof(address))) { retcode = -EFAULT; goto done; } } } - done: + done: request.count = dma->buf_count; - DRM_DEBUG( "%d buffers, retcode = %d\n", request.count, retcode ); + DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode); - if ( copy_to_user( argp, &request, sizeof(request) ) ) + if (copy_to_user(argp, &request, sizeof(request))) return -EFAULT; return retcode; } - diff --git a/linux-core/drm_compat.h b/linux-core/drm_compat.h index 2efa8306..b7fc56ef 100644 --- a/linux-core/drm_compat.h +++ b/linux-core/drm_compat.h @@ -1,7 +1,7 @@ /** - * \file drm_compat.h + * \file drm_compat.h * Backward compatability definitions for Direct Rendering Manager - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -39,7 +39,7 @@ #endif #ifndef MODULE_LICENSE -#define MODULE_LICENSE(x) +#define MODULE_LICENSE(x) #endif #ifndef preempt_disable @@ -47,7 +47,7 @@ #define preempt_enable() #endif -#ifndef pte_offset_map +#ifndef pte_offset_map #define pte_offset_map pte_offset #define pte_unmap(pte) #endif @@ -80,14 +80,14 @@ #endif #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19) -static inline struct page * vmalloc_to_page(void * vmalloc_addr) +static inline struct page *vmalloc_to_page(void *vmalloc_addr) { - unsigned long addr = (unsigned long) vmalloc_addr; + unsigned long addr = (unsigned long)vmalloc_addr; struct page *page = NULL; pgd_t *pgd = pgd_offset_k(addr); pmd_t *pmd; pte_t *ptep, pte; - + if (!pgd_none(*pgd)) { pmd = pmd_offset(pgd, addr); if (!pmd_none(*pmd)) { @@ -118,7 +118,7 @@ static inline struct page * vmalloc_to_page(void * vmalloc_addr) #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) static inline unsigned iminor(struct inode *inode) { - return MINOR(inode->i_rdev); + return MINOR(inode->i_rdev); } #define old_encode_dev(x) (x) @@ -130,21 +130,38 @@ struct device; #define pci_dev_put(x) do {} while (0) #define pci_get_subsys pci_find_subsys -static inline struct class_device *DRM(sysfs_device_add)(struct drm_sysfs_class *cs, dev_t dev, struct device *device, const char *fmt, ...){return NULL;} +static inline struct class_device *DRM(sysfs_device_add) (struct drm_sysfs_class + * cs, dev_t dev, + struct device * + device, + const char *fmt, + ...) { + return NULL; +} -static inline void DRM(sysfs_device_remove)(dev_t dev){} +static inline void DRM(sysfs_device_remove) (dev_t dev) { +} -static inline void DRM(sysfs_destroy)(struct drm_sysfs_class *cs){} +static inline void DRM(sysfs_destroy) (struct drm_sysfs_class * cs) { +} -static inline struct drm_sysfs_class *DRM(sysfs_create)(struct module *owner, char *name) { return NULL; } +static inline struct drm_sysfs_class *DRM(sysfs_create) (struct module * owner, + char *name) { + return NULL; +} #ifndef pci_pretty_name #define pci_pretty_name(x) x->name #endif struct drm_device; -static inline int radeon_create_i2c_busses(struct drm_device *dev){return 0;}; -static inline void radeon_delete_i2c_busses(struct drm_device *dev){}; +static inline int radeon_create_i2c_busses(struct drm_device *dev) +{ + return 0; +}; +static inline void radeon_delete_i2c_busses(struct drm_device *dev) +{ +}; #endif diff --git a/linux-core/drm_context.c b/linux-core/drm_context.c index cfa4a172..a6fec094 100644 --- a/linux-core/drm_context.c +++ b/linux-core/drm_context.c @@ -1,7 +1,7 @@ /** - * \file drm_context.h + * \file drm_context.h * IOCTLs for generic contexts - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -56,25 +56,26 @@ * in drm_device::context_sareas, while holding the drm_device::struct_sem * lock. */ -void drm_ctxbitmap_free( drm_device_t *dev, int ctx_handle ) +void drm_ctxbitmap_free(drm_device_t * dev, int ctx_handle) { - if ( ctx_handle < 0 ) goto failed; - if ( !dev->ctx_bitmap ) goto failed; + if (ctx_handle < 0) + goto failed; + if (!dev->ctx_bitmap) + goto failed; - if ( ctx_handle < DRM_MAX_CTXBITMAP ) { + if (ctx_handle < DRM_MAX_CTXBITMAP) { down(&dev->struct_sem); - clear_bit( ctx_handle, dev->ctx_bitmap ); + clear_bit(ctx_handle, dev->ctx_bitmap); dev->context_sareas[ctx_handle] = NULL; up(&dev->struct_sem); return; } -failed: - DRM_ERROR( "Attempt to free invalid context handle: %d\n", - ctx_handle ); - return; + failed: + DRM_ERROR("Attempt to free invalid context handle: %d\n", ctx_handle); + return; } -/** +/** * Context bitmap allocation. * * \param dev DRM device. @@ -84,29 +85,33 @@ failed: * drm_device::context_sareas to accommodate the new entry while holding the * drm_device::struct_sem lock. */ -int drm_ctxbitmap_next( drm_device_t *dev ) +int drm_ctxbitmap_next(drm_device_t * dev) { int bit; - if(!dev->ctx_bitmap) return -1; + if (!dev->ctx_bitmap) + return -1; down(&dev->struct_sem); - bit = find_first_zero_bit( dev->ctx_bitmap, DRM_MAX_CTXBITMAP ); - if ( bit < DRM_MAX_CTXBITMAP ) { - set_bit( bit, dev->ctx_bitmap ); - DRM_DEBUG( "drm_ctxbitmap_next bit : %d\n", bit ); - if((bit+1) > dev->max_context) { - dev->max_context = (bit+1); - if(dev->context_sareas) { + bit = find_first_zero_bit(dev->ctx_bitmap, DRM_MAX_CTXBITMAP); + if (bit < DRM_MAX_CTXBITMAP) { + set_bit(bit, dev->ctx_bitmap); + DRM_DEBUG("drm_ctxbitmap_next bit : %d\n", bit); + if ((bit + 1) > dev->max_context) { + dev->max_context = (bit + 1); + if (dev->context_sareas) { drm_map_t **ctx_sareas; ctx_sareas = drm_realloc(dev->context_sareas, - (dev->max_context - 1) * - sizeof(*dev->context_sareas), - dev->max_context * - sizeof(*dev->context_sareas), - DRM_MEM_MAPS); - if(!ctx_sareas) { + (dev->max_context - + 1) * + sizeof(*dev-> + context_sareas), + dev->max_context * + sizeof(*dev-> + context_sareas), + DRM_MEM_MAPS); + if (!ctx_sareas) { clear_bit(bit, dev->ctx_bitmap); up(&dev->struct_sem); return -1; @@ -115,11 +120,11 @@ int drm_ctxbitmap_next( drm_device_t *dev ) dev->context_sareas[bit] = NULL; } else { /* max_context == 1 at this point */ - dev->context_sareas = drm_alloc( - dev->max_context * - sizeof(*dev->context_sareas), - DRM_MEM_MAPS); - if(!dev->context_sareas) { + dev->context_sareas = + drm_alloc(dev->max_context * + sizeof(*dev->context_sareas), + DRM_MEM_MAPS); + if (!dev->context_sareas) { clear_bit(bit, dev->ctx_bitmap); up(&dev->struct_sem); return -1; @@ -142,26 +147,26 @@ int drm_ctxbitmap_next( drm_device_t *dev ) * Allocates and initialize drm_device::ctx_bitmap and drm_device::context_sareas, while holding * the drm_device::struct_sem lock. */ -int drm_ctxbitmap_init( drm_device_t *dev ) +int drm_ctxbitmap_init(drm_device_t * dev) { int i; - int temp; + int temp; down(&dev->struct_sem); - dev->ctx_bitmap = (unsigned long *) drm_alloc( PAGE_SIZE, - DRM_MEM_CTXBITMAP ); - if ( dev->ctx_bitmap == NULL ) { + dev->ctx_bitmap = (unsigned long *)drm_alloc(PAGE_SIZE, + DRM_MEM_CTXBITMAP); + if (dev->ctx_bitmap == NULL) { up(&dev->struct_sem); return -ENOMEM; } - memset( (void *)dev->ctx_bitmap, 0, PAGE_SIZE ); + memset((void *)dev->ctx_bitmap, 0, PAGE_SIZE); dev->context_sareas = NULL; dev->max_context = -1; up(&dev->struct_sem); - for ( i = 0 ; i < DRM_RESERVED_CONTEXTS ; i++ ) { - temp = drm_ctxbitmap_next( dev ); - DRM_DEBUG( "drm_ctxbitmap_init : %d\n", temp ); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + temp = drm_ctxbitmap_next(dev); + DRM_DEBUG("drm_ctxbitmap_init : %d\n", temp); } return 0; @@ -175,14 +180,14 @@ int drm_ctxbitmap_init( drm_device_t *dev ) * Frees drm_device::ctx_bitmap and drm_device::context_sareas, while holding * the drm_device::struct_sem lock. */ -void drm_ctxbitmap_cleanup( drm_device_t *dev ) +void drm_ctxbitmap_cleanup(drm_device_t * dev) { down(&dev->struct_sem); - if( dev->context_sareas ) drm_free( dev->context_sareas, - sizeof(*dev->context_sareas) * - dev->max_context, - DRM_MEM_MAPS ); - drm_free( (void *)dev->ctx_bitmap, PAGE_SIZE, DRM_MEM_CTXBITMAP ); + if (dev->context_sareas) + drm_free(dev->context_sareas, + sizeof(*dev->context_sareas) * + dev->max_context, DRM_MEM_MAPS); + drm_free((void *)dev->ctx_bitmap, PAGE_SIZE, DRM_MEM_CTXBITMAP); up(&dev->struct_sem); } @@ -194,7 +199,7 @@ void drm_ctxbitmap_cleanup( drm_device_t *dev ) /** * Get per-context SAREA. - * + * * \param inode device inode. * \param filp file pointer. * \param cmd command. @@ -205,10 +210,10 @@ void drm_ctxbitmap_cleanup( drm_device_t *dev ) * returns its handle. */ int drm_getsareactx(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_ctx_priv_map_t __user *argp = (void __user *)arg; drm_ctx_priv_map_t request; drm_map_t *map; @@ -217,7 +222,8 @@ int drm_getsareactx(struct inode *inode, struct file *filp, return -EFAULT; down(&dev->struct_sem); - if (dev->max_context < 0 || request.ctx_id >= (unsigned) dev->max_context) { + if (dev->max_context < 0 + || request.ctx_id >= (unsigned)dev->max_context) { up(&dev->struct_sem); return -EINVAL; } @@ -233,7 +239,7 @@ int drm_getsareactx(struct inode *inode, struct file *filp, /** * Set per-context SAREA. - * + * * \param inode device inode. * \param filp file pointer. * \param cmd command. @@ -244,37 +250,36 @@ int drm_getsareactx(struct inode *inode, struct file *filp, * drm_device::context_sareas with it. */ int drm_setsareactx(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_ctx_priv_map_t request; drm_map_t *map = NULL; drm_map_list_t *r_list = NULL; struct list_head *list; if (copy_from_user(&request, - (drm_ctx_priv_map_t __user *)arg, - sizeof(request))) + (drm_ctx_priv_map_t __user *) arg, sizeof(request))) return -EFAULT; down(&dev->struct_sem); list_for_each(list, &dev->maplist->head) { r_list = list_entry(list, drm_map_list_t, head); - if(r_list->map && - r_list->map->handle == request.handle) + if (r_list->map && r_list->map->handle == request.handle) goto found; } -bad: + bad: up(&dev->struct_sem); return -EINVAL; -found: + found: map = r_list->map; - if (!map) goto bad; + if (!map) + goto bad; if (dev->max_context < 0) goto bad; - if (request.ctx_id >= (unsigned) dev->max_context) + if (request.ctx_id >= (unsigned)dev->max_context) goto bad; dev->context_sareas[request.ctx_id] = map; up(&dev->struct_sem); @@ -297,22 +302,21 @@ found: * * Attempt to set drm_device::context_flag. */ -int drm_context_switch( drm_device_t *dev, int old, int new ) +int drm_context_switch(drm_device_t * dev, int old, int new) { - if ( test_and_set_bit( 0, &dev->context_flag ) ) { - DRM_ERROR( "Reentering -- FIXME\n" ); - return -EBUSY; - } - + if (test_and_set_bit(0, &dev->context_flag)) { + DRM_ERROR("Reentering -- FIXME\n"); + return -EBUSY; + } - DRM_DEBUG( "Context switch from %d to %d\n", old, new ); + DRM_DEBUG("Context switch from %d to %d\n", old, new); - if ( new == dev->last_context ) { - clear_bit( 0, &dev->context_flag ); - return 0; - } + if (new == dev->last_context) { + clear_bit(0, &dev->context_flag); + return 0; + } - return 0; + return 0; } /** @@ -326,22 +330,22 @@ int drm_context_switch( drm_device_t *dev, int old, int new ) * hardware lock is held, clears the drm_device::context_flag and wakes up * drm_device::context_wait. */ -int drm_context_switch_complete( drm_device_t *dev, int new ) +int drm_context_switch_complete(drm_device_t * dev, int new) { - dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ - dev->last_switch = jiffies; + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; - if ( !_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) ) { - DRM_ERROR( "Lock isn't held after context switch\n" ); - } + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Lock isn't held after context switch\n"); + } - /* If a context switch is ever initiated - when the kernel holds the lock, release - that lock here. */ - clear_bit( 0, &dev->context_flag ); - wake_up( &dev->context_wait ); + /* If a context switch is ever initiated + when the kernel holds the lock, release + that lock here. */ + clear_bit(0, &dev->context_flag); + wake_up(&dev->context_wait); - return 0; + return 0; } /** @@ -353,29 +357,28 @@ int drm_context_switch_complete( drm_device_t *dev, int new ) * \param arg user argument pointing to a drm_ctx_res structure. * \return zero on success or a negative number on failure. */ -int drm_resctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_ctx_res_t res; drm_ctx_t __user *argp = (void __user *)arg; drm_ctx_t ctx; int i; - if ( copy_from_user( &res, argp, sizeof(res) ) ) + if (copy_from_user(&res, argp, sizeof(res))) return -EFAULT; - if ( res.count >= DRM_RESERVED_CONTEXTS ) { - memset( &ctx, 0, sizeof(ctx) ); - for ( i = 0 ; i < DRM_RESERVED_CONTEXTS ; i++ ) { + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { ctx.handle = i; - if ( copy_to_user( &res.contexts[i], - &i, sizeof(i) ) ) + if (copy_to_user(&res.contexts[i], &i, sizeof(i))) return -EFAULT; } } res.count = DRM_RESERVED_CONTEXTS; - if ( copy_to_user( argp, &res, sizeof(res) ) ) + if (copy_to_user(argp, &res, sizeof(res))) return -EFAULT; return 0; } @@ -391,58 +394,57 @@ int drm_resctx( struct inode *inode, struct file *filp, * * Get a new handle for the context and copy to userspace. */ -int drm_addctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; - drm_ctx_list_t * ctx_entry; + drm_ctx_list_t *ctx_entry; drm_ctx_t __user *argp = (void __user *)arg; drm_ctx_t ctx; - if ( copy_from_user( &ctx, argp, sizeof(ctx) ) ) + if (copy_from_user(&ctx, argp, sizeof(ctx))) return -EFAULT; - ctx.handle = drm_ctxbitmap_next( dev ); - if ( ctx.handle == DRM_KERNEL_CONTEXT ) { - /* Skip kernel's context and get a new one. */ - ctx.handle = drm_ctxbitmap_next( dev ); + ctx.handle = drm_ctxbitmap_next(dev); + if (ctx.handle == DRM_KERNEL_CONTEXT) { + /* Skip kernel's context and get a new one. */ + ctx.handle = drm_ctxbitmap_next(dev); } - DRM_DEBUG( "%d\n", ctx.handle ); - if ( ctx.handle == -1 ) { - DRM_DEBUG( "Not enough free contexts.\n" ); - /* Should this return -EBUSY instead? */ + DRM_DEBUG("%d\n", ctx.handle); + if (ctx.handle == -1) { + DRM_DEBUG("Not enough free contexts.\n"); + /* Should this return -EBUSY instead? */ return -ENOMEM; } - if ( ctx.handle != DRM_KERNEL_CONTEXT ) - { + if (ctx.handle != DRM_KERNEL_CONTEXT) { if (dev->fn_tbl->context_ctor) dev->fn_tbl->context_ctor(dev, ctx.handle); } - ctx_entry = drm_alloc( sizeof(*ctx_entry), DRM_MEM_CTXLIST ); - if ( !ctx_entry ) { + ctx_entry = drm_alloc(sizeof(*ctx_entry), DRM_MEM_CTXLIST); + if (!ctx_entry) { DRM_DEBUG("out of memory\n"); return -ENOMEM; } - INIT_LIST_HEAD( &ctx_entry->head ); + INIT_LIST_HEAD(&ctx_entry->head); ctx_entry->handle = ctx.handle; ctx_entry->tag = priv; - down( &dev->ctxlist_sem ); - list_add( &ctx_entry->head, &dev->ctxlist->head ); + down(&dev->ctxlist_sem); + list_add(&ctx_entry->head, &dev->ctxlist->head); ++dev->ctx_count; - up( &dev->ctxlist_sem ); + up(&dev->ctxlist_sem); - if ( copy_to_user( argp, &ctx, sizeof(ctx) ) ) + if (copy_to_user(argp, &ctx, sizeof(ctx))) return -EFAULT; return 0; } -int drm_modctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { /* This does nothing */ return 0; @@ -457,19 +459,19 @@ int drm_modctx( struct inode *inode, struct file *filp, * \param arg user argument pointing to a drm_ctx structure. * \return zero on success or a negative number on failure. */ -int drm_getctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_ctx_t __user *argp = (void __user *)arg; drm_ctx_t ctx; - if ( copy_from_user( &ctx, argp, sizeof(ctx) ) ) + if (copy_from_user(&ctx, argp, sizeof(ctx))) return -EFAULT; /* This is 0, because we don't handle any context flags */ ctx.flags = 0; - if ( copy_to_user( argp, &ctx, sizeof(ctx) ) ) + if (copy_to_user(argp, &ctx, sizeof(ctx))) return -EFAULT; return 0; } @@ -485,18 +487,18 @@ int drm_getctx( struct inode *inode, struct file *filp, * * Calls context_switch(). */ -int drm_switchctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_ctx_t ctx; - if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; - DRM_DEBUG( "%d\n", ctx.handle ); - return drm_context_switch( dev, dev->last_context, ctx.handle ); + DRM_DEBUG("%d\n", ctx.handle); + return drm_context_switch(dev, dev->last_context, ctx.handle); } /** @@ -510,18 +512,18 @@ int drm_switchctx( struct inode *inode, struct file *filp, * * Calls context_switch_complete(). */ -int drm_newctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_ctx_t ctx; - if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; - DRM_DEBUG( "%d\n", ctx.handle ); - drm_context_switch_complete( dev, ctx.handle ); + DRM_DEBUG("%d\n", ctx.handle); + drm_context_switch_complete(dev, ctx.handle); return 0; } @@ -537,42 +539,41 @@ int drm_newctx( struct inode *inode, struct file *filp, * * If not the special kernel context, calls ctxbitmap_free() to free the specified context. */ -int drm_rmctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_ctx_t ctx; - if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; - DRM_DEBUG( "%d\n", ctx.handle ); - if ( ctx.handle == DRM_KERNEL_CONTEXT + 1 ) { + DRM_DEBUG("%d\n", ctx.handle); + if (ctx.handle == DRM_KERNEL_CONTEXT + 1) { priv->remove_auth_on_close = 1; } - if ( ctx.handle != DRM_KERNEL_CONTEXT ) { + if (ctx.handle != DRM_KERNEL_CONTEXT) { if (dev->fn_tbl->context_dtor) dev->fn_tbl->context_dtor(dev, ctx.handle); - drm_ctxbitmap_free( dev, ctx.handle ); + drm_ctxbitmap_free(dev, ctx.handle); } - down( &dev->ctxlist_sem ); - if ( !list_empty( &dev->ctxlist->head ) ) { + down(&dev->ctxlist_sem); + if (!list_empty(&dev->ctxlist->head)) { drm_ctx_list_t *pos, *n; - list_for_each_entry_safe( pos, n, &dev->ctxlist->head, head ) { - if ( pos->handle == ctx.handle ) { - list_del( &pos->head ); - drm_free( pos, sizeof(*pos), DRM_MEM_CTXLIST ); + list_for_each_entry_safe(pos, n, &dev->ctxlist->head, head) { + if (pos->handle == ctx.handle) { + list_del(&pos->head); + drm_free(pos, sizeof(*pos), DRM_MEM_CTXLIST); --dev->ctx_count; } } } - up( &dev->ctxlist_sem ); + up(&dev->ctxlist_sem); return 0; } /*@}*/ - diff --git a/linux-core/drm_core.h b/linux-core/drm_core.h index cfe62191..33b14cc2 100644 --- a/linux-core/drm_core.h +++ b/linux-core/drm_core.h @@ -35,4 +35,3 @@ #define DRIVER_MAJOR 1 #define DRIVER_MINOR 0 #define DRIVER_PATCHLEVEL 0 - diff --git a/linux-core/drm_dma.c b/linux-core/drm_dma.c index c7a5448a..66886309 100644 --- a/linux-core/drm_dma.c +++ b/linux-core/drm_dma.c @@ -1,5 +1,5 @@ /** - * \file drm_dma.h + * \file drm_dma.h * DMA IOCTL and function support * * \author Rickard E. (Rik) Faith @@ -37,23 +37,23 @@ /** * Initialize the DMA data. - * + * * \param dev DRM device. * \return zero on success or a negative value on failure. * * Allocate and initialize a drm_device_dma structure. */ -int drm_dma_setup( drm_device_t *dev ) +int drm_dma_setup(drm_device_t * dev) { int i; - dev->dma = drm_alloc( sizeof(*dev->dma), DRM_MEM_DRIVER ); - if ( !dev->dma ) + dev->dma = drm_alloc(sizeof(*dev->dma), DRM_MEM_DRIVER); + if (!dev->dma) return -ENOMEM; - memset( dev->dma, 0, sizeof(*dev->dma) ); + memset(dev->dma, 0, sizeof(*dev->dma)); - for ( i = 0 ; i <= DRM_MAX_ORDER ; i++ ) + for (i = 0; i <= DRM_MAX_ORDER; i++) memset(&dev->dma->bufs[i], 0, sizeof(dev->dma->bufs[0])); return 0; @@ -67,14 +67,15 @@ int drm_dma_setup( drm_device_t *dev ) * Free all pages associated with DMA buffers, the buffers and pages lists, and * finally the the drm_device::dma structure itself. */ -void drm_dma_takedown(drm_device_t *dev) +void drm_dma_takedown(drm_device_t * dev) { - drm_device_dma_t *dma = dev->dma; - int i, j; + drm_device_dma_t *dma = dev->dma; + int i, j; - if (!dma) return; + if (!dma) + return; - /* Clear dma buffers */ + /* Clear dma buffers */ for (i = 0; i <= DRM_MAX_ORDER; i++) { if (dma->bufs[i].seg_count) { DRM_DEBUG("order %d: buf_count = %d," @@ -85,64 +86,63 @@ void drm_dma_takedown(drm_device_t *dev) for (j = 0; j < dma->bufs[i].seg_count; j++) { if (dma->bufs[i].seglist[j]) { drm_free_pages(dma->bufs[i].seglist[j], - dma->bufs[i].page_order, - DRM_MEM_DMA); + dma->bufs[i].page_order, + DRM_MEM_DMA); } } drm_free(dma->bufs[i].seglist, - dma->bufs[i].seg_count - * sizeof(*dma->bufs[0].seglist), - DRM_MEM_SEGS); + dma->bufs[i].seg_count + * sizeof(*dma->bufs[0].seglist), DRM_MEM_SEGS); } - if (dma->bufs[i].buf_count) { - for (j = 0; j < dma->bufs[i].buf_count; j++) { + if (dma->bufs[i].buf_count) { + for (j = 0; j < dma->bufs[i].buf_count; j++) { if (dma->bufs[i].buflist[j].dev_private) { - drm_free(dma->bufs[i].buflist[j].dev_private, - dma->bufs[i].buflist[j].dev_priv_size, - DRM_MEM_BUFS); + drm_free(dma->bufs[i].buflist[j]. + dev_private, + dma->bufs[i].buflist[j]. + dev_priv_size, DRM_MEM_BUFS); } } - drm_free(dma->bufs[i].buflist, - dma->bufs[i].buf_count * - sizeof(*dma->bufs[0].buflist), - DRM_MEM_BUFS); + drm_free(dma->bufs[i].buflist, + dma->bufs[i].buf_count * + sizeof(*dma->bufs[0].buflist), DRM_MEM_BUFS); } } if (dma->buflist) { drm_free(dma->buflist, - dma->buf_count * sizeof(*dma->buflist), - DRM_MEM_BUFS); + dma->buf_count * sizeof(*dma->buflist), DRM_MEM_BUFS); } if (dma->pagelist) { drm_free(dma->pagelist, - dma->page_count * sizeof(*dma->pagelist), - DRM_MEM_PAGES); + dma->page_count * sizeof(*dma->pagelist), + DRM_MEM_PAGES); } drm_free(dev->dma, sizeof(*dev->dma), DRM_MEM_DRIVER); dev->dma = NULL; } - /** * Free a buffer. * * \param dev DRM device. * \param buf buffer to free. - * + * * Resets the fields of \p buf. */ -void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf) +void drm_free_buffer(drm_device_t * dev, drm_buf_t * buf) { - if (!buf) return; + if (!buf) + return; - buf->waiting = 0; - buf->pending = 0; - buf->filp = NULL; - buf->used = 0; + buf->waiting = 0; + buf->pending = 0; + buf->filp = NULL; + buf->used = 0; - if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) && waitqueue_active(&buf->dma_wait)) { + if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) + && waitqueue_active(&buf->dma_wait)) { wake_up_interruptible(&buf->dma_wait); } } @@ -154,14 +154,15 @@ void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf) * * Frees each buffer associated with \p filp not already on the hardware. */ -void drm_core_reclaim_buffers( struct file *filp ) +void drm_core_reclaim_buffers(struct file *filp) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_device_dma_t *dma = dev->dma; - int i; + int i; - if (!dma) return; + if (!dma) + return; for (i = 0; i < dma->buf_count; i++) { if (dma->buflist[i]->filp == filp) { switch (dma->buflist[i]->list) { @@ -179,4 +180,3 @@ void drm_core_reclaim_buffers( struct file *filp ) } } EXPORT_SYMBOL(drm_core_reclaim_buffers); - diff --git a/linux-core/drm_drawable.c b/linux-core/drm_drawable.c index e8e8e42b..c9b867cd 100644 --- a/linux-core/drm_drawable.c +++ b/linux-core/drm_drawable.c @@ -1,5 +1,5 @@ /** - * \file drm_drawable.h + * \file drm_drawable.h * IOCTLs for drawables * * \author Rickard E. (Rik) Faith @@ -37,20 +37,20 @@ /** No-op. */ int drm_adddraw(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_draw_t draw; draw.handle = 0; /* NOOP */ DRM_DEBUG("%d\n", draw.handle); - if (copy_to_user((drm_draw_t __user *)arg, &draw, sizeof(draw))) + if (copy_to_user((drm_draw_t __user *) arg, &draw, sizeof(draw))) return -EFAULT; return 0; } /** No-op. */ int drm_rmdraw(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { return 0; /* NOOP */ } diff --git a/linux-core/drm_drv.c b/linux-core/drm_drv.c index 630e29dc..3cc8da02 100644 --- a/linux-core/drm_drv.c +++ b/linux-core/drm_drv.c @@ -1,5 +1,5 @@ /** - * \file drm_drv.h + * \file drm_drv.h * Generic driver template * * \author Rickard E. (Rik) Faith @@ -54,7 +54,7 @@ #include "drmP.h" #include "drm_core.h" -static void __exit drm_cleanup( drm_device_t *dev ); +static void __exit drm_cleanup(drm_device_t * dev); #ifndef MODULE /** Use an additional macro to avoid preprocessor troubles */ @@ -64,80 +64,81 @@ static void __exit drm_cleanup( drm_device_t *dev ); * boot-loader (e.g., LILO). It calls the insmod option routine, * parse_options(). */ -static int __init drm_options( char *str ) +static int __init drm_options(char *str) { - drm_parse_options( str ); + drm_parse_options(str); return 1; } -__setup( DRIVER_NAME "=", DRM_OPTIONS_FUNC ); +__setup(DRIVER_NAME "=", DRM_OPTIONS_FUNC); #undef DRM_OPTIONS_FUNC #endif int drm_fb_loaded = 0; /** Ioctl table */ -drm_ioctl_desc_t drm_ioctls[] = { - [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { drm_version, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_by_busid, 0, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_MAP)] = { drm_getmap, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_CLIENT)] = { drm_getclient, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_STATS)] = { drm_getstats, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_SET_VERSION)] = { drm_setversion, 0, 1 }, - - [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_noop, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_noop, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, - - [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RM_MAP)] = { drm_rmmap, 1, 0 }, - - [DRM_IOCTL_NR(DRM_IOCTL_SET_SAREA_CTX)] = { drm_setsareactx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_SAREA_CTX)] = { drm_getsareactx, 1, 0 }, - - [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { drm_addctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { drm_rmctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { drm_modctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { drm_getctx, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { drm_switchctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { drm_newctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { drm_resctx, 1, 0 }, - - [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, - - [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { drm_lock, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { drm_unlock, 1, 0 }, - - [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_noop, 1, 0 }, - - [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { drm_addbufs, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { drm_markbufs, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { drm_infobufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { drm_mapbufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { drm_freebufs, 1, 0 }, +drm_ioctl_desc_t drm_ioctls[] = { + [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = {drm_version, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = {drm_getunique, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = {drm_getmagic, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = {drm_irq_by_busid, 0, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAP)] = {drm_getmap, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CLIENT)] = {drm_getclient, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_STATS)] = {drm_getstats, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_SET_VERSION)] = {drm_setversion, 0, 1}, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = {drm_setunique, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = {drm_noop, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = {drm_noop, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = {drm_authmagic, 1, 1}, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = {drm_addmap, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_RM_MAP)] = {drm_rmmap, 1, 0}, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_SAREA_CTX)] = {drm_setsareactx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_SAREA_CTX)] = {drm_getsareactx, 1, 0}, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = {drm_addctx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = {drm_rmctx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = {drm_modctx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = {drm_getctx, 1, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = {drm_switchctx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = {drm_newctx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = {drm_resctx, 1, 0}, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = {drm_adddraw, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = {drm_rmdraw, 1, 1}, + + [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = {drm_lock, 1, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = {drm_unlock, 1, 0}, + + [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = {drm_noop, 1, 0}, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = {drm_addbufs, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = {drm_markbufs, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = {drm_infobufs, 1, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = {drm_mapbufs, 1, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = {drm_freebufs, 1, 0}, /* The DRM_IOCTL_DMA ioctl should be defined by the driver. */ + [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = {NULL, 1, 0}, - [DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { drm_control, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = {drm_control, 1, 1}, #if __OS_HAS_AGP - [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = { drm_agp_enable, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = { drm_agp_info, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = { drm_agp_alloc, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = { drm_agp_free, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = {drm_agp_acquire, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = {drm_agp_release, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = {drm_agp_enable, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = {drm_agp_info, 1, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = {drm_agp_alloc, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = {drm_agp_free, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = {drm_agp_bind, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = {drm_agp_unbind, 1, 1}, #endif - [DRM_IOCTL_NR(DRM_IOCTL_SG_ALLOC)] = { drm_sg_alloc, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_SG_FREE)] = { drm_sg_free, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_SG_ALLOC)] = {drm_sg_alloc, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_SG_FREE)] = {drm_sg_free, 1, 1}, - [DRM_IOCTL_NR(DRM_IOCTL_WAIT_VBLANK)] = { drm_wait_vblank, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_WAIT_VBLANK)] = {drm_wait_vblank, 0, 0}, }; #define DRIVER_IOCTL_COUNT DRM_ARRAY_SIZE( drm_ioctls ) @@ -151,7 +152,7 @@ drm_ioctl_desc_t drm_ioctls[] = { * * \sa drm_device and setup(). */ -int drm_takedown( drm_device_t *dev ) +int drm_takedown(drm_device_t * dev) { drm_magic_entry_t *pt, *next; drm_map_t *map; @@ -160,77 +161,79 @@ int drm_takedown( drm_device_t *dev ) drm_vma_entry_t *vma, *vma_next; int i; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); if (dev->fn_tbl->pretakedown) dev->fn_tbl->pretakedown(dev); - if ( dev->irq_enabled ) drm_irq_uninstall( dev ); + if (dev->irq_enabled) + drm_irq_uninstall(dev); - down( &dev->struct_sem ); - del_timer( &dev->timer ); + down(&dev->struct_sem); + del_timer(&dev->timer); - if ( dev->devname ) { - drm_free( dev->devname, strlen( dev->devname ) + 1, - DRM_MEM_DRIVER ); + if (dev->devname) { + drm_free(dev->devname, strlen(dev->devname) + 1, + DRM_MEM_DRIVER); dev->devname = NULL; } - if ( dev->unique ) { - drm_free( dev->unique, strlen( dev->unique ) + 1, - DRM_MEM_DRIVER ); + if (dev->unique) { + drm_free(dev->unique, strlen(dev->unique) + 1, DRM_MEM_DRIVER); dev->unique = NULL; dev->unique_len = 0; } - /* Clear pid list */ - for ( i = 0 ; i < DRM_HASH_SIZE ; i++ ) { - for ( pt = dev->magiclist[i].head ; pt ; pt = next ) { + /* Clear pid list */ + for (i = 0; i < DRM_HASH_SIZE; i++) { + for (pt = dev->magiclist[i].head; pt; pt = next) { next = pt->next; - drm_free( pt, sizeof(*pt), DRM_MEM_MAGIC ); + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); } dev->magiclist[i].head = dev->magiclist[i].tail = NULL; } - /* Clear AGP information */ + /* Clear AGP information */ if (drm_core_has_AGP(dev) && dev->agp) { drm_agp_mem_t *entry; drm_agp_mem_t *nexte; - /* Remove AGP resources, but leave dev->agp - intact until drv_cleanup is called. */ - for ( entry = dev->agp->memory ; entry ; entry = nexte ) { + /* Remove AGP resources, but leave dev->agp + intact until drv_cleanup is called. */ + for (entry = dev->agp->memory; entry; entry = nexte) { nexte = entry->next; - if ( entry->bound ) drm_unbind_agp( entry->memory ); - drm_free_agp( entry->memory, entry->pages ); - drm_free( entry, sizeof(*entry), DRM_MEM_AGPLISTS ); + if (entry->bound) + drm_unbind_agp(entry->memory); + drm_free_agp(entry->memory, entry->pages); + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); } dev->agp->memory = NULL; - if ( dev->agp->acquired ) drm_agp_do_release(); + if (dev->agp->acquired) + drm_agp_do_release(); dev->agp->acquired = 0; - dev->agp->enabled = 0; + dev->agp->enabled = 0; } - /* Clear vma list (only built for debugging) */ - if ( dev->vmalist ) { - for ( vma = dev->vmalist ; vma ; vma = vma_next ) { + /* Clear vma list (only built for debugging) */ + if (dev->vmalist) { + for (vma = dev->vmalist; vma; vma = vma_next) { vma_next = vma->next; - drm_free( vma, sizeof(*vma), DRM_MEM_VMAS ); + drm_free(vma, sizeof(*vma), DRM_MEM_VMAS); } dev->vmalist = NULL; } - if( dev->maplist ) { - list_for_each_safe( list, list_next, &dev->maplist->head ) { - r_list = (drm_map_list_t *)list; + if (dev->maplist) { + list_for_each_safe(list, list_next, &dev->maplist->head) { + r_list = (drm_map_list_t *) list; - if ( ( map = r_list->map ) ) { - switch ( map->type ) { + if ((map = r_list->map)) { + switch (map->type) { case _DRM_REGISTERS: case _DRM_FRAME_BUFFER: continue; - + case _DRM_SHM: vfree(map->handle); break; @@ -242,7 +245,8 @@ int drm_takedown( drm_device_t *dev ) break; case _DRM_SCATTER_GATHER: /* Handle it */ - if (drm_core_check_feature(dev, DRIVER_SG) && dev->sg) { + if (drm_core_check_feature + (dev, DRIVER_SG) && dev->sg) { drm_sg_cleanup(dev->sg); dev->sg = NULL; } @@ -250,38 +254,37 @@ int drm_takedown( drm_device_t *dev ) } drm_free(map, sizeof(*map), DRM_MEM_MAPS); } - list_del( list ); + list_del(list); drm_free(r_list, sizeof(*r_list), DRM_MEM_MAPS); - } - } + } + } - if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) && dev->queuelist) { - for ( i = 0 ; i < dev->queue_count ; i++ ) { + for (i = 0; i < dev->queue_count; i++) { - if ( dev->queuelist[i] ) { - drm_free( dev->queuelist[i], - sizeof(*dev->queuelist[0]), - DRM_MEM_QUEUES ); + if (dev->queuelist[i]) { + drm_free(dev->queuelist[i], + sizeof(*dev->queuelist[0]), + DRM_MEM_QUEUES); dev->queuelist[i] = NULL; } } - drm_free( dev->queuelist, - dev->queue_slots * sizeof(*dev->queuelist), - DRM_MEM_QUEUES ); + drm_free(dev->queuelist, + dev->queue_slots * sizeof(*dev->queuelist), + DRM_MEM_QUEUES); dev->queuelist = NULL; } dev->queue_count = 0; if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) - drm_dma_takedown( dev ); + drm_dma_takedown(dev); - if ( dev->lock.hw_lock ) { - dev->sigdata.lock = dev->lock.hw_lock = NULL; /* SHM removed */ + if (dev->lock.hw_lock) { + dev->sigdata.lock = dev->lock.hw_lock = NULL; /* SHM removed */ dev->lock.filp = NULL; - wake_up_interruptible( &dev->lock.lock_queue ); + wake_up_interruptible(&dev->lock.lock_queue); } - up( &dev->struct_sem ); + up(&dev->struct_sem); return 0; } @@ -289,7 +292,7 @@ int drm_takedown( drm_device_t *dev ) void __exit drm_cleanup_pci(struct pci_dev *pdev) { drm_device_t *dev = pci_get_drvdata(pdev); - + pci_set_drvdata(pdev, NULL); pci_release_regions(pdev); if (dev) @@ -300,7 +303,7 @@ EXPORT_SYMBOL(drm_cleanup_pci); #ifdef MODULE static char *drm_opts = NULL; #endif -MODULE_PARM( drm_opts, "s" ); +MODULE_PARM(drm_opts, "s"); /** * Module initialization. Called via init_module at module load time, or via @@ -311,33 +314,38 @@ MODULE_PARM( drm_opts, "s" ); * Initializes an array of drm_device structures, and attempts to * initialize all available devices, using consecutive minors, registering the * stubs and initializing the AGP device. - * + * * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and * after the initialization for driver customization. */ -int __devinit drm_init( struct pci_driver *driver, struct pci_device_id* pciidlist, struct drm_driver_fn *driver_fn) +int __devinit drm_init(struct pci_driver *driver, + struct pci_device_id *pciidlist, + struct drm_driver_fn *driver_fn) { struct pci_dev *pdev; struct pci_device_id *pid; int i; - - DRM_DEBUG( "\n" ); + + DRM_DEBUG("\n"); #ifdef MODULE - drm_parse_options( drm_opts ); + drm_parse_options(drm_opts); #endif drm_mem_init(); - - for (i=0; (pciidlist[i].vendor != 0) && !drm_fb_loaded; i++) { + + for (i = 0; (pciidlist[i].vendor != 0) && !drm_fb_loaded; i++) { pid = &pciidlist[i]; - + pdev = NULL; /* pass back in pdev to account for multiple identical cards */ - while ((pdev = pci_get_subsys(pid->vendor, pid->device, pid->subvendor, pid->subdevice, pdev))) { + while ((pdev = + pci_get_subsys(pid->vendor, pid->device, pid->subvendor, + pid->subdevice, pdev))) { /* is there already a driver loaded, or (short circuit saves work) */ /* does something like VesaFB have control of the memory region? */ - if (pci_dev_driver(pdev) || pci_request_regions(pdev, "DRM scan")) { + if (pci_dev_driver(pdev) + || pci_request_regions(pdev, "DRM scan")) { /* go into stealth mode */ drm_fb_loaded = 1; pci_dev_put(pdev); @@ -347,16 +355,19 @@ int __devinit drm_init( struct pci_driver *driver, struct pci_device_id* pciidli pci_release_regions(pdev); } } - + if (drm_fb_loaded == 0) pci_register_driver(driver); else { - for (i=0; pciidlist[i].vendor != 0; i++) { + for (i = 0; pciidlist[i].vendor != 0; i++) { pid = &pciidlist[i]; - + pdev = NULL; /* pass back in pdev to account for multiple identical cards */ - while ((pdev = pci_get_subsys(pid->vendor, pid->device, pid->subvendor, pid->subdevice, pdev))) { + while ((pdev = + pci_get_subsys(pid->vendor, pid->device, + pid->subvendor, pid->subdevice, + pdev))) { /* stealth mode requires a manual probe */ drm_probe(pdev, &pciidlist[i], driver_fn); } @@ -371,16 +382,16 @@ EXPORT_SYMBOL(drm_init); * Called via cleanup_module() at module unload time. * * Cleans up all DRM device, calling takedown(). - * + * * \sa drm_init(). */ -static void __exit drm_cleanup( drm_device_t *dev ) +static void __exit drm_cleanup(drm_device_t * dev) { drm_map_t *map; drm_map_list_t *r_list; struct list_head *list, *list_next; - - DRM_DEBUG( "\n" ); + + DRM_DEBUG("\n"); if (!dev) { DRM_ERROR("cleanup called no dev\n"); return; @@ -388,28 +399,33 @@ static void __exit drm_cleanup( drm_device_t *dev ) drm_takedown(dev); - if( dev->maplist ) { - list_for_each_safe( list, list_next, &dev->maplist->head ) { - r_list = (drm_map_list_t *)list; + if (dev->maplist) { + list_for_each_safe(list, list_next, &dev->maplist->head) { + r_list = (drm_map_list_t *) list; - if ( ( map = r_list->map ) ) { - switch ( map->type ) { + if ((map = r_list->map)) { + switch (map->type) { case _DRM_REGISTERS: - drm_ioremapfree( map->handle, map->size, dev ); + drm_ioremapfree(map->handle, map->size, + dev); break; - + case _DRM_FRAME_BUFFER: - if ( drm_core_has_MTRR(dev)) { - if ( map->mtrr >= 0 ) { + if (drm_core_has_MTRR(dev)) { + if (map->mtrr >= 0) { int retcode; - retcode = mtrr_del( map->mtrr, - map->offset, - map->size ); - DRM_DEBUG( "mtrr_del=%d\n", retcode ); + retcode = + mtrr_del(map->mtrr, + map-> + offset, + map->size); + DRM_DEBUG + ("mtrr_del=%d\n", + retcode); } } break; - + case _DRM_SHM: case _DRM_AGP: case _DRM_SCATTER_GATHER: @@ -418,43 +434,44 @@ static void __exit drm_cleanup( drm_device_t *dev ) } drm_free(map, sizeof(*map), DRM_MEM_MAPS); } - list_del( list ); + list_del(list); drm_free(r_list, sizeof(*r_list), DRM_MEM_MAPS); - } + } drm_free(dev->maplist, sizeof(*dev->maplist), DRM_MEM_MAPS); dev->maplist = NULL; - } - if (drm_fb_loaded==0) + } + if (drm_fb_loaded == 0) pci_disable_device(dev->pdev); - drm_ctxbitmap_cleanup( dev ); + drm_ctxbitmap_cleanup(dev); - if (drm_core_has_MTRR(dev) && drm_core_has_AGP(dev) && dev->agp && dev->agp->agp_mtrr >= 0) { + if (drm_core_has_MTRR(dev) && drm_core_has_AGP(dev) && dev->agp + && dev->agp->agp_mtrr >= 0) { int retval; - retval = mtrr_del( dev->agp->agp_mtrr, - dev->agp->agp_info.aper_base, - dev->agp->agp_info.aper_size*1024*1024 ); - DRM_DEBUG( "mtrr_del=%d\n", retval ); + retval = mtrr_del(dev->agp->agp_mtrr, + dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size * 1024 * 1024); + DRM_DEBUG("mtrr_del=%d\n", retval); } - if (drm_core_has_AGP(dev) && dev->agp ) { - drm_free( dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS ); + if (drm_core_has_AGP(dev) && dev->agp) { + drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); dev->agp = NULL; } if (dev->fn_tbl->postcleanup) dev->fn_tbl->postcleanup(dev); - if ( drm_put_minor(dev) ) - DRM_ERROR( "Cannot unload module\n" ); + if (drm_put_minor(dev)) + DRM_ERROR("Cannot unload module\n"); } -void __exit drm_exit (struct pci_driver *driver) +void __exit drm_exit(struct pci_driver *driver) { int i; drm_device_t *dev; drm_minor_t *minor; - - DRM_DEBUG( "\n" ); + + DRM_DEBUG("\n"); if (drm_fb_loaded) { for (i = 0; i < cards_limit; i++) { minor = &drm_minors[i]; @@ -469,24 +486,24 @@ void __exit drm_exit (struct pci_driver *driver) } } else pci_unregister_driver(driver); - DRM_INFO( "Module unloaded\n" ); + DRM_INFO("Module unloaded\n"); } EXPORT_SYMBOL(drm_exit); /** File operations structure */ static struct file_operations drm_stub_fops = { .owner = THIS_MODULE, - .open = drm_stub_open + .open = drm_stub_open }; static int __init drm_core_init(void) { int ret = -ENOMEM; - - cards_limit = (cards_limit < DRM_MAX_MINOR + 1 ? cards_limit : DRM_MAX_MINOR + 1); - drm_minors = drm_calloc(cards_limit, - sizeof(*drm_minors), DRM_MEM_STUB); - if(!drm_minors) + + cards_limit = + (cards_limit < DRM_MAX_MINOR + 1 ? cards_limit : DRM_MAX_MINOR + 1); + drm_minors = drm_calloc(cards_limit, sizeof(*drm_minors), DRM_MEM_STUB); + if (!drm_minors) goto err_p1; if (register_chrdev(DRM_MAJOR, "drm", &drm_stub_fops)) @@ -494,7 +511,7 @@ static int __init drm_core_init(void) drm_class = drm_sysfs_create(THIS_MODULE, "drm"); if (IS_ERR(drm_class)) { - printk (KERN_ERR "DRM: Error creating drm class.\n"); + printk(KERN_ERR "DRM: Error creating drm class.\n"); ret = PTR_ERR(drm_class); goto err_p2; } @@ -505,26 +522,22 @@ static int __init drm_core_init(void) ret = -1; goto err_p3; } - drm_agp = (drm_agp_t *)inter_module_get("drm_agp"); - - DRM_INFO( "Initialized %s %d.%d.%d %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE - ); + drm_agp = (drm_agp_t *) inter_module_get("drm_agp"); + + DRM_INFO("Initialized %s %d.%d.%d %s\n", + DRIVER_NAME, + DRIVER_MAJOR, DRIVER_MINOR, DRIVER_PATCHLEVEL, DRIVER_DATE); return 0; -err_p3: + err_p3: drm_sysfs_destroy(drm_class); -err_p2: + err_p2: unregister_chrdev(DRM_MAJOR, "drm"); drm_free(drm_minors, sizeof(*drm_minors) * cards_limit, DRM_MEM_STUB); -err_p1: + err_p1: return ret; } -static void __exit drm_core_exit (void) +static void __exit drm_core_exit(void) { if (drm_agp) inter_module_put("drm_agp"); @@ -534,13 +547,11 @@ static void __exit drm_core_exit (void) unregister_chrdev(DRM_MAJOR, "drm"); - drm_free(drm_minors, sizeof(*drm_minors) * - cards_limit, DRM_MEM_STUB); + drm_free(drm_minors, sizeof(*drm_minors) * cards_limit, DRM_MEM_STUB); } -module_init( drm_core_init ); -module_exit( drm_core_exit ); - +module_init(drm_core_init); +module_exit(drm_core_exit); /** * Get version information @@ -553,8 +564,8 @@ module_exit( drm_core_exit ); * * Fills in the version information in \p arg. */ -int drm_version( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_version(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -562,19 +573,19 @@ int drm_version( struct inode *inode, struct file *filp, drm_version_t version; int ret; - if ( copy_from_user( &version, argp, sizeof(version) ) ) + if (copy_from_user(&version, argp, sizeof(version))) return -EFAULT; /* version is a required function to return the personality module version */ if ((ret = dev->fn_tbl->version(&version))) return ret; - - if ( copy_to_user( argp, &version, sizeof(version) ) ) + + if (copy_to_user(argp, &version, sizeof(version))) return -EFAULT; return 0; } -/** +/** * Called whenever a process performs an ioctl on /dev/drm. * * \param inode device inode. @@ -586,8 +597,8 @@ int drm_version( struct inode *inode, struct file *filp, * Looks up the ioctl function in the ::ioctls table, checking for root * previleges if so required, and dispatches to the respective function. */ -int drm_ioctl( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -596,38 +607,39 @@ int drm_ioctl( struct inode *inode, struct file *filp, unsigned int nr = DRM_IOCTL_NR(cmd); int retcode = -EINVAL; - atomic_inc( &dev->ioctl_count ); - atomic_inc( &dev->counts[_DRM_STAT_IOCTLS] ); + atomic_inc(&dev->ioctl_count); + atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]); ++priv->ioctl_count; - DRM_DEBUG( "pid=%d, cmd=0x%02x, nr=0x%02x, dev 0x%lx, auth=%d\n", - current->pid, cmd, nr, (long)old_encode_dev(dev->device), - priv->authenticated ); + DRM_DEBUG("pid=%d, cmd=0x%02x, nr=0x%02x, dev 0x%lx, auth=%d\n", + current->pid, cmd, nr, (long)old_encode_dev(dev->device), + priv->authenticated); if (nr < DRIVER_IOCTL_COUNT) ioctl = &drm_ioctls[nr]; - else if ((nr >= DRM_COMMAND_BASE) || (nr < DRM_COMMAND_BASE + dev->fn_tbl->num_ioctls)) + else if ((nr >= DRM_COMMAND_BASE) + || (nr < DRM_COMMAND_BASE + dev->fn_tbl->num_ioctls)) ioctl = &dev->fn_tbl->ioctls[nr - DRM_COMMAND_BASE]; else goto err_i1; func = ioctl->func; - if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->fn_tbl->dma_ioctl) /* Local override? */ + if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->fn_tbl->dma_ioctl) /* Local override? */ func = dev->fn_tbl->dma_ioctl; - if ( !func ) { - DRM_DEBUG( "no function\n" ); + if (!func) { + DRM_DEBUG("no function\n"); retcode = -EINVAL; - } else if ( ( ioctl->root_only && !capable( CAP_SYS_ADMIN ) )|| - ( ioctl->auth_needed && !priv->authenticated ) ) { + } else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN)) || + (ioctl->auth_needed && !priv->authenticated)) { retcode = -EACCES; } else { - retcode = func( inode, filp, cmd, arg ); + retcode = func(inode, filp, cmd, arg); } -err_i1: - atomic_dec( &dev->ioctl_count ); - if (retcode) DRM_DEBUG( "ret = %x\n", retcode); + err_i1: + atomic_dec(&dev->ioctl_count); + if (retcode) + DRM_DEBUG("ret = %x\n", retcode); return retcode; } EXPORT_SYMBOL(drm_ioctl); - diff --git a/linux-core/drm_fops.c b/linux-core/drm_fops.c index fea01130..e6e0e867 100644 --- a/linux-core/drm_fops.c +++ b/linux-core/drm_fops.c @@ -1,7 +1,7 @@ /** - * \file drm_fops.h + * \file drm_fops.h * File operations for DRM - * + * * \author Rickard E. (Rik) Faith * \author Daryll Strauss * \author Gareth Hughes @@ -37,42 +37,41 @@ #include "drmP.h" #include -static int drm_setup( drm_device_t *dev ) +static int drm_setup(drm_device_t * dev) { int i; if (dev->fn_tbl->presetup) dev->fn_tbl->presetup(dev); - atomic_set( &dev->ioctl_count, 0 ); - atomic_set( &dev->vma_count, 0 ); + atomic_set(&dev->ioctl_count, 0); + atomic_set(&dev->vma_count, 0); dev->buf_use = 0; - atomic_set( &dev->buf_alloc, 0 ); + atomic_set(&dev->buf_alloc, 0); - if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) - { - i = drm_dma_setup( dev ); - if ( i < 0 ) + if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) { + i = drm_dma_setup(dev); + if (i < 0) return i; } - - for ( i = 0 ; i < DRM_ARRAY_SIZE(dev->counts) ; i++ ) - atomic_set( &dev->counts[i], 0 ); - for ( i = 0 ; i < DRM_HASH_SIZE ; i++ ) { + for (i = 0; i < DRM_ARRAY_SIZE(dev->counts); i++) + atomic_set(&dev->counts[i], 0); + + for (i = 0; i < DRM_HASH_SIZE; i++) { dev->magiclist[i].head = NULL; dev->magiclist[i].tail = NULL; } - dev->ctxlist = drm_alloc(sizeof(*dev->ctxlist), - DRM_MEM_CTXLIST); - if(dev->ctxlist == NULL) return -ENOMEM; + dev->ctxlist = drm_alloc(sizeof(*dev->ctxlist), DRM_MEM_CTXLIST); + if (dev->ctxlist == NULL) + return -ENOMEM; memset(dev->ctxlist, 0, sizeof(*dev->ctxlist)); INIT_LIST_HEAD(&dev->ctxlist->head); dev->vmalist = NULL; dev->sigdata.lock = dev->lock.hw_lock = NULL; - init_waitqueue_head( &dev->lock.lock_queue ); + init_waitqueue_head(&dev->lock.lock_queue); dev->queue_count = 0; dev->queue_reserved = 0; dev->queue_slots = 0; @@ -84,7 +83,7 @@ static int drm_setup( drm_device_t *dev ) dev->last_context = 0; dev->last_switch = 0; dev->last_checked = 0; - init_waitqueue_head( &dev->context_wait ); + init_waitqueue_head(&dev->context_wait); dev->if_version = 0; dev->ctx_start = 0; @@ -94,14 +93,14 @@ static int drm_setup( drm_device_t *dev ) dev->buf_wp = dev->buf; dev->buf_end = dev->buf + DRM_BSZ; dev->buf_async = NULL; - init_waitqueue_head( &dev->buf_readers ); - init_waitqueue_head( &dev->buf_writers ); + init_waitqueue_head(&dev->buf_readers); + init_waitqueue_head(&dev->buf_writers); - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* * The kernel's context could be created here, but is now created - * in drm_dma_enqueue. This is more resource-efficient for + * in drm_dma_enqueue. This is more resource-efficient for * hardware that does not do DMA, but may mean that * drm_select_queue fails between the time the interrupt is * initialized and the time the queues are initialized. @@ -112,10 +111,9 @@ static int drm_setup( drm_device_t *dev ) return 0; } - /** * Open file. - * + * * \param inode device inode * \param filp file pointer. * \return zero on success or a negative number on failure. @@ -124,7 +122,7 @@ static int drm_setup( drm_device_t *dev ) * increments the device open count. If the open count was previous at zero, * i.e., it's the first that the device is open, then calls setup(). */ -int drm_open( struct inode *inode, struct file *filp ) +int drm_open(struct inode *inode, struct file *filp) { drm_device_t *dev = NULL; int minor = iminor(inode); @@ -132,20 +130,20 @@ int drm_open( struct inode *inode, struct file *filp ) if (!((minor >= 0) && (minor < cards_limit))) return -ENODEV; - + dev = drm_minors[minor].dev; if (!dev) return -ENODEV; - retcode = drm_open_helper( inode, filp, dev ); - if ( !retcode ) { - atomic_inc( &dev->counts[_DRM_STAT_OPENS] ); - spin_lock( &dev->count_lock ); - if ( !dev->open_count++ ) { - spin_unlock( &dev->count_lock ); - return drm_setup( dev ); + retcode = drm_open_helper(inode, filp, dev); + if (!retcode) { + atomic_inc(&dev->counts[_DRM_STAT_OPENS]); + spin_lock(&dev->count_lock); + if (!dev->open_count++) { + spin_unlock(&dev->count_lock); + return drm_setup(dev); } - spin_unlock( &dev->count_lock ); + spin_unlock(&dev->count_lock); } return retcode; @@ -167,7 +165,7 @@ int drm_stub_open(struct inode *inode, struct file *filp) int minor = iminor(inode); int err = -ENODEV; struct file_operations *old_fops; - + DRM_DEBUG("\n"); if (!((minor >= 0) && (minor < cards_limit))) @@ -189,57 +187,60 @@ int drm_stub_open(struct inode *inode, struct file *filp) } /** - * Called whenever a process opens /dev/drm. + * Called whenever a process opens /dev/drm. * * \param inode device inode. * \param filp file pointer. * \param dev device. * \return zero on success or a negative number on failure. - * + * * Creates and initializes a drm_file structure for the file private data in \p * filp and add it into the double linked list in \p dev. */ -int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev) +int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t * dev) { - int minor = iminor(inode); - drm_file_t *priv; + int minor = iminor(inode); + drm_file_t *priv; int ret; - if (filp->f_flags & O_EXCL) return -EBUSY; /* No exclusive opens */ - if (!drm_cpu_valid()) return -EINVAL; + if (filp->f_flags & O_EXCL) + return -EBUSY; /* No exclusive opens */ + if (!drm_cpu_valid()) + return -EINVAL; DRM_DEBUG("pid = %d, minor = %d\n", current->pid, minor); - priv = drm_alloc(sizeof(*priv), DRM_MEM_FILES); - if(!priv) return -ENOMEM; + priv = drm_alloc(sizeof(*priv), DRM_MEM_FILES); + if (!priv) + return -ENOMEM; memset(priv, 0, sizeof(*priv)); - filp->private_data = priv; - priv->uid = current->euid; - priv->pid = current->pid; - priv->minor = minor; - priv->dev = dev; - priv->ioctl_count = 0; + filp->private_data = priv; + priv->uid = current->euid; + priv->pid = current->pid; + priv->minor = minor; + priv->dev = dev; + priv->ioctl_count = 0; priv->authenticated = capable(CAP_SYS_ADMIN); - priv->lock_count = 0; + priv->lock_count = 0; if (dev->fn_tbl->open_helper) { - ret=dev->fn_tbl->open_helper(dev, priv); + ret = dev->fn_tbl->open_helper(dev, priv); if (ret < 0) goto out_free; } down(&dev->struct_sem); if (!dev->file_last) { - priv->next = NULL; - priv->prev = NULL; + priv->next = NULL; + priv->prev = NULL; dev->file_first = priv; - dev->file_last = priv; + dev->file_last = priv; } else { - priv->next = NULL; - priv->prev = dev->file_last; + priv->next = NULL; + priv->prev = dev->file_last; dev->file_last->next = priv; - dev->file_last = priv; + dev->file_last = priv; } up(&dev->struct_sem); @@ -250,31 +251,35 @@ int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev) if (!dev->hose) { struct pci_dev *pci_dev; pci_dev = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, NULL); - if (pci_dev) dev->hose = pci_dev->sysdata; + if (pci_dev) + dev->hose = pci_dev->sysdata; if (!dev->hose) { struct pci_bus *b = pci_bus_b(pci_root_buses.next); - if (b) dev->hose = b->sysdata; + if (b) + dev->hose = b->sysdata; } } #endif return 0; -out_free: + out_free: drm_free(priv, sizeof(*priv), DRM_MEM_FILES); - filp->private_data=NULL; + filp->private_data = NULL; return ret; } /** No-op. */ int drm_fasync(int fd, struct file *filp, int on) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - int retcode; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode; - DRM_DEBUG("fd = %d, device = 0x%lx\n", fd, (long)old_encode_dev(dev->device)); + DRM_DEBUG("fd = %d, device = 0x%lx\n", fd, + (long)old_encode_dev(dev->device)); retcode = fasync_helper(fd, filp, on, &dev->buf_async); - if (retcode < 0) return retcode; + if (retcode < 0) + return retcode; return 0; } EXPORT_SYMBOL(drm_fasync); @@ -291,7 +296,7 @@ EXPORT_SYMBOL(drm_fasync); * data from its list and free it. Decreases the open count and if it reaches * zero calls takedown(). */ -int drm_release( struct inode *inode, struct file *filp ) +int drm_release(struct inode *inode, struct file *filp) { drm_file_t *priv = filp->private_data; drm_device_t *dev; @@ -300,7 +305,7 @@ int drm_release( struct inode *inode, struct file *filp ) lock_kernel(); dev = priv->dev; - DRM_DEBUG( "open_count = %d\n", dev->open_count ); + DRM_DEBUG("open_count = %d\n", dev->open_count); if (dev->fn_tbl->prerelease) dev->fn_tbl->prerelease(dev, filp); @@ -309,134 +314,133 @@ int drm_release( struct inode *inode, struct file *filp ) * Begin inline drm_release */ - DRM_DEBUG( "pid = %d, device = 0x%lx, open_count = %d\n", - current->pid, (long)old_encode_dev(dev->device), dev->open_count ); + DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n", + current->pid, (long)old_encode_dev(dev->device), + dev->open_count); + + if (priv->lock_count && dev->lock.hw_lock && + _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) && + dev->lock.filp == filp) { + DRM_DEBUG("File %p released, freeing lock for context %d\n", + filp, _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); - if ( priv->lock_count && dev->lock.hw_lock && - _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) && - dev->lock.filp == filp ) { - DRM_DEBUG( "File %p released, freeing lock for context %d\n", - filp, - _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) ); - if (dev->fn_tbl->release) dev->fn_tbl->release(dev, filp); - drm_lock_free( dev, &dev->lock.hw_lock->lock, - _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) ); + drm_lock_free(dev, &dev->lock.hw_lock->lock, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); - /* FIXME: may require heavy-handed reset of - hardware at this point, possibly - processed via a callback to the X - server. */ - } - else if ( dev->fn_tbl->release && priv->lock_count && dev->lock.hw_lock ) { + /* FIXME: may require heavy-handed reset of + hardware at this point, possibly + processed via a callback to the X + server. */ + } else if (dev->fn_tbl->release && priv->lock_count + && dev->lock.hw_lock) { /* The lock is required to reclaim buffers */ - DECLARE_WAITQUEUE( entry, current ); + DECLARE_WAITQUEUE(entry, current); - add_wait_queue( &dev->lock.lock_queue, &entry ); + add_wait_queue(&dev->lock.lock_queue, &entry); for (;;) { current->state = TASK_INTERRUPTIBLE; - if ( !dev->lock.hw_lock ) { + if (!dev->lock.hw_lock) { /* Device has been unregistered */ retcode = -EINTR; break; } - if ( drm_lock_take( &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT ) ) { - dev->lock.filp = filp; + if (drm_lock_take(&dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + dev->lock.filp = filp; dev->lock.lock_time = jiffies; - atomic_inc( &dev->counts[_DRM_STAT_LOCKS] ); + atomic_inc(&dev->counts[_DRM_STAT_LOCKS]); break; /* Got lock */ } - /* Contention */ + /* Contention */ schedule(); - if ( signal_pending( current ) ) { + if (signal_pending(current)) { retcode = -ERESTARTSYS; break; } } current->state = TASK_RUNNING; - remove_wait_queue( &dev->lock.lock_queue, &entry ); - if( !retcode ) { + remove_wait_queue(&dev->lock.lock_queue, &entry); + if (!retcode) { if (dev->fn_tbl->release) dev->fn_tbl->release(dev, filp); - drm_lock_free( dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT ); + drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT); } } - - if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) - { + + if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) { dev->fn_tbl->reclaim_buffers(filp); } - drm_fasync( -1, filp, 0 ); + drm_fasync(-1, filp, 0); - down( &dev->ctxlist_sem ); - if ( !list_empty( &dev->ctxlist->head ) ) { + down(&dev->ctxlist_sem); + if (!list_empty(&dev->ctxlist->head)) { drm_ctx_list_t *pos, *n; - list_for_each_entry_safe( pos, n, &dev->ctxlist->head, head ) { - if ( pos->tag == priv && - pos->handle != DRM_KERNEL_CONTEXT ) { + list_for_each_entry_safe(pos, n, &dev->ctxlist->head, head) { + if (pos->tag == priv && + pos->handle != DRM_KERNEL_CONTEXT) { if (dev->fn_tbl->context_dtor) - dev->fn_tbl->context_dtor(dev, pos->handle); + dev->fn_tbl->context_dtor(dev, + pos->handle); - drm_ctxbitmap_free( dev, pos->handle ); + drm_ctxbitmap_free(dev, pos->handle); - list_del( &pos->head ); - drm_free( pos, sizeof(*pos), DRM_MEM_CTXLIST ); + list_del(&pos->head); + drm_free(pos, sizeof(*pos), DRM_MEM_CTXLIST); --dev->ctx_count; } } } - up( &dev->ctxlist_sem ); + up(&dev->ctxlist_sem); - down( &dev->struct_sem ); - if ( priv->remove_auth_on_close == 1 ) { + down(&dev->struct_sem); + if (priv->remove_auth_on_close == 1) { drm_file_t *temp = dev->file_first; - while ( temp ) { + while (temp) { temp->authenticated = 0; temp = temp->next; } } - if ( priv->prev ) { + if (priv->prev) { priv->prev->next = priv->next; } else { - dev->file_first = priv->next; + dev->file_first = priv->next; } - if ( priv->next ) { + if (priv->next) { priv->next->prev = priv->prev; } else { - dev->file_last = priv->prev; + dev->file_last = priv->prev; } - up( &dev->struct_sem ); - + up(&dev->struct_sem); + if (dev->fn_tbl->free_filp_priv) - dev->fn_tbl->free_filp_priv( dev, priv ); - drm_free( priv, sizeof(*priv), DRM_MEM_FILES ); + dev->fn_tbl->free_filp_priv(dev, priv); + drm_free(priv, sizeof(*priv), DRM_MEM_FILES); /* ======================================================== * End inline drm_release */ - atomic_inc( &dev->counts[_DRM_STAT_CLOSES] ); - spin_lock( &dev->count_lock ); - if ( !--dev->open_count ) { - if ( atomic_read( &dev->ioctl_count ) || dev->blocked ) { - DRM_ERROR( "Device busy: %d %d\n", - atomic_read( &dev->ioctl_count ), - dev->blocked ); - spin_unlock( &dev->count_lock ); + atomic_inc(&dev->counts[_DRM_STAT_CLOSES]); + spin_lock(&dev->count_lock); + if (!--dev->open_count) { + if (atomic_read(&dev->ioctl_count) || dev->blocked) { + DRM_ERROR("Device busy: %d %d\n", + atomic_read(&dev->ioctl_count), dev->blocked); + spin_unlock(&dev->count_lock); unlock_kernel(); return -EBUSY; } - spin_unlock( &dev->count_lock ); + spin_unlock(&dev->count_lock); unlock_kernel(); - return drm_takedown( dev ); + return drm_takedown(dev); } - spin_unlock( &dev->count_lock ); + spin_unlock(&dev->count_lock); unlock_kernel(); diff --git a/linux-core/drm_init.c b/linux-core/drm_init.c index f359b8d8..65413474 100644 --- a/linux-core/drm_init.c +++ b/linux-core/drm_init.c @@ -1,5 +1,5 @@ /** - * \file drm_init.h + * \file drm_init.h * Setup/Cleanup for DRM * * \author Rickard E. (Rik) Faith @@ -55,10 +55,14 @@ static void drm_parse_option(char *s) char *c, *r; DRM_DEBUG("\"%s\"\n", s); - if (!s || !*s) return; - for (c = s; *c && *c != ':'; c++); /* find : or \0 */ - if (*c) r = c + 1; else r = NULL; /* remember remainder */ - *c = '\0'; /* terminate */ + if (!s || !*s) + return; + for (c = s; *c && *c != ':'; c++) ; /* find : or \0 */ + if (*c) + r = c + 1; + else + r = NULL; /* remember remainder */ + *c = '\0'; /* terminate */ if (!strcmp(s, "debug")) { drm_flags |= DRM_FLAG_DEBUG; DRM_INFO("Debug messages ON\n"); @@ -70,7 +74,7 @@ static void drm_parse_option(char *s) /** * Parse the insmod "drm_opts=" options, or the command-line - * options passed to the kernel via LILO. + * options passed to the kernel via LILO. * * \param s contains option_list without the 'drm_opts=' part. * @@ -101,14 +105,18 @@ void drm_parse_options(char *s) { char *h, *t, *n; - DRM_DEBUG("\"%s\"\n", s ?: ""); - if (!s || !*s) return; + DRM_DEBUG("\"%s\"\n", s ? : ""); + if (!s || !*s) + return; for (h = t = n = s; h && *h; h = n) { - for (; *t && *t != ';'; t++); /* find ; or \0 */ - if (*t) n = t + 1; else n = NULL; /* remember next */ - *t = '\0'; /* terminate */ - drm_parse_option(h); /* parse */ + for (; *t && *t != ';'; t++) ; /* find ; or \0 */ + if (*t) + n = t + 1; + else + n = NULL; /* remember next */ + *t = '\0'; /* terminate */ + drm_parse_option(h); /* parse */ } } @@ -120,10 +128,11 @@ void drm_parse_options(char *s) int drm_cpu_valid(void) { #if defined(__i386__) - if (boot_cpu_data.x86 == 3) return 0; /* No cmpxchg on a 386 */ + if (boot_cpu_data.x86 == 3) + return 0; /* No cmpxchg on a 386 */ #endif #if defined(__sparc__) && !defined(__sparc_v9__) - return 0; /* No cmpxchg before v9 sparc. */ + return 0; /* No cmpxchg before v9 sparc. */ #endif return 1; } diff --git a/linux-core/drm_ioctl.c b/linux-core/drm_ioctl.c index 7221e5ba..f255b953 100644 --- a/linux-core/drm_ioctl.c +++ b/linux-core/drm_ioctl.c @@ -1,5 +1,5 @@ /** - * \file drm_ioctl.h + * \file drm_ioctl.h * IOCTL processing for DRM * * \author Rickard E. (Rik) Faith @@ -40,7 +40,7 @@ /** * Get the bus id. - * + * * \param inode device inode. * \param filp file pointer. * \param cmd command. @@ -50,12 +50,12 @@ * Copies the bus id from drm_device::unique into user space. */ int drm_getunique(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_unique_t __user *argp = (void __user *)arg; - drm_unique_t u; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_unique_t __user *argp = (void __user *)arg; + drm_unique_t u; if (copy_from_user(&u, argp, sizeof(u))) return -EFAULT; @@ -71,7 +71,7 @@ int drm_getunique(struct inode *inode, struct file *filp, /** * Set the bus id. - * + * * \param inode device inode. * \param filp file pointer. * \param cmd command. @@ -84,30 +84,33 @@ int drm_getunique(struct inode *inode, struct file *filp, * version 1.1 or greater. */ int drm_setunique(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_unique_t u; - int domain, bus, slot, func, ret; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_unique_t u; + int domain, bus, slot, func, ret; - if (dev->unique_len || dev->unique) return -EBUSY; + if (dev->unique_len || dev->unique) + return -EBUSY; - if (copy_from_user(&u, (drm_unique_t __user *)arg, sizeof(u))) + if (copy_from_user(&u, (drm_unique_t __user *) arg, sizeof(u))) return -EFAULT; - if (!u.unique_len || u.unique_len > 1024) return -EINVAL; + if (!u.unique_len || u.unique_len > 1024) + return -EINVAL; dev->unique_len = u.unique_len; - dev->unique = drm_alloc(u.unique_len + 1, DRM_MEM_DRIVER); - if(!dev->unique) return -ENOMEM; + dev->unique = drm_alloc(u.unique_len + 1, DRM_MEM_DRIVER); + if (!dev->unique) + return -ENOMEM; if (copy_from_user(dev->unique, u.unique, dev->unique_len)) return -EFAULT; dev->unique[dev->unique_len] = '\0'; dev->devname = drm_alloc(strlen(dev->name) + strlen(dev->unique) + 2, - DRM_MEM_DRIVER); + DRM_MEM_DRIVER); if (!dev->devname) return -ENOMEM; @@ -121,18 +124,16 @@ int drm_setunique(struct inode *inode, struct file *filp, return DRM_ERR(EINVAL); domain = bus >> 8; bus &= 0xff; - + if ((domain != dev->pci_domain) || (bus != dev->pci_bus) || - (slot != dev->pci_slot) || - (func != dev->pci_func)) + (slot != dev->pci_slot) || (func != dev->pci_func)) return -EINVAL; return 0; } -static int -drm_set_busid(drm_device_t *dev) +static int drm_set_busid(drm_device_t * dev) { if (dev->unique != NULL) return EBUSY; @@ -143,10 +144,10 @@ drm_set_busid(drm_device_t *dev) return ENOMEM; snprintf(dev->unique, dev->unique_len, "pci:%04x:%02x:%02x.%d", - dev->pci_domain, dev->pci_bus, dev->pci_slot, dev->pci_func); + dev->pci_domain, dev->pci_bus, dev->pci_slot, dev->pci_func); dev->devname = drm_alloc(strlen(dev->name) + dev->unique_len + 2, - DRM_MEM_DRIVER); + DRM_MEM_DRIVER); if (dev->devname == NULL) return ENOMEM; @@ -155,7 +156,6 @@ drm_set_busid(drm_device_t *dev) return 0; } - /** * Get a mapping information. * @@ -163,23 +163,23 @@ drm_set_busid(drm_device_t *dev) * \param filp file pointer. * \param cmd command. * \param arg user argument, pointing to a drm_map structure. - * + * * \return zero on success or a negative number on failure. * * Searches for the mapping with the specified offset and copies its information * into userspace */ -int drm_getmap( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_getmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_map_t __user *argp = (void __user *)arg; - drm_map_t map; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_map_t __user *argp = (void __user *)arg; + drm_map_t map; drm_map_list_t *r_list = NULL; struct list_head *list; - int idx; - int i; + int idx; + int i; if (copy_from_user(&map, argp, sizeof(map))) return -EFAULT; @@ -193,26 +193,27 @@ int drm_getmap( struct inode *inode, struct file *filp, i = 0; list_for_each(list, &dev->maplist->head) { - if(i == idx) { + if (i == idx) { r_list = list_entry(list, drm_map_list_t, head); break; } i++; } - if(!r_list || !r_list->map) { + if (!r_list || !r_list->map) { up(&dev->struct_sem); return -EINVAL; } map.offset = r_list->map->offset; - map.size = r_list->map->size; - map.type = r_list->map->type; - map.flags = r_list->map->flags; + map.size = r_list->map->size; + map.type = r_list->map->type; + map.flags = r_list->map->flags; map.handle = r_list->map->handle; - map.mtrr = r_list->map->mtrr; + map.mtrr = r_list->map->mtrr; up(&dev->struct_sem); - if (copy_to_user(argp, &map, sizeof(map))) return -EFAULT; + if (copy_to_user(argp, &map, sizeof(map))) + return -EFAULT; return 0; } @@ -223,39 +224,38 @@ int drm_getmap( struct inode *inode, struct file *filp, * \param filp file pointer. * \param cmd command. * \param arg user argument, pointing to a drm_client structure. - * + * * \return zero on success or a negative number on failure. * * Searches for the client with the specified index and copies its information * into userspace */ -int drm_getclient( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_getclient(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_client_t __user *argp = (void __user *)arg; drm_client_t client; - drm_file_t *pt; - int idx; - int i; + drm_file_t *pt; + int idx; + int i; if (copy_from_user(&client, argp, sizeof(client))) return -EFAULT; idx = client.idx; down(&dev->struct_sem); - for (i = 0, pt = dev->file_first; i < idx && pt; i++, pt = pt->next) - ; + for (i = 0, pt = dev->file_first; i < idx && pt; i++, pt = pt->next) ; if (!pt) { up(&dev->struct_sem); return -EINVAL; } - client.auth = pt->authenticated; - client.pid = pt->pid; - client.uid = pt->uid; + client.auth = pt->authenticated; + client.pid = pt->pid; + client.uid = pt->uid; client.magic = pt->magic; - client.iocs = pt->ioctl_count; + client.iocs = pt->ioctl_count; up(&dev->struct_sem); if (copy_to_user(argp, &client, sizeof(client))) @@ -263,48 +263,47 @@ int drm_getclient( struct inode *inode, struct file *filp, return 0; } -/** - * Get statistics information. - * +/** + * Get statistics information. + * * \param inode device inode. * \param filp file pointer. * \param cmd command. * \param arg user argument, pointing to a drm_stats structure. - * + * * \return zero on success or a negative number on failure. */ -int drm_getstats( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_getstats(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_stats_t stats; - int i; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_stats_t stats; + int i; memset(&stats, 0, sizeof(stats)); - + down(&dev->struct_sem); for (i = 0; i < dev->counters; i++) { if (dev->types[i] == _DRM_STAT_LOCK) stats.data[i].value - = (dev->lock.hw_lock - ? dev->lock.hw_lock->lock : 0); - else + = (dev->lock.hw_lock ? dev->lock.hw_lock->lock : 0); + else stats.data[i].value = atomic_read(&dev->counts[i]); - stats.data[i].type = dev->types[i]; + stats.data[i].type = dev->types[i]; } - + stats.count = dev->counters; up(&dev->struct_sem); - if (copy_to_user((drm_stats_t __user *)arg, &stats, sizeof(stats))) + if (copy_to_user((drm_stats_t __user *) arg, &stats, sizeof(stats))) return -EFAULT; return 0; } -/** +/** * Setversion ioctl. * * \param inode device inode. @@ -359,7 +358,7 @@ int drm_setversion(DRM_IOCTL_ARGS) /** No-op ioctl. */ int drm_noop(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { DRM_DEBUG("\n"); return 0; diff --git a/linux-core/drm_irq.c b/linux-core/drm_irq.c index d8cc56ad..8d4bf327 100644 --- a/linux-core/drm_irq.c +++ b/linux-core/drm_irq.c @@ -1,5 +1,5 @@ /** - * \file drm_irq.h + * \file drm_irq.h * IRQ support * * \author Rickard E. (Rik) Faith @@ -39,19 +39,19 @@ /** * Get interrupt from bus id. - * + * * \param inode device inode. * \param filp file pointer. * \param cmd command. * \param arg user argument, pointing to a drm_irq_busid structure. * \return zero on success or a negative number on failure. - * + * * Finds the PCI device with the specified bus id and gets its IRQ number. * This IOCTL is deprecated, and will now return EINVAL for any busid not equal * to that of the device that this DRM instance attached to. */ int drm_irq_by_busid(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -66,14 +66,12 @@ int drm_irq_by_busid(struct inode *inode, struct file *filp, if ((p.busnum >> 8) != dev->pci_domain || (p.busnum & 0xff) != dev->pci_bus || - p.devnum != dev->pci_slot || - p.funcnum != dev->pci_func) + p.devnum != dev->pci_slot || p.funcnum != dev->pci_func) return -EINVAL; p.irq = dev->irq; - DRM_DEBUG("%d:%d:%d => IRQ %d\n", - p.busnum, p.devnum, p.funcnum, p.irq); + DRM_DEBUG("%d:%d:%d => IRQ %d\n", p.busnum, p.devnum, p.funcnum, p.irq); if (copy_to_user(argp, &p, sizeof(p))) return -EFAULT; return 0; @@ -88,33 +86,33 @@ int drm_irq_by_busid(struct inode *inode, struct file *filp, * \c drm_driver_irq_preinstall() and \c drm_driver_irq_postinstall() functions * before and after the installation. */ -int drm_irq_install( drm_device_t *dev ) +int drm_irq_install(drm_device_t * dev) { int ret; - unsigned long sh_flags=0; + unsigned long sh_flags = 0; if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) return -EINVAL; - if ( dev->irq == 0 ) + if (dev->irq == 0) return -EINVAL; - down( &dev->struct_sem ); + down(&dev->struct_sem); /* Driver must have been initialized */ - if ( !dev->dev_private ) { - up( &dev->struct_sem ); + if (!dev->dev_private) { + up(&dev->struct_sem); return -EINVAL; } - if ( dev->irq_enabled ) { - up( &dev->struct_sem ); + if (dev->irq_enabled) { + up(&dev->struct_sem); return -EBUSY; } dev->irq_enabled = 1; - up( &dev->struct_sem ); + up(&dev->struct_sem); - DRM_DEBUG( "%s: irq=%d\n", __FUNCTION__, dev->irq ); + DRM_DEBUG("%s: irq=%d\n", __FUNCTION__, dev->irq); dev->dma->next_buffer = NULL; dev->dma->next_queue = NULL; @@ -122,31 +120,31 @@ int drm_irq_install( drm_device_t *dev ) if (drm_core_check_feature(dev, DRIVER_IRQ_VBL)) { init_waitqueue_head(&dev->vbl_queue); - - spin_lock_init( &dev->vbl_lock ); - - INIT_LIST_HEAD( &dev->vbl_sigs.head ); - + + spin_lock_init(&dev->vbl_lock); + + INIT_LIST_HEAD(&dev->vbl_sigs.head); + dev->vbl_pending = 0; } - /* Before installing handler */ + /* Before installing handler */ dev->fn_tbl->irq_preinstall(dev); - /* Install handler */ + /* Install handler */ if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED)) sh_flags = SA_SHIRQ; - - ret = request_irq( dev->irq, dev->fn_tbl->irq_handler, - sh_flags, dev->devname, dev ); - if ( ret < 0 ) { - down( &dev->struct_sem ); + + ret = request_irq(dev->irq, dev->fn_tbl->irq_handler, + sh_flags, dev->devname, dev); + if (ret < 0) { + down(&dev->struct_sem); dev->irq_enabled = 0; - up( &dev->struct_sem ); + up(&dev->struct_sem); return ret; } - /* After installing handler */ + /* After installing handler */ dev->fn_tbl->irq_postinstall(dev); return 0; @@ -159,26 +157,26 @@ int drm_irq_install( drm_device_t *dev ) * * Calls the driver's \c drm_driver_irq_uninstall() function, and stops the irq. */ -int drm_irq_uninstall( drm_device_t *dev ) +int drm_irq_uninstall(drm_device_t * dev) { int irq_enabled; if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) return -EINVAL; - down( &dev->struct_sem ); + down(&dev->struct_sem); irq_enabled = dev->irq_enabled; dev->irq_enabled = 0; - up( &dev->struct_sem ); + up(&dev->struct_sem); - if ( !irq_enabled ) + if (!irq_enabled) return -EINVAL; - DRM_DEBUG( "%s: irq=%d\n", __FUNCTION__, dev->irq ); + DRM_DEBUG("%s: irq=%d\n", __FUNCTION__, dev->irq); dev->fn_tbl->irq_uninstall(dev); - free_irq( dev->irq, dev ); + free_irq(dev->irq, dev); return 0; } @@ -195,30 +193,30 @@ EXPORT_SYMBOL(drm_irq_uninstall); * * Calls irq_install() or irq_uninstall() according to \p arg. */ -int drm_control( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_control(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_control_t ctl; - + /* if we haven't irq we fallback for compatibility reasons - this used to be a separate function in drm_dma.h */ - if ( copy_from_user( &ctl, (drm_control_t __user *)arg, sizeof(ctl) ) ) + if (copy_from_user(&ctl, (drm_control_t __user *) arg, sizeof(ctl))) return -EFAULT; - switch ( ctl.func ) { + switch (ctl.func) { case DRM_INST_HANDLER: if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) return 0; if (dev->if_version < DRM_IF_VERSION(1, 2) && ctl.irq != dev->irq) return -EINVAL; - return drm_irq_install( dev ); + return drm_irq_install(dev); case DRM_UNINST_HANDLER: if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) return 0; - return drm_irq_uninstall( dev ); + return drm_irq_uninstall(dev); default: return -EINVAL; } @@ -233,7 +231,7 @@ int drm_control( struct inode *inode, struct file *filp, * \param data user argument, pointing to a drm_wait_vblank structure. * \return zero on success or a negative number on failure. * - * Verifies the IRQ is installed. + * Verifies the IRQ is installed. * * If a signal is requested checks if this task has already scheduled the same signal * for the same vblank sequence number - nothing to be done in @@ -243,7 +241,7 @@ int drm_control( struct inode *inode, struct file *filp, * * If a signal is not requested, then calls vblank_wait(). */ -int drm_wait_vblank( DRM_IOCTL_ARGS ) +int drm_wait_vblank(DRM_IOCTL_ARGS) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -259,11 +257,11 @@ int drm_wait_vblank( DRM_IOCTL_ARGS ) if (!dev->irq) return -EINVAL; - DRM_COPY_FROM_USER_IOCTL( vblwait, argp, sizeof(vblwait) ); + DRM_COPY_FROM_USER_IOCTL(vblwait, argp, sizeof(vblwait)); - switch ( vblwait.request.type & ~_DRM_VBLANK_FLAGS_MASK ) { + switch (vblwait.request.type & ~_DRM_VBLANK_FLAGS_MASK) { case _DRM_VBLANK_RELATIVE: - vblwait.request.sequence += atomic_read( &dev->vbl_received ); + vblwait.request.sequence += atomic_read(&dev->vbl_received); vblwait.request.type &= ~_DRM_VBLANK_RELATIVE; case _DRM_VBLANK_ABSOLUTE: break; @@ -272,64 +270,68 @@ int drm_wait_vblank( DRM_IOCTL_ARGS ) } flags = vblwait.request.type & _DRM_VBLANK_FLAGS_MASK; - - if ( flags & _DRM_VBLANK_SIGNAL ) { + + if (flags & _DRM_VBLANK_SIGNAL) { unsigned long irqflags; drm_vbl_sig_t *vbl_sig; - - vblwait.reply.sequence = atomic_read( &dev->vbl_received ); - spin_lock_irqsave( &dev->vbl_lock, irqflags ); + vblwait.reply.sequence = atomic_read(&dev->vbl_received); + + spin_lock_irqsave(&dev->vbl_lock, irqflags); /* Check if this task has already scheduled the same signal * for the same vblank sequence number; nothing to be done in * that case */ - list_for_each_entry( vbl_sig, &dev->vbl_sigs.head, head ) { + list_for_each_entry(vbl_sig, &dev->vbl_sigs.head, head) { if (vbl_sig->sequence == vblwait.request.sequence && vbl_sig->info.si_signo == vblwait.request.signal - && vbl_sig->task == current) - { - spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + && vbl_sig->task == current) { + spin_unlock_irqrestore(&dev->vbl_lock, + irqflags); goto done; } } - if ( dev->vbl_pending >= 100 ) { - spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + if (dev->vbl_pending >= 100) { + spin_unlock_irqrestore(&dev->vbl_lock, irqflags); return -EBUSY; } dev->vbl_pending++; - spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + spin_unlock_irqrestore(&dev->vbl_lock, irqflags); - if ( !( vbl_sig = drm_alloc( sizeof( drm_vbl_sig_t ), DRM_MEM_DRIVER ) ) ) { + if (! + (vbl_sig = + drm_alloc(sizeof(drm_vbl_sig_t), DRM_MEM_DRIVER))) { return -ENOMEM; } - memset( (void *)vbl_sig, 0, sizeof(*vbl_sig) ); + memset((void *)vbl_sig, 0, sizeof(*vbl_sig)); vbl_sig->sequence = vblwait.request.sequence; vbl_sig->info.si_signo = vblwait.request.signal; vbl_sig->task = current; - spin_lock_irqsave( &dev->vbl_lock, irqflags ); + spin_lock_irqsave(&dev->vbl_lock, irqflags); - list_add_tail( (struct list_head *) vbl_sig, &dev->vbl_sigs.head ); + list_add_tail((struct list_head *)vbl_sig, &dev->vbl_sigs.head); - spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + spin_unlock_irqrestore(&dev->vbl_lock, irqflags); } else { if (dev->fn_tbl->vblank_wait) - ret = dev->fn_tbl->vblank_wait( dev, &vblwait.request.sequence ); + ret = + dev->fn_tbl->vblank_wait(dev, + &vblwait.request.sequence); - do_gettimeofday( &now ); + do_gettimeofday(&now); vblwait.reply.tval_sec = now.tv_sec; vblwait.reply.tval_usec = now.tv_usec; } -done: - DRM_COPY_TO_USER_IOCTL( argp, vblwait, sizeof(vblwait) ); + done: + DRM_COPY_TO_USER_IOCTL(argp, vblwait, sizeof(vblwait)); return ret; } @@ -343,31 +345,30 @@ done: * * If a signal is not requested, then calls vblank_wait(). */ -void drm_vbl_send_signals( drm_device_t *dev ) +void drm_vbl_send_signals(drm_device_t * dev) { struct list_head *list, *tmp; drm_vbl_sig_t *vbl_sig; - unsigned int vbl_seq = atomic_read( &dev->vbl_received ); + unsigned int vbl_seq = atomic_read(&dev->vbl_received); unsigned long flags; - spin_lock_irqsave( &dev->vbl_lock, flags ); + spin_lock_irqsave(&dev->vbl_lock, flags); - list_for_each_safe( list, tmp, &dev->vbl_sigs.head ) { - vbl_sig = list_entry( list, drm_vbl_sig_t, head ); - if ( ( vbl_seq - vbl_sig->sequence ) <= (1<<23) ) { + list_for_each_safe(list, tmp, &dev->vbl_sigs.head) { + vbl_sig = list_entry(list, drm_vbl_sig_t, head); + if ((vbl_seq - vbl_sig->sequence) <= (1 << 23)) { vbl_sig->info.si_code = vbl_seq; - send_sig_info( vbl_sig->info.si_signo, &vbl_sig->info, vbl_sig->task ); + send_sig_info(vbl_sig->info.si_signo, &vbl_sig->info, + vbl_sig->task); - list_del( list ); + list_del(list); - drm_free( vbl_sig, sizeof(*vbl_sig), DRM_MEM_DRIVER ); + drm_free(vbl_sig, sizeof(*vbl_sig), DRM_MEM_DRIVER); dev->vbl_pending--; } } - spin_unlock_irqrestore( &dev->vbl_lock, flags ); + spin_unlock_irqrestore(&dev->vbl_lock, flags); } EXPORT_SYMBOL(drm_vbl_send_signals); - - diff --git a/linux-core/drm_lock.c b/linux-core/drm_lock.c index 84cc460c..ea9485b5 100644 --- a/linux-core/drm_lock.c +++ b/linux-core/drm_lock.c @@ -1,7 +1,7 @@ /** - * \file drm_lock.h + * \file drm_lock.h * IOCTLs for locking - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -35,8 +35,7 @@ #include "drmP.h" - -/** +/** * Lock ioctl. * * \param inode device inode. @@ -47,89 +46,86 @@ * * Add the current task to the lock wait queue, and attempt to take to lock. */ -int drm_lock( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - DECLARE_WAITQUEUE( entry, current ); - drm_lock_t lock; - int ret = 0; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + DECLARE_WAITQUEUE(entry, current); + drm_lock_t lock; + int ret = 0; ++priv->lock_count; - if ( copy_from_user( &lock, (drm_lock_t __user *)arg, sizeof(lock) ) ) + if (copy_from_user(&lock, (drm_lock_t __user *) arg, sizeof(lock))) return -EFAULT; - if ( lock.context == DRM_KERNEL_CONTEXT ) { - DRM_ERROR( "Process %d using kernel context %d\n", - current->pid, lock.context ); - return -EINVAL; - } + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } - DRM_DEBUG( "%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", - lock.context, current->pid, - dev->lock.hw_lock->lock, lock.flags ); + DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, + dev->lock.hw_lock->lock, lock.flags); if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE)) - if ( lock.context < 0 ) + if (lock.context < 0) return -EINVAL; - add_wait_queue( &dev->lock.lock_queue, &entry ); + add_wait_queue(&dev->lock.lock_queue, &entry); for (;;) { current->state = TASK_INTERRUPTIBLE; - if ( !dev->lock.hw_lock ) { + if (!dev->lock.hw_lock) { /* Device has been unregistered */ ret = -EINTR; break; } - if ( drm_lock_take( &dev->lock.hw_lock->lock, - lock.context ) ) { - dev->lock.filp = filp; + if (drm_lock_take(&dev->lock.hw_lock->lock, lock.context)) { + dev->lock.filp = filp; dev->lock.lock_time = jiffies; - atomic_inc( &dev->counts[_DRM_STAT_LOCKS] ); - break; /* Got lock */ + atomic_inc(&dev->counts[_DRM_STAT_LOCKS]); + break; /* Got lock */ } - + /* Contention */ schedule(); - if ( signal_pending( current ) ) { + if (signal_pending(current)) { ret = -ERESTARTSYS; break; } } current->state = TASK_RUNNING; - remove_wait_queue( &dev->lock.lock_queue, &entry ); - - sigemptyset( &dev->sigmask ); - sigaddset( &dev->sigmask, SIGSTOP ); - sigaddset( &dev->sigmask, SIGTSTP ); - sigaddset( &dev->sigmask, SIGTTIN ); - sigaddset( &dev->sigmask, SIGTTOU ); + remove_wait_queue(&dev->lock.lock_queue, &entry); + + sigemptyset(&dev->sigmask); + sigaddset(&dev->sigmask, SIGSTOP); + sigaddset(&dev->sigmask, SIGTSTP); + sigaddset(&dev->sigmask, SIGTTIN); + sigaddset(&dev->sigmask, SIGTTOU); dev->sigdata.context = lock.context; - dev->sigdata.lock = dev->lock.hw_lock; - block_all_signals( drm_notifier, - &dev->sigdata, &dev->sigmask ); - + dev->sigdata.lock = dev->lock.hw_lock; + block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask); + if (dev->fn_tbl->dma_ready && (lock.flags & _DRM_LOCK_READY)) dev->fn_tbl->dma_ready(dev); - - if ( dev->fn_tbl->dma_quiescent && (lock.flags & _DRM_LOCK_QUIESCENT )) + + if (dev->fn_tbl->dma_quiescent && (lock.flags & _DRM_LOCK_QUIESCENT)) return dev->fn_tbl->dma_quiescent(dev); - - - if ( dev->fn_tbl->kernel_context_switch && dev->last_context != lock.context ) { + + if (dev->fn_tbl->kernel_context_switch + && dev->last_context != lock.context) { dev->fn_tbl->kernel_context_switch(dev, dev->last_context, - lock.context); + lock.context); } - - DRM_DEBUG( "%d %s\n", lock.context, ret ? "interrupted" : "has lock" ); + DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); - return ret; + return ret; } -/** +/** * Unlock ioctl. * * \param inode device inode. @@ -140,34 +136,33 @@ int drm_lock( struct inode *inode, struct file *filp, * * Transfer and free the lock. */ -int drm_unlock( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_lock_t lock; - if ( copy_from_user( &lock, (drm_lock_t __user *)arg, sizeof(lock) ) ) + if (copy_from_user(&lock, (drm_lock_t __user *) arg, sizeof(lock))) return -EFAULT; - if ( lock.context == DRM_KERNEL_CONTEXT ) { - DRM_ERROR( "Process %d using kernel context %d\n", - current->pid, lock.context ); + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); return -EINVAL; } - atomic_inc( &dev->counts[_DRM_STAT_UNLOCKS] ); + atomic_inc(&dev->counts[_DRM_STAT_UNLOCKS]); if (dev->fn_tbl->kernel_context_switch_unlock) dev->fn_tbl->kernel_context_switch_unlock(dev); - else - { - drm_lock_transfer( dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT ); - - if ( drm_lock_free( dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT ) ) { - DRM_ERROR( "\n" ); + else { + drm_lock_transfer(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT); + + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); } } @@ -190,8 +185,10 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context) do { old = *lock; - if (old & _DRM_LOCK_HELD) new = old | _DRM_LOCK_CONT; - else new = context | _DRM_LOCK_HELD; + if (old & _DRM_LOCK_HELD) + new = old | _DRM_LOCK_CONT; + else + new = context | _DRM_LOCK_HELD; prev = cmpxchg(lock, old, new); } while (prev != old); if (_DRM_LOCKING_CONTEXT(old) == context) { @@ -204,7 +201,7 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context) } } if (new == (context | _DRM_LOCK_HELD)) { - /* Have lock */ + /* Have lock */ return 1; } return 0; @@ -212,8 +209,8 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context) /** * This takes a lock forcibly and hands it to context. Should ONLY be used - * inside *_unlock to give lock to kernel before calling *_dma_schedule. - * + * inside *_unlock to give lock to kernel before calling *_dma_schedule. + * * \param dev DRM device. * \param lock lock pointer. * \param context locking context. @@ -222,15 +219,15 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context) * Resets the lock file pointer. * Marks the lock as held by the given context, via the \p cmpxchg instruction. */ -int drm_lock_transfer(drm_device_t *dev, - __volatile__ unsigned int *lock, unsigned int context) +int drm_lock_transfer(drm_device_t * dev, + __volatile__ unsigned int *lock, unsigned int context) { unsigned int old, new, prev; dev->lock.filp = NULL; do { - old = *lock; - new = context | _DRM_LOCK_HELD; + old = *lock; + new = context | _DRM_LOCK_HELD; prev = cmpxchg(lock, old, new); } while (prev != old); return 1; @@ -238,30 +235,29 @@ int drm_lock_transfer(drm_device_t *dev, /** * Free lock. - * + * * \param dev DRM device. * \param lock lock. * \param context context. - * + * * Resets the lock file pointer. * Marks the lock as not held, via the \p cmpxchg instruction. Wakes any task * waiting on the lock queue. */ -int drm_lock_free(drm_device_t *dev, - __volatile__ unsigned int *lock, unsigned int context) +int drm_lock_free(drm_device_t * dev, + __volatile__ unsigned int *lock, unsigned int context) { unsigned int old, new, prev; dev->lock.filp = NULL; do { - old = *lock; - new = 0; + old = *lock; + new = 0; prev = cmpxchg(lock, old, new); } while (prev != old); if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) { DRM_ERROR("%d freed heavyweight lock held by %d\n", - context, - _DRM_LOCKING_CONTEXT(old)); + context, _DRM_LOCKING_CONTEXT(old)); return 1; } wake_up_interruptible(&dev->lock.lock_queue); @@ -281,19 +277,19 @@ int drm_lock_free(drm_device_t *dev, */ int drm_notifier(void *priv) { - drm_sigdata_t *s = (drm_sigdata_t *)priv; - unsigned int old, new, prev; - + drm_sigdata_t *s = (drm_sigdata_t *) priv; + unsigned int old, new, prev; - /* Allow signal delivery if lock isn't held */ + /* Allow signal delivery if lock isn't held */ if (!s->lock || !_DRM_LOCK_IS_HELD(s->lock->lock) - || _DRM_LOCKING_CONTEXT(s->lock->lock) != s->context) return 1; + || _DRM_LOCKING_CONTEXT(s->lock->lock) != s->context) + return 1; - /* Otherwise, set flag to force call to - drmUnlock */ + /* Otherwise, set flag to force call to + drmUnlock */ do { - old = s->lock->lock; - new = old | _DRM_LOCK_CONT; + old = s->lock->lock; + new = old | _DRM_LOCK_CONT; prev = cmpxchg(&s->lock->lock, old, new); } while (prev != old); return 0; diff --git a/linux-core/drm_memory.c b/linux-core/drm_memory.c index 81f109b3..008e69ec 100644 --- a/linux-core/drm_memory.c +++ b/linux-core/drm_memory.c @@ -1,12 +1,12 @@ -/** - * \file drm_memory.h +/** + * \file drm_memory.h * Memory management wrappers for DRM * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ -/* +/* * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. @@ -48,7 +48,7 @@ void drm_mem_init(void) /** * Called when "/proc/dri/%dev%/mem" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -57,10 +57,10 @@ void drm_mem_init(void) * \param data private data. * \return number of written bytes. * - * No-op. + * No-op. */ int drm_mem_info(char *buf, char **start, off_t offset, - int len, int *eof, void *data) + int len, int *eof, void *data) { return 0; } @@ -83,7 +83,8 @@ void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area) { void *pt; - if (!(pt = kmalloc(size, GFP_KERNEL))) return NULL; + if (!(pt = kmalloc(size, GFP_KERNEL))) + return NULL; if (oldpt && oldsize) { memcpy(pt, oldpt, oldsize); kfree(oldpt); @@ -103,21 +104,20 @@ void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area) unsigned long drm_alloc_pages(int order, int area) { unsigned long address; - unsigned long bytes = PAGE_SIZE << order; + unsigned long bytes = PAGE_SIZE << order; unsigned long addr; - unsigned int sz; + unsigned int sz; address = __get_free_pages(GFP_KERNEL, order); - if (!address) + if (!address) return 0; - /* Zero */ + /* Zero */ memset((void *)address, 0, bytes); - /* Reserve */ + /* Reserve */ for (addr = address, sz = bytes; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { SetPageReserved(virt_to_page(addr)); } @@ -126,7 +126,7 @@ unsigned long drm_alloc_pages(int order, int area) /** * Free pages. - * + * * \param address address of the pages to free. * \param order size order. * \param area memory area. (Not used.) @@ -137,22 +137,20 @@ void drm_free_pages(unsigned long address, int order, int area) { unsigned long bytes = PAGE_SIZE << order; unsigned long addr; - unsigned int sz; + unsigned int sz; - if (!address) + if (!address) return; /* Unreserve */ for (addr = address, sz = bytes; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { ClearPageReserved(virt_to_page(addr)); } free_pages(address, order); } - #if __OS_HAS_AGP /** Wrapper around agp_allocate_memory() */ DRM_AGP_MEM *drm_alloc_agp(int pages, u32 type) @@ -161,21 +159,21 @@ DRM_AGP_MEM *drm_alloc_agp(int pages, u32 type) } /** Wrapper around agp_free_memory() */ -int drm_free_agp(DRM_AGP_MEM *handle, int pages) +int drm_free_agp(DRM_AGP_MEM * handle, int pages) { return drm_agp_free_memory(handle) ? 0 : -EINVAL; } /** Wrapper around agp_bind_memory() */ -int drm_bind_agp(DRM_AGP_MEM *handle, unsigned int start) +int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start) { return drm_agp_bind_memory(handle, start); } /** Wrapper around agp_unbind_memory() */ -int drm_unbind_agp(DRM_AGP_MEM *handle) +int drm_unbind_agp(DRM_AGP_MEM * handle) { return drm_agp_unbind_memory(handle); } -#endif /* agp */ -#endif /* debug_memory */ +#endif /* agp */ +#endif /* debug_memory */ diff --git a/linux-core/drm_memory.h b/linux-core/drm_memory.h index cb90b514..3a31e74b 100644 --- a/linux-core/drm_memory.h +++ b/linux-core/drm_memory.h @@ -1,12 +1,12 @@ -/** - * \file drm_memory.h +/** + * \file drm_memory.h * Memory management wrappers for DRM * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ -/* +/* * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. @@ -39,7 +39,7 @@ /** * Cut down version of drm_memory_debug.h, which used to be called - * drm_memory.h. + * drm_memory.h. */ /* Need the 4-argument version of vmap(). */ @@ -72,8 +72,8 @@ /* * Find the drm_map that covers the range [offset, offset+size). */ -static inline drm_map_t * -drm_lookup_map (unsigned long offset, unsigned long size, drm_device_t *dev) +static inline drm_map_t *drm_lookup_map(unsigned long offset, + unsigned long size, drm_device_t * dev) { struct list_head *list; drm_map_list_t *r_list; @@ -84,16 +84,18 @@ drm_lookup_map (unsigned long offset, unsigned long size, drm_device_t *dev) map = r_list->map; if (!map) continue; - if (map->offset <= offset && (offset + size) <= (map->offset + map->size)) + if (map->offset <= offset + && (offset + size) <= (map->offset + map->size)) return map; } return NULL; } -static inline void * -agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) +static inline void *agp_remap(unsigned long offset, unsigned long size, + drm_device_t * dev) { - unsigned long *phys_addr_map, i, num_pages = PAGE_ALIGN(size) / PAGE_SIZE; + unsigned long *phys_addr_map, i, num_pages = + PAGE_ALIGN(size) / PAGE_SIZE; struct drm_agp_mem *agpmem; struct page **page_map; void *addr; @@ -106,7 +108,8 @@ agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) for (agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) if (agpmem->bound <= offset - && (agpmem->bound + (agpmem->pages << PAGE_SHIFT)) >= (offset + size)) + && (agpmem->bound + (agpmem->pages << PAGE_SHIFT)) >= + (offset + size)) break; if (!agpmem) return NULL; @@ -121,7 +124,8 @@ agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) if (!page_map) return NULL; - phys_addr_map = agpmem->memory->memory + (offset - agpmem->bound) / PAGE_SIZE; + phys_addr_map = + agpmem->memory->memory + (offset - agpmem->bound) / PAGE_SIZE; for (i = 0; i < num_pages; ++i) page_map[i] = pfn_to_page(phys_addr_map[i] >> PAGE_SHIFT); addr = vmap(page_map, num_pages, VM_IOREMAP, PAGE_AGP); @@ -130,35 +134,37 @@ agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) return addr; } -static inline unsigned long -drm_follow_page (void *vaddr) +static inline unsigned long drm_follow_page(void *vaddr) { - pgd_t *pgd = pgd_offset_k((unsigned long) vaddr); - pmd_t *pmd = pmd_offset(pgd, (unsigned long) vaddr); - pte_t *ptep = pte_offset_kernel(pmd, (unsigned long) vaddr); + pgd_t *pgd = pgd_offset_k((unsigned long)vaddr); + pmd_t *pmd = pmd_offset(pgd, (unsigned long)vaddr); + pte_t *ptep = pte_offset_kernel(pmd, (unsigned long)vaddr); return pte_pfn(*ptep) << PAGE_SHIFT; } -#else /* __OS_HAS_AGP */ +#else /* __OS_HAS_AGP */ -static inline drm_map_t *drm_lookup_map(unsigned long offset, unsigned long size, drm_device_t *dev) +static inline drm_map_t *drm_lookup_map(unsigned long offset, + unsigned long size, drm_device_t * dev) { - return NULL; + return NULL; } -static inline void *agp_remap(unsigned long offset, unsigned long size, drm_device_t *dev) +static inline void *agp_remap(unsigned long offset, unsigned long size, + drm_device_t * dev) { - return NULL; + return NULL; } -static inline unsigned long drm_follow_page (void *vaddr) +static inline unsigned long drm_follow_page(void *vaddr) { - return 0; + return 0; } #endif -static inline void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t *dev) +static inline void *drm_ioremap(unsigned long offset, unsigned long size, + drm_device_t * dev) { #if defined(VMAP_4_ARGS) if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture) { @@ -172,8 +178,8 @@ static inline void *drm_ioremap(unsigned long offset, unsigned long size, drm_de return ioremap(offset, size); } -static inline void *drm_ioremap_nocache(unsigned long offset, unsigned long size, - drm_device_t *dev) +static inline void *drm_ioremap_nocache(unsigned long offset, + unsigned long size, drm_device_t * dev) { #if defined(VMAP_4_ARGS) if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture) { @@ -187,7 +193,8 @@ static inline void *drm_ioremap_nocache(unsigned long offset, unsigned long size return ioremap_nocache(offset, size); } -static inline void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *dev) +static inline void drm_ioremapfree(void *pt, unsigned long size, + drm_device_t * dev) { #if defined(VMAP_4_ARGS) /* @@ -196,12 +203,12 @@ static inline void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *d * a future revision of the interface... */ if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture - && ((unsigned long) pt >= VMALLOC_START && (unsigned long) pt < VMALLOC_END)) - { + && ((unsigned long)pt >= VMALLOC_START + && (unsigned long)pt < VMALLOC_END)) { unsigned long offset; drm_map_t *map; - offset = drm_follow_page(pt) | ((unsigned long) pt & ~PAGE_MASK); + offset = drm_follow_page(pt) | ((unsigned long)pt & ~PAGE_MASK); map = drm_lookup_map(offset, size, dev); if (map && map->type == _DRM_AGP) { vunmap(pt); @@ -209,6 +216,5 @@ static inline void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *d } } #endif - iounmap(pt); } diff --git a/linux-core/drm_memory_debug.c b/linux-core/drm_memory_debug.c index 2c3564af..39dfa75e 100644 --- a/linux-core/drm_memory_debug.c +++ b/linux-core/drm_memory_debug.c @@ -1,5 +1,5 @@ /** - * \file drm_memory_debug.h + * \file drm_memory_debug.h * Memory management wrappers for DRM. * * \author Rickard E. (Rik) Faith @@ -35,75 +35,75 @@ #include "drmP.h" typedef struct drm_mem_stats { - const char *name; - int succeed_count; - int free_count; - int fail_count; - unsigned long bytes_allocated; - unsigned long bytes_freed; + const char *name; + int succeed_count; + int free_count; + int fail_count; + unsigned long bytes_allocated; + unsigned long bytes_freed; } drm_mem_stats_t; -static spinlock_t drm_mem_lock = SPIN_LOCK_UNLOCKED; -static unsigned long drm_ram_available = 0; /* In pages */ -static unsigned long drm_ram_used = 0; -static drm_mem_stats_t drm_mem_stats[] = { - [DRM_MEM_DMA] = { "dmabufs" }, - [DRM_MEM_SAREA] = { "sareas" }, - [DRM_MEM_DRIVER] = { "driver" }, - [DRM_MEM_MAGIC] = { "magic" }, - [DRM_MEM_IOCTLS] = { "ioctltab" }, - [DRM_MEM_MAPS] = { "maplist" }, - [DRM_MEM_VMAS] = { "vmalist" }, - [DRM_MEM_BUFS] = { "buflist" }, - [DRM_MEM_SEGS] = { "seglist" }, - [DRM_MEM_PAGES] = { "pagelist" }, - [DRM_MEM_FILES] = { "files" }, - [DRM_MEM_QUEUES] = { "queues" }, - [DRM_MEM_CMDS] = { "commands" }, - [DRM_MEM_MAPPINGS] = { "mappings" }, - [DRM_MEM_BUFLISTS] = { "buflists" }, - [DRM_MEM_AGPLISTS] = { "agplist" }, - [DRM_MEM_SGLISTS] = { "sglist" }, - [DRM_MEM_TOTALAGP] = { "totalagp" }, - [DRM_MEM_BOUNDAGP] = { "boundagp" }, - [DRM_MEM_CTXBITMAP] = { "ctxbitmap"}, - [DRM_MEM_CTXLIST] = { "ctxlist" }, - [DRM_MEM_STUB] = { "stub" }, - { NULL, 0, } /* Last entry must be null */ +static spinlock_t drm_mem_lock = SPIN_LOCK_UNLOCKED; +static unsigned long drm_ram_available = 0; /* In pages */ +static unsigned long drm_ram_used = 0; +static drm_mem_stats_t drm_mem_stats[] = { + [DRM_MEM_DMA] = {"dmabufs"}, + [DRM_MEM_SAREA] = {"sareas"}, + [DRM_MEM_DRIVER] = {"driver"}, + [DRM_MEM_MAGIC] = {"magic"}, + [DRM_MEM_IOCTLS] = {"ioctltab"}, + [DRM_MEM_MAPS] = {"maplist"}, + [DRM_MEM_VMAS] = {"vmalist"}, + [DRM_MEM_BUFS] = {"buflist"}, + [DRM_MEM_SEGS] = {"seglist"}, + [DRM_MEM_PAGES] = {"pagelist"}, + [DRM_MEM_FILES] = {"files"}, + [DRM_MEM_QUEUES] = {"queues"}, + [DRM_MEM_CMDS] = {"commands"}, + [DRM_MEM_MAPPINGS] = {"mappings"}, + [DRM_MEM_BUFLISTS] = {"buflists"}, + [DRM_MEM_AGPLISTS] = {"agplist"}, + [DRM_MEM_SGLISTS] = {"sglist"}, + [DRM_MEM_TOTALAGP] = {"totalagp"}, + [DRM_MEM_BOUNDAGP] = {"boundagp"}, + [DRM_MEM_CTXBITMAP] = {"ctxbitmap"}, + [DRM_MEM_CTXLIST] = {"ctxlist"}, + [DRM_MEM_STUB] = {"stub"}, + {NULL, 0,} /* Last entry must be null */ }; void drm_mem_init(void) { drm_mem_stats_t *mem; - struct sysinfo si; + struct sysinfo si; for (mem = drm_mem_stats; mem->name; ++mem) { - mem->succeed_count = 0; - mem->free_count = 0; - mem->fail_count = 0; + mem->succeed_count = 0; + mem->free_count = 0; + mem->fail_count = 0; mem->bytes_allocated = 0; - mem->bytes_freed = 0; + mem->bytes_freed = 0; } si_meminfo(&si); drm_ram_available = si.totalram; - drm_ram_used = 0; + drm_ram_used = 0; } /* drm_mem_info is called whenever a process reads /dev/drm/mem. */ static int drm__mem_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data) + int request, int *eof, void *data) { drm_mem_stats_t *pt; - int len = 0; + int len = 0; if (offset > DRM_PROC_LIMIT) { *eof = 1; return 0; } - *eof = 0; + *eof = 0; *start = &buf[offset]; DRM_PROC_PRINT(" total counts " @@ -129,13 +129,14 @@ static int drm__mem_info(char *buf, char **start, off_t offset, - (long)pt->bytes_freed); } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } int drm_mem_info(char *buf, char **start, off_t offset, - int len, int *eof, void *data) + int len, int *eof, void *data) { int ret; @@ -182,7 +183,8 @@ void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area) { void *pt; - if (!(pt = drm_alloc(size, area))) return NULL; + if (!(pt = drm_alloc(size, area))) + return NULL; if (oldpt && oldsize) { memcpy(pt, oldpt, oldsize); drm_free(oldpt, oldsize, area); @@ -195,12 +197,14 @@ void drm_free(void *pt, size_t size, int area) int alloc_count; int free_count; - if (!pt) DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n"); - else kfree(pt); + if (!pt) + DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n"); + else + kfree(pt); spin_lock(&drm_mem_lock); drm_mem_stats[area].bytes_freed += size; - free_count = ++drm_mem_stats[area].free_count; - alloc_count = drm_mem_stats[area].succeed_count; + free_count = ++drm_mem_stats[area].free_count; + alloc_count = drm_mem_stats[area].succeed_count; spin_unlock(&drm_mem_lock); if (free_count > alloc_count) { DRM_MEM_ERROR(area, "Excess frees: %d frees, %d allocs\n", @@ -211,9 +215,9 @@ void drm_free(void *pt, size_t size, int area) unsigned long drm_alloc_pages(int order, int area) { unsigned long address; - unsigned long bytes = PAGE_SIZE << order; + unsigned long bytes = PAGE_SIZE << order; unsigned long addr; - unsigned int sz; + unsigned int sz; spin_lock(&drm_mem_lock); if ((drm_ram_used >> PAGE_SHIFT) @@ -233,17 +237,15 @@ unsigned long drm_alloc_pages(int order, int area) spin_lock(&drm_mem_lock); ++drm_mem_stats[area].succeed_count; drm_mem_stats[area].bytes_allocated += bytes; - drm_ram_used += bytes; + drm_ram_used += bytes; spin_unlock(&drm_mem_lock); - - /* Zero outside the lock */ + /* Zero outside the lock */ memset((void *)address, 0, bytes); - /* Reserve */ + /* Reserve */ for (addr = address, sz = bytes; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { SetPageReserved(virt_to_page(addr)); } @@ -253,28 +255,27 @@ unsigned long drm_alloc_pages(int order, int area) void drm_free_pages(unsigned long address, int order, int area) { unsigned long bytes = PAGE_SIZE << order; - int alloc_count; - int free_count; + int alloc_count; + int free_count; unsigned long addr; - unsigned int sz; + unsigned int sz; if (!address) { DRM_MEM_ERROR(area, "Attempt to free address 0\n"); } else { - /* Unreserve */ + /* Unreserve */ for (addr = address, sz = bytes; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { ClearPageReserved(virt_to_page(addr)); } free_pages(address, order); } spin_lock(&drm_mem_lock); - free_count = ++drm_mem_stats[area].free_count; - alloc_count = drm_mem_stats[area].succeed_count; + free_count = ++drm_mem_stats[area].free_count; + alloc_count = drm_mem_stats[area].succeed_count; drm_mem_stats[area].bytes_freed += bytes; - drm_ram_used -= bytes; + drm_ram_used -= bytes; spin_unlock(&drm_mem_lock); if (free_count > alloc_count) { DRM_MEM_ERROR(area, @@ -283,7 +284,7 @@ void drm_free_pages(unsigned long address, int order, int area) } } -void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t *dev) +void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t * dev) { void *pt; @@ -306,7 +307,8 @@ void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t *dev) return pt; } -void *drm_ioremap_nocache(unsigned long offset, unsigned long size, drm_device_t *dev) +void *drm_ioremap_nocache(unsigned long offset, unsigned long size, + drm_device_t * dev) { void *pt; @@ -329,7 +331,7 @@ void *drm_ioremap_nocache(unsigned long offset, unsigned long size, drm_device_t return pt; } -void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *dev) +void drm_ioremapfree(void *pt, unsigned long size, drm_device_t * dev) { int alloc_count; int free_count; @@ -342,8 +344,8 @@ void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *dev) spin_lock(&drm_mem_lock); drm_mem_stats[DRM_MEM_MAPPINGS].bytes_freed += size; - free_count = ++drm_mem_stats[DRM_MEM_MAPPINGS].free_count; - alloc_count = drm_mem_stats[DRM_MEM_MAPPINGS].succeed_count; + free_count = ++drm_mem_stats[DRM_MEM_MAPPINGS].free_count; + alloc_count = drm_mem_stats[DRM_MEM_MAPPINGS].succeed_count; spin_unlock(&drm_mem_lock); if (free_count > alloc_count) { DRM_MEM_ERROR(DRM_MEM_MAPPINGS, @@ -367,7 +369,7 @@ DRM_AGP_MEM *drm_alloc_agp(int pages, u32 type) spin_lock(&drm_mem_lock); ++drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count; drm_mem_stats[DRM_MEM_TOTALAGP].bytes_allocated - += pages << PAGE_SHIFT; + += pages << PAGE_SHIFT; spin_unlock(&drm_mem_lock); return handle; } @@ -377,11 +379,11 @@ DRM_AGP_MEM *drm_alloc_agp(int pages, u32 type) return NULL; } -int drm_free_agp(DRM_AGP_MEM *handle, int pages) +int drm_free_agp(DRM_AGP_MEM * handle, int pages) { - int alloc_count; - int free_count; - int retval = -EINVAL; + int alloc_count; + int free_count; + int retval = -EINVAL; if (!handle) { DRM_MEM_ERROR(DRM_MEM_TOTALAGP, @@ -391,10 +393,10 @@ int drm_free_agp(DRM_AGP_MEM *handle, int pages) if (drm_agp_free_memory(handle)) { spin_lock(&drm_mem_lock); - free_count = ++drm_mem_stats[DRM_MEM_TOTALAGP].free_count; - alloc_count = drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count; + free_count = ++drm_mem_stats[DRM_MEM_TOTALAGP].free_count; + alloc_count = drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count; drm_mem_stats[DRM_MEM_TOTALAGP].bytes_freed - += pages << PAGE_SHIFT; + += pages << PAGE_SHIFT; spin_unlock(&drm_mem_lock); if (free_count > alloc_count) { DRM_MEM_ERROR(DRM_MEM_TOTALAGP, @@ -406,7 +408,7 @@ int drm_free_agp(DRM_AGP_MEM *handle, int pages) return retval; } -int drm_bind_agp(DRM_AGP_MEM *handle, unsigned int start) +int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start) { int retcode = -EINVAL; @@ -420,7 +422,7 @@ int drm_bind_agp(DRM_AGP_MEM *handle, unsigned int start) spin_lock(&drm_mem_lock); ++drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count; drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_allocated - += handle->page_count << PAGE_SHIFT; + += handle->page_count << PAGE_SHIFT; spin_unlock(&drm_mem_lock); return retcode; } @@ -430,7 +432,7 @@ int drm_bind_agp(DRM_AGP_MEM *handle, unsigned int start) return retcode; } -int drm_unbind_agp(DRM_AGP_MEM *handle) +int drm_unbind_agp(DRM_AGP_MEM * handle) { int alloc_count; int free_count; @@ -442,12 +444,13 @@ int drm_unbind_agp(DRM_AGP_MEM *handle) return retcode; } - if ((retcode = drm_agp_unbind_memory(handle))) return retcode; + if ((retcode = drm_agp_unbind_memory(handle))) + return retcode; spin_lock(&drm_mem_lock); - free_count = ++drm_mem_stats[DRM_MEM_BOUNDAGP].free_count; + free_count = ++drm_mem_stats[DRM_MEM_BOUNDAGP].free_count; alloc_count = drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count; drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_freed - += handle->page_count << PAGE_SHIFT; + += handle->page_count << PAGE_SHIFT; spin_unlock(&drm_mem_lock); if (free_count > alloc_count) { DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, diff --git a/linux-core/drm_memory_debug.h b/linux-core/drm_memory_debug.h index fb046965..2a84c2c9 100644 --- a/linux-core/drm_memory_debug.h +++ b/linux-core/drm_memory_debug.h @@ -1,5 +1,5 @@ /** - * \file drm_memory_debug.h + * \file drm_memory_debug.h * Memory management wrappers for DRM. * * \author Rickard E. (Rik) Faith @@ -35,75 +35,74 @@ #include "drmP.h" typedef struct drm_mem_stats { - const char *name; - int succeed_count; - int free_count; - int fail_count; - unsigned long bytes_allocated; - unsigned long bytes_freed; + const char *name; + int succeed_count; + int free_count; + int fail_count; + unsigned long bytes_allocated; + unsigned long bytes_freed; } drm_mem_stats_t; -static spinlock_t DRM(mem_lock) = SPIN_LOCK_UNLOCKED; -static unsigned long DRM(ram_available) = 0; /* In pages */ -static unsigned long DRM(ram_used) = 0; -static drm_mem_stats_t DRM(mem_stats)[] = { - [DRM_MEM_DMA] = { "dmabufs" }, - [DRM_MEM_SAREA] = { "sareas" }, - [DRM_MEM_DRIVER] = { "driver" }, - [DRM_MEM_MAGIC] = { "magic" }, - [DRM_MEM_IOCTLS] = { "ioctltab" }, - [DRM_MEM_MAPS] = { "maplist" }, - [DRM_MEM_VMAS] = { "vmalist" }, - [DRM_MEM_BUFS] = { "buflist" }, - [DRM_MEM_SEGS] = { "seglist" }, - [DRM_MEM_PAGES] = { "pagelist" }, - [DRM_MEM_FILES] = { "files" }, - [DRM_MEM_QUEUES] = { "queues" }, - [DRM_MEM_CMDS] = { "commands" }, - [DRM_MEM_MAPPINGS] = { "mappings" }, - [DRM_MEM_BUFLISTS] = { "buflists" }, - [DRM_MEM_AGPLISTS] = { "agplist" }, - [DRM_MEM_SGLISTS] = { "sglist" }, - [DRM_MEM_TOTALAGP] = { "totalagp" }, - [DRM_MEM_BOUNDAGP] = { "boundagp" }, - [DRM_MEM_CTXBITMAP] = { "ctxbitmap"}, - [DRM_MEM_CTXLIST] = { "ctxlist" }, - [DRM_MEM_STUB] = { "stub" }, - { NULL, 0, } /* Last entry must be null */ +static spinlock_t DRM(mem_lock) = SPIN_LOCK_UNLOCKED; +static unsigned long DRM(ram_available) = 0; /* In pages */ +static unsigned long DRM(ram_used) = 0; +static drm_mem_stats_t DRM(mem_stats)[] = +{ + [DRM_MEM_DMA] = {"dmabufs"}, + [DRM_MEM_SAREA] = {"sareas"}, + [DRM_MEM_DRIVER] = {"driver"}, + [DRM_MEM_MAGIC] = {"magic"}, + [DRM_MEM_IOCTLS] = {"ioctltab"}, + [DRM_MEM_MAPS] = {"maplist"}, + [DRM_MEM_VMAS] = {"vmalist"}, + [DRM_MEM_BUFS] = {"buflist"}, + [DRM_MEM_SEGS] = {"seglist"}, + [DRM_MEM_PAGES] = {"pagelist"}, + [DRM_MEM_FILES] = {"files"}, + [DRM_MEM_QUEUES] = {"queues"}, + [DRM_MEM_CMDS] = {"commands"}, + [DRM_MEM_MAPPINGS] = {"mappings"}, + [DRM_MEM_BUFLISTS] = {"buflists"}, + [DRM_MEM_AGPLISTS] = {"agplist"}, + [DRM_MEM_SGLISTS] = {"sglist"}, + [DRM_MEM_TOTALAGP] = {"totalagp"}, + [DRM_MEM_BOUNDAGP] = {"boundagp"}, + [DRM_MEM_CTXBITMAP] = {"ctxbitmap"}, + [DRM_MEM_CTXLIST] = {"ctxlist"}, + [DRM_MEM_STUB] = {"stub"}, + {NULL, 0,} /* Last entry must be null */ }; -void DRM(mem_init)(void) -{ +void DRM(mem_init) (void) { drm_mem_stats_t *mem; - struct sysinfo si; + struct sysinfo si; for (mem = DRM(mem_stats); mem->name; ++mem) { - mem->succeed_count = 0; - mem->free_count = 0; - mem->fail_count = 0; + mem->succeed_count = 0; + mem->free_count = 0; + mem->fail_count = 0; mem->bytes_allocated = 0; - mem->bytes_freed = 0; + mem->bytes_freed = 0; } si_meminfo(&si); DRM(ram_available) = si.totalram; - DRM(ram_used) = 0; + DRM(ram_used) = 0; } /* drm_mem_info is called whenever a process reads /dev/drm/mem. */ -static int DRM(_mem_info)(char *buf, char **start, off_t offset, - int request, int *eof, void *data) -{ +static int DRM(_mem_info) (char *buf, char **start, off_t offset, + int request, int *eof, void *data) { drm_mem_stats_t *pt; - int len = 0; + int len = 0; if (offset > DRM_PROC_LIMIT) { *eof = 1; return 0; } - *eof = 0; + *eof = 0; *start = &buf[offset]; DRM_PROC_PRINT(" total counts " @@ -129,24 +128,23 @@ static int DRM(_mem_info)(char *buf, char **start, off_t offset, - (long)pt->bytes_freed); } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } -int DRM(mem_info)(char *buf, char **start, off_t offset, - int len, int *eof, void *data) -{ +int DRM(mem_info) (char *buf, char **start, off_t offset, + int len, int *eof, void *data) { int ret; spin_lock(&DRM(mem_lock)); - ret = DRM(_mem_info)(buf, start, offset, len, eof, data); + ret = DRM(_mem_info) (buf, start, offset, len, eof, data); spin_unlock(&DRM(mem_lock)); return ret; } -void *DRM(alloc)(size_t size, int area) -{ +void *DRM(alloc) (size_t size, int area) { void *pt; if (!size) { @@ -167,40 +165,40 @@ void *DRM(alloc)(size_t size, int area) return pt; } -void *DRM(calloc)(size_t nmemb, size_t size, int area) -{ +void *DRM(calloc) (size_t nmemb, size_t size, int area) { void *addr; - addr = DRM(alloc)(nmemb * size, area); + addr = DRM(alloc) (nmemb * size, area); if (addr != NULL) memset((void *)addr, 0, size * nmemb); return addr; } -void *DRM(realloc)(void *oldpt, size_t oldsize, size_t size, int area) -{ +void *DRM(realloc) (void *oldpt, size_t oldsize, size_t size, int area) { void *pt; - if (!(pt = DRM(alloc)(size, area))) return NULL; + if (!(pt = DRM(alloc) (size, area))) + return NULL; if (oldpt && oldsize) { memcpy(pt, oldpt, oldsize); - DRM(free)(oldpt, oldsize, area); + DRM(free) (oldpt, oldsize, area); } return pt; } -void DRM(free)(void *pt, size_t size, int area) -{ +void DRM(free) (void *pt, size_t size, int area) { int alloc_count; int free_count; - if (!pt) DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n"); - else kfree(pt); + if (!pt) + DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n"); + else + kfree(pt); spin_lock(&DRM(mem_lock)); DRM(mem_stats)[area].bytes_freed += size; - free_count = ++DRM(mem_stats)[area].free_count; - alloc_count = DRM(mem_stats)[area].succeed_count; + free_count = ++DRM(mem_stats)[area].free_count; + alloc_count = DRM(mem_stats)[area].succeed_count; spin_unlock(&DRM(mem_lock)); if (free_count > alloc_count) { DRM_MEM_ERROR(area, "Excess frees: %d frees, %d allocs\n", @@ -208,12 +206,11 @@ void DRM(free)(void *pt, size_t size, int area) } } -unsigned long DRM(alloc_pages)(int order, int area) -{ +unsigned long DRM(alloc_pages) (int order, int area) { unsigned long address; - unsigned long bytes = PAGE_SIZE << order; + unsigned long bytes = PAGE_SIZE << order; unsigned long addr; - unsigned int sz; + unsigned int sz; spin_lock(&DRM(mem_lock)); if ((DRM(ram_used) >> PAGE_SHIFT) @@ -233,48 +230,44 @@ unsigned long DRM(alloc_pages)(int order, int area) spin_lock(&DRM(mem_lock)); ++DRM(mem_stats)[area].succeed_count; DRM(mem_stats)[area].bytes_allocated += bytes; - DRM(ram_used) += bytes; + DRM(ram_used) += bytes; spin_unlock(&DRM(mem_lock)); - - /* Zero outside the lock */ + /* Zero outside the lock */ memset((void *)address, 0, bytes); - /* Reserve */ + /* Reserve */ for (addr = address, sz = bytes; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { SetPageReserved(virt_to_page(addr)); } return address; } -void DRM(free_pages)(unsigned long address, int order, int area) -{ +void DRM(free_pages) (unsigned long address, int order, int area) { unsigned long bytes = PAGE_SIZE << order; - int alloc_count; - int free_count; + int alloc_count; + int free_count; unsigned long addr; - unsigned int sz; + unsigned int sz; if (!address) { DRM_MEM_ERROR(area, "Attempt to free address 0\n"); } else { - /* Unreserve */ + /* Unreserve */ for (addr = address, sz = bytes; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { ClearPageReserved(virt_to_page(addr)); } free_pages(address, order); } spin_lock(&DRM(mem_lock)); - free_count = ++DRM(mem_stats)[area].free_count; - alloc_count = DRM(mem_stats)[area].succeed_count; + free_count = ++DRM(mem_stats)[area].free_count; + alloc_count = DRM(mem_stats)[area].succeed_count; DRM(mem_stats)[area].bytes_freed += bytes; - DRM(ram_used) -= bytes; + DRM(ram_used) -= bytes; spin_unlock(&DRM(mem_lock)); if (free_count > alloc_count) { DRM_MEM_ERROR(area, @@ -283,8 +276,8 @@ void DRM(free_pages)(unsigned long address, int order, int area) } } -void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev) -{ +void *DRM(ioremap) (unsigned long offset, unsigned long size, + drm_device_t * dev) { void *pt; if (!size) { @@ -306,8 +299,8 @@ void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev) return pt; } -void *DRM(ioremap_nocache)(unsigned long offset, unsigned long size, drm_device_t *dev) -{ +void *DRM(ioremap_nocache) (unsigned long offset, unsigned long size, + drm_device_t * dev) { void *pt; if (!size) { @@ -329,8 +322,7 @@ void *DRM(ioremap_nocache)(unsigned long offset, unsigned long size, drm_device_ return pt; } -void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev) -{ +void DRM(ioremapfree) (void *pt, unsigned long size, drm_device_t * dev) { int alloc_count; int free_count; @@ -342,8 +334,8 @@ void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev) spin_lock(&DRM(mem_lock)); DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_freed += size; - free_count = ++DRM(mem_stats)[DRM_MEM_MAPPINGS].free_count; - alloc_count = DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count; + free_count = ++DRM(mem_stats)[DRM_MEM_MAPPINGS].free_count; + alloc_count = DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count; spin_unlock(&DRM(mem_lock)); if (free_count > alloc_count) { DRM_MEM_ERROR(DRM_MEM_MAPPINGS, @@ -354,8 +346,7 @@ void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev) #if __OS_HAS_AGP -DRM_AGP_MEM *DRM(alloc_agp)(int pages, u32 type) -{ +DRM_AGP_MEM *DRM(alloc_agp) (int pages, u32 type) { DRM_AGP_MEM *handle; if (!pages) { @@ -363,11 +354,11 @@ DRM_AGP_MEM *DRM(alloc_agp)(int pages, u32 type) return NULL; } - if ((handle = DRM(agp_allocate_memory)(pages, type))) { + if ((handle = DRM(agp_allocate_memory) (pages, type))) { spin_lock(&DRM(mem_lock)); ++DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count; DRM(mem_stats)[DRM_MEM_TOTALAGP].bytes_allocated - += pages << PAGE_SHIFT; + += pages << PAGE_SHIFT; spin_unlock(&DRM(mem_lock)); return handle; } @@ -377,11 +368,10 @@ DRM_AGP_MEM *DRM(alloc_agp)(int pages, u32 type) return NULL; } -int DRM(free_agp)(DRM_AGP_MEM *handle, int pages) -{ - int alloc_count; - int free_count; - int retval = -EINVAL; +int DRM(free_agp) (DRM_AGP_MEM * handle, int pages) { + int alloc_count; + int free_count; + int retval = -EINVAL; if (!handle) { DRM_MEM_ERROR(DRM_MEM_TOTALAGP, @@ -389,12 +379,12 @@ int DRM(free_agp)(DRM_AGP_MEM *handle, int pages) return retval; } - if (DRM(agp_free_memory)(handle)) { + if (DRM(agp_free_memory) (handle)) { spin_lock(&DRM(mem_lock)); - free_count = ++DRM(mem_stats)[DRM_MEM_TOTALAGP].free_count; - alloc_count = DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count; + free_count = ++DRM(mem_stats)[DRM_MEM_TOTALAGP].free_count; + alloc_count = DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count; DRM(mem_stats)[DRM_MEM_TOTALAGP].bytes_freed - += pages << PAGE_SHIFT; + += pages << PAGE_SHIFT; spin_unlock(&DRM(mem_lock)); if (free_count > alloc_count) { DRM_MEM_ERROR(DRM_MEM_TOTALAGP, @@ -406,8 +396,7 @@ int DRM(free_agp)(DRM_AGP_MEM *handle, int pages) return retval; } -int DRM(bind_agp)(DRM_AGP_MEM *handle, unsigned int start) -{ +int DRM(bind_agp) (DRM_AGP_MEM * handle, unsigned int start) { int retcode = -EINVAL; if (!handle) { @@ -416,11 +405,11 @@ int DRM(bind_agp)(DRM_AGP_MEM *handle, unsigned int start) return retcode; } - if (!(retcode = DRM(agp_bind_memory)(handle, start))) { + if (!(retcode = DRM(agp_bind_memory) (handle, start))) { spin_lock(&DRM(mem_lock)); ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].succeed_count; DRM(mem_stats)[DRM_MEM_BOUNDAGP].bytes_allocated - += handle->page_count << PAGE_SHIFT; + += handle->page_count << PAGE_SHIFT; spin_unlock(&DRM(mem_lock)); return retcode; } @@ -430,8 +419,7 @@ int DRM(bind_agp)(DRM_AGP_MEM *handle, unsigned int start) return retcode; } -int DRM(unbind_agp)(DRM_AGP_MEM *handle) -{ +int DRM(unbind_agp) (DRM_AGP_MEM * handle) { int alloc_count; int free_count; int retcode = -EINVAL; @@ -442,12 +430,13 @@ int DRM(unbind_agp)(DRM_AGP_MEM *handle) return retcode; } - if ((retcode = DRM(agp_unbind_memory)(handle))) return retcode; + if ((retcode = DRM(agp_unbind_memory) (handle))) + return retcode; spin_lock(&DRM(mem_lock)); - free_count = ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].free_count; + free_count = ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].free_count; alloc_count = DRM(mem_stats)[DRM_MEM_BOUNDAGP].succeed_count; DRM(mem_stats)[DRM_MEM_BOUNDAGP].bytes_freed - += handle->page_count << PAGE_SHIFT; + += handle->page_count << PAGE_SHIFT; spin_unlock(&DRM(mem_lock)); if (free_count > alloc_count) { DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, diff --git a/linux-core/drm_os_linux.h b/linux-core/drm_os_linux.h index c3f8ec0e..836144d1 100644 --- a/linux-core/drm_os_linux.h +++ b/linux-core/drm_os_linux.h @@ -3,7 +3,6 @@ * OS abstraction macros. */ - #include /* For task queue support */ #include @@ -15,7 +14,7 @@ /** Current process ID */ #define DRM_CURRENTPID current->pid #define DRM_UDELAY(d) udelay(d) -#if LINUX_VERSION_CODE <= 0x020608 /* KERNEL_VERSION(2,6,8) */ +#if LINUX_VERSION_CODE <= 0x020608 /* KERNEL_VERSION(2,6,8) */ /** Read a byte from a MMIO region */ #define DRM_READ8(map, offset) readb(((unsigned long)(map)->handle) + (offset)) /** Read a word from a MMIO region */ @@ -57,8 +56,8 @@ /** backwards compatibility with old irq return values */ #ifndef IRQ_HANDLED typedef void irqreturn_t; -#define IRQ_HANDLED /* nothing */ -#define IRQ_NONE /* nothing */ +#define IRQ_HANDLED /* nothing */ +#define IRQ_NONE /* nothing */ #endif /** AGP types */ @@ -81,17 +80,17 @@ struct no_agp_kern { #endif #if !(__OS_HAS_MTRR) -static __inline__ int mtrr_add (unsigned long base, unsigned long size, - unsigned int type, char increment) +static __inline__ int mtrr_add(unsigned long base, unsigned long size, + unsigned int type, char increment) { return -ENODEV; } -static __inline__ int mtrr_del (int reg, unsigned long base, - unsigned long size) +static __inline__ int mtrr_del(int reg, unsigned long base, unsigned long size) { return -ENODEV; } + #define MTRR_TYPE_WRCOMB 1 #endif @@ -124,10 +123,9 @@ static __inline__ int mtrr_del (int reg, unsigned long base, #define DRM_PUT_USER_UNCHECKED(uaddr, val) \ __put_user(val, uaddr) - #define DRM_GET_PRIV_WITH_RETURN(_priv, _filp) _priv = _filp->private_data -/** +/** * Get the pointer to the SAREA. * * Searches the SAREA on the mapping lists and points drm_device::sarea to it. @@ -171,7 +169,5 @@ do { \ remove_wait_queue(&(queue), &entry); \ } while (0) - #define DRM_WAKEUP( queue ) wake_up_interruptible( queue ) #define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue ) - diff --git a/linux-core/drm_pci.c b/linux-core/drm_pci.c index ba46f4fa..bde5e07e 100644 --- a/linux-core/drm_pci.c +++ b/linux-core/drm_pci.c @@ -2,14 +2,14 @@ /** * \file drm_pci.h * \brief Functions and ioctls to manage PCI memory - * + * * \warning These interfaces aren't stable yet. - * + * * \todo Implement the remaining ioctl's for the PCI pools. * \todo Add support to map these buffers. * \todo The wrappers here are so thin that they would be better off inlined.. * - * \author Jos�Fonseca + * \author Jose Fonseca * \author Leif Delgass */ @@ -37,7 +37,6 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - #include #include "drmP.h" @@ -45,13 +44,11 @@ /** \name PCI memory */ /*@{*/ - /** * \brief Allocate a PCI consistent memory block, for DMA. */ -void * -drm_pci_alloc(drm_device_t *dev, size_t size, size_t align, - dma_addr_t maxaddr, dma_addr_t *busaddr) +void *drm_pci_alloc(drm_device_t * dev, size_t size, size_t align, + dma_addr_t maxaddr, dma_addr_t * busaddr) { void *address; #if 0 @@ -70,19 +67,19 @@ drm_pci_alloc(drm_device_t *dev, size_t size, size_t align, spin_unlock(&drm_mem_lock); #endif - /* pci_alloc_consistent only guarantees alignment to the smallest + /* pci_alloc_consistent only guarantees alignment to the smallest * PAGE_SIZE order which is greater than or equal to the requested size. * Return NULL here for now to make sure nobody tries for larger alignment */ if (align > size) return NULL; - if (pci_set_dma_mask( dev->pdev, maxaddr ) != 0) { - DRM_ERROR( "Setting pci dma mask failed\n" ); + if (pci_set_dma_mask(dev->pdev, maxaddr) != 0) { + DRM_ERROR("Setting pci dma mask failed\n"); return NULL; } - address = pci_alloc_consistent( dev->pdev, size, busaddr ); + address = pci_alloc_consistent(dev->pdev, size, busaddr); #if DRM_DEBUG_MEMORY if (address == NULL) { @@ -95,7 +92,7 @@ drm_pci_alloc(drm_device_t *dev, size_t size, size_t align, spin_lock(&drm_mem_lock); ++drm_mem_stats[area].succeed_count; drm_mem_stats[area].bytes_allocated += size; - drm_ram_used += size; + drm_ram_used += size; spin_unlock(&drm_mem_lock); #else if (address == NULL) @@ -106,10 +103,9 @@ drm_pci_alloc(drm_device_t *dev, size_t size, size_t align, #if 0 /* XXX - Is virt_to_page() legal for consistent mem? */ - /* Reserve */ + /* Reserve */ for (addr = (unsigned long)address, sz = size; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { SetPageReserved(virt_to_page(addr)); } #endif @@ -122,7 +118,7 @@ EXPORT_SYMBOL(drm_pci_alloc); * \brief Free a PCI consistent memory block. */ void -drm_pci_free(drm_device_t *dev, size_t size, void *vaddr, dma_addr_t busaddr) +drm_pci_free(drm_device_t * dev, size_t size, void *vaddr, dma_addr_t busaddr) { #if 0 unsigned long addr; @@ -141,22 +137,21 @@ drm_pci_free(drm_device_t *dev, size_t size, void *vaddr, dma_addr_t busaddr) } else { #if 0 /* XXX - Is virt_to_page() legal for consistent mem? */ - /* Unreserve */ + /* Unreserve */ for (addr = (unsigned long)vaddr, sz = size; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { ClearPageReserved(virt_to_page(addr)); } #endif - pci_free_consistent( dev->pdev, size, vaddr, busaddr ); + pci_free_consistent(dev->pdev, size, vaddr, busaddr); } #if DRM_DEBUG_MEMORY spin_lock(&drm_mem_lock); - free_count = ++drm_mem_stats[area].free_count; - alloc_count = drm_mem_stats[area].succeed_count; + free_count = ++drm_mem_stats[area].free_count; + alloc_count = drm_mem_stats[area].succeed_count; drm_mem_stats[area].bytes_freed += size; - drm_ram_used -= size; + drm_ram_used -= size; spin_unlock(&drm_mem_lock); if (free_count > alloc_count) { DRM_MEM_ERROR(area, diff --git a/linux-core/drm_proc.c b/linux-core/drm_proc.c index 7f342075..0f2bd480 100644 --- a/linux-core/drm_proc.c +++ b/linux-core/drm_proc.c @@ -1,5 +1,5 @@ /** - * \file drm_proc.h + * \file drm_proc.h * /proc support for DRM * * \author Rickard E. (Rik) Faith @@ -39,19 +39,19 @@ #include "drmP.h" -static int drm_name_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); -static int drm_vm_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); -static int drm_clients_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); -static int drm_queues_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); -static int drm_bufs_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); +static int drm_name_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_vm_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_clients_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_queues_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_bufs_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); #if DRM_DEBUG_CODE -static int drm_vma_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); +static int drm_vma_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); #endif /** @@ -59,18 +59,19 @@ static int drm_vma_info(char *buf, char **start, off_t offset, */ struct drm_proc_list { const char *name; /**< file name */ - int (*f)(char *, char **, off_t, int, int *, void *); /**< proc callback*/ + int (*f) (char *, char **, off_t, int, int *, void *); /**< proc callback*/ } drm_proc_list[] = { - { "name", drm_name_info }, - { "mem", drm_mem_info }, - { "vm", drm_vm_info }, - { "clients", drm_clients_info }, - { "queues", drm_queues_info }, - { "bufs", drm_bufs_info }, + {"name", drm_name_info}, + {"mem", drm_mem_info}, + {"vm", drm_vm_info}, + {"clients", drm_clients_info}, + {"queues", drm_queues_info}, + {"bufs", drm_bufs_info}, #if DRM_DEBUG_CODE - { "vma", drm_vma_info }, + {"vma", drm_vma_info}, #endif }; + #define DRM_PROC_ENTRIES (sizeof(drm_proc_list)/sizeof(drm_proc_list[0])) /** @@ -81,18 +82,17 @@ struct drm_proc_list { * \param root DRI proc dir entry. * \param dev_root resulting DRI device proc dir entry. * \return root entry pointer on success, or NULL on failure. - * + * * Create the DRI proc root entry "/proc/dri", the device proc root entry * "/proc/dri/%minor%/", and each entry in proc_list as * "/proc/dri/%minor%/%name%". */ -int drm_proc_init(drm_device_t *dev, int minor, - struct proc_dir_entry *root, - struct proc_dir_entry **dev_root) +int drm_proc_init(drm_device_t * dev, int minor, + struct proc_dir_entry *root, struct proc_dir_entry **dev_root) { struct proc_dir_entry *ent; - int i, j; - char name[64]; + int i, j; + char name[64]; sprintf(name, "%d", minor); *dev_root = create_proc_entry(name, S_IFDIR, root); @@ -103,7 +103,7 @@ int drm_proc_init(drm_device_t *dev, int minor, for (i = 0; i < DRM_PROC_ENTRIES; i++) { ent = create_proc_entry(drm_proc_list[i].name, - S_IFREG|S_IRUGO, *dev_root); + S_IFREG | S_IRUGO, *dev_root); if (!ent) { DRM_ERROR("Cannot create /proc/dri/%s/%s\n", name, drm_proc_list[i].name); @@ -114,12 +114,11 @@ int drm_proc_init(drm_device_t *dev, int minor, return -1; } ent->read_proc = drm_proc_list[i].f; - ent->data = dev; + ent->data = dev; } return 0; } - /** * Cleanup the proc filesystem resources. * @@ -131,12 +130,13 @@ int drm_proc_init(drm_device_t *dev, int minor, * Remove all proc entries created by proc_init(). */ int drm_proc_cleanup(int minor, struct proc_dir_entry *root, - struct proc_dir_entry *dev_root) + struct proc_dir_entry *dev_root) { - int i; + int i; char name[64]; - if (!root || !dev_root) return 0; + if (!root || !dev_root) + return 0; for (i = 0; i < DRM_PROC_ENTRIES; i++) remove_proc_entry(drm_proc_list[i].name, dev_root); @@ -148,7 +148,7 @@ int drm_proc_cleanup(int minor, struct proc_dir_entry *root, /** * Called when "/proc/dri/.../name" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -156,14 +156,14 @@ int drm_proc_cleanup(int minor, struct proc_dir_entry *root, * \param eof whether there is no more data to return. * \param data private data. * \return number of written bytes. - * + * * Prints the device name together with the bus id if available. */ static int drm_name_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; if (offset > DRM_PROC_LIMIT) { *eof = 1; @@ -171,23 +171,26 @@ static int drm_name_info(char *buf, char **start, off_t offset, int request, } *start = &buf[offset]; - *eof = 0; + *eof = 0; if (dev->unique) { DRM_PROC_PRINT("%s 0x%lx %s\n", - dev->name, (long)old_encode_dev(dev->device), dev->unique); + dev->name, (long)old_encode_dev(dev->device), + dev->unique); } else { - DRM_PROC_PRINT("%s 0x%lx\n", dev->name, (long)old_encode_dev(dev->device)); + DRM_PROC_PRINT("%s 0x%lx\n", dev->name, + (long)old_encode_dev(dev->device)); } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } /** * Called when "/proc/dri/.../vm" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -195,24 +198,24 @@ static int drm_name_info(char *buf, char **start, off_t offset, int request, * \param eof whether there is no more data to return. * \param data private data. * \return number of written bytes. - * + * * Prints information about all mappings in drm_device::maplist. */ static int drm__vm_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; - drm_map_t *map; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; + drm_map_t *map; drm_map_list_t *r_list; struct list_head *list; - /* Hardcoded from _DRM_FRAME_BUFFER, - _DRM_REGISTERS, _DRM_SHM, _DRM_AGP, and - _DRM_SCATTER_GATHER. */ - const char *types[] = { "FB", "REG", "SHM", "AGP", "SG" }; - const char *type; - int i; + /* Hardcoded from _DRM_FRAME_BUFFER, + _DRM_REGISTERS, _DRM_SHM, _DRM_AGP, and + _DRM_SCATTER_GATHER. */ + const char *types[] = { "FB", "REG", "SHM", "AGP", "SG" }; + const char *type; + int i; if (offset > DRM_PROC_LIMIT) { *eof = 1; @@ -220,33 +223,36 @@ static int drm__vm_info(char *buf, char **start, off_t offset, int request, } *start = &buf[offset]; - *eof = 0; + *eof = 0; DRM_PROC_PRINT("slot offset size type flags " "address mtrr\n\n"); i = 0; - if (dev->maplist != NULL) list_for_each(list, &dev->maplist->head) { + if (dev->maplist != NULL) + list_for_each(list, &dev->maplist->head) { r_list = list_entry(list, drm_map_list_t, head); map = r_list->map; - if(!map) continue; - if (map->type < 0 || map->type > 4) type = "??"; - else type = types[map->type]; + if (!map) + continue; + if (map->type < 0 || map->type > 4) + type = "??"; + else + type = types[map->type]; DRM_PROC_PRINT("%4d 0x%08lx 0x%08lx %4.4s 0x%02x 0x%08lx ", i, map->offset, map->size, - type, - map->flags, - (unsigned long)map->handle); + type, map->flags, (unsigned long)map->handle); if (map->mtrr < 0) { DRM_PROC_PRINT("none\n"); } else { DRM_PROC_PRINT("%4d\n", map->mtrr); } i++; - } + } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } @@ -255,10 +261,10 @@ static int drm__vm_info(char *buf, char **start, off_t offset, int request, * Simply calls _vm_info() while holding the drm_device::struct_sem lock. */ static int drm_vm_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int ret; + drm_device_t *dev = (drm_device_t *) data; + int ret; down(&dev->struct_sem); ret = drm__vm_info(buf, start, offset, request, eof, data); @@ -268,7 +274,7 @@ static int drm_vm_info(char *buf, char **start, off_t offset, int request, /** * Called when "/proc/dri/.../queues" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -278,12 +284,12 @@ static int drm_vm_info(char *buf, char **start, off_t offset, int request, * \return number of written bytes. */ static int drm__queues_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data) + int request, int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; - int i; - drm_queue_t *q; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; + int i; + drm_queue_t *q; if (offset > DRM_PROC_LIMIT) { *eof = 1; @@ -291,7 +297,7 @@ static int drm__queues_info(char *buf, char **start, off_t offset, } *start = &buf[offset]; - *eof = 0; + *eof = 0; DRM_PROC_PRINT(" ctx/flags use fin" " blk/rw/rwf wait flushed queued" @@ -309,14 +315,17 @@ static int drm__queues_info(char *buf, char **start, off_t offset, atomic_read(&q->block_count), atomic_read(&q->block_read) ? 'r' : '-', atomic_read(&q->block_write) ? 'w' : '-', - waitqueue_active(&q->read_queue) ? 'r':'-', - waitqueue_active(&q->write_queue) ? 'w':'-', - waitqueue_active(&q->flush_queue) ? 'f':'-', + waitqueue_active(&q->read_queue) ? 'r' : '-', + waitqueue_active(&q-> + write_queue) ? 'w' : '-', + waitqueue_active(&q-> + flush_queue) ? 'f' : '-', DRM_BUFCOUNT(&q->waitlist)); atomic_dec(&q->use_count); } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } @@ -325,10 +334,10 @@ static int drm__queues_info(char *buf, char **start, off_t offset, * Simply calls _queues_info() while holding the drm_device::struct_sem lock. */ static int drm_queues_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int ret; + drm_device_t *dev = (drm_device_t *) data; + int ret; down(&dev->struct_sem); ret = drm__queues_info(buf, start, offset, request, eof, data); @@ -338,7 +347,7 @@ static int drm_queues_info(char *buf, char **start, off_t offset, int request, /** * Called when "/proc/dri/.../bufs" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -348,12 +357,12 @@ static int drm_queues_info(char *buf, char **start, off_t offset, int request, * \return number of written bytes. */ static int drm__bufs_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; drm_device_dma_t *dma = dev->dma; - int i; + int i; if (!dma || offset > DRM_PROC_LIMIT) { *eof = 1; @@ -361,7 +370,7 @@ static int drm__bufs_info(char *buf, char **start, off_t offset, int request, } *start = &buf[offset]; - *eof = 0; + *eof = 0; DRM_PROC_PRINT(" o size count free segs pages kB\n\n"); for (i = 0; i <= DRM_MAX_ORDER; i++) { @@ -374,19 +383,21 @@ static int drm__bufs_info(char *buf, char **start, off_t offset, int request, .freelist.count), dma->bufs[i].seg_count, dma->bufs[i].seg_count - *(1 << dma->bufs[i].page_order), + * (1 << dma->bufs[i].page_order), (dma->bufs[i].seg_count * (1 << dma->bufs[i].page_order)) * PAGE_SIZE / 1024); } DRM_PROC_PRINT("\n"); for (i = 0; i < dma->buf_count; i++) { - if (i && !(i%32)) DRM_PROC_PRINT("\n"); + if (i && !(i % 32)) + DRM_PROC_PRINT("\n"); DRM_PROC_PRINT(" %d", dma->buflist[i]->list); } DRM_PROC_PRINT("\n"); - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } @@ -395,10 +406,10 @@ static int drm__bufs_info(char *buf, char **start, off_t offset, int request, * Simply calls _bufs_info() while holding the drm_device::struct_sem lock. */ static int drm_bufs_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int ret; + drm_device_t *dev = (drm_device_t *) data; + int ret; down(&dev->struct_sem); ret = drm__bufs_info(buf, start, offset, request, eof, data); @@ -408,7 +419,7 @@ static int drm_bufs_info(char *buf, char **start, off_t offset, int request, /** * Called when "/proc/dri/.../clients" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -418,11 +429,11 @@ static int drm_bufs_info(char *buf, char **start, off_t offset, int request, * \return number of written bytes. */ static int drm__clients_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data) + int request, int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; - drm_file_t *priv; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; + drm_file_t *priv; if (offset > DRM_PROC_LIMIT) { *eof = 1; @@ -430,7 +441,7 @@ static int drm__clients_info(char *buf, char **start, off_t offset, } *start = &buf[offset]; - *eof = 0; + *eof = 0; DRM_PROC_PRINT("a dev pid uid magic ioctls\n\n"); for (priv = dev->file_first; priv; priv = priv->next) { @@ -438,12 +449,11 @@ static int drm__clients_info(char *buf, char **start, off_t offset, priv->authenticated ? 'y' : 'n', priv->minor, priv->pid, - priv->uid, - priv->magic, - priv->ioctl_count); + priv->uid, priv->magic, priv->ioctl_count); } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } @@ -452,10 +462,10 @@ static int drm__clients_info(char *buf, char **start, off_t offset, * Simply calls _clients_info() while holding the drm_device::struct_sem lock. */ static int drm_clients_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data) + int request, int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int ret; + drm_device_t *dev = (drm_device_t *) data; + int ret; down(&dev->struct_sem); ret = drm__clients_info(buf, start, offset, request, eof, data); @@ -466,14 +476,14 @@ static int drm_clients_info(char *buf, char **start, off_t offset, #if DRM_DEBUG_CODE static int drm__vma_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; - drm_vma_entry_t *pt; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; + drm_vma_entry_t *pt; struct vm_area_struct *vma; #if defined(__i386__) - unsigned int pgprot; + unsigned int pgprot; #endif if (offset > DRM_PROC_LIMIT) { @@ -482,51 +492,53 @@ static int drm__vma_info(char *buf, char **start, off_t offset, int request, } *start = &buf[offset]; - *eof = 0; + *eof = 0; DRM_PROC_PRINT("vma use count: %d, high_memory = %p, 0x%08lx\n", atomic_read(&dev->vma_count), high_memory, virt_to_phys(high_memory)); for (pt = dev->vmalist; pt; pt = pt->next) { - if (!(vma = pt->vma)) continue; + if (!(vma = pt->vma)) + continue; DRM_PROC_PRINT("\n%5d 0x%08lx-0x%08lx %c%c%c%c%c%c 0x%08lx", pt->pid, vma->vm_start, vma->vm_end, - vma->vm_flags & VM_READ ? 'r' : '-', - vma->vm_flags & VM_WRITE ? 'w' : '-', - vma->vm_flags & VM_EXEC ? 'x' : '-', + vma->vm_flags & VM_READ ? 'r' : '-', + vma->vm_flags & VM_WRITE ? 'w' : '-', + vma->vm_flags & VM_EXEC ? 'x' : '-', vma->vm_flags & VM_MAYSHARE ? 's' : 'p', - vma->vm_flags & VM_LOCKED ? 'l' : '-', - vma->vm_flags & VM_IO ? 'i' : '-', + vma->vm_flags & VM_LOCKED ? 'l' : '-', + vma->vm_flags & VM_IO ? 'i' : '-', VM_OFFSET(vma)); #if defined(__i386__) pgprot = pgprot_val(vma->vm_page_prot); DRM_PROC_PRINT(" %c%c%c%c%c%c%c%c%c", - pgprot & _PAGE_PRESENT ? 'p' : '-', - pgprot & _PAGE_RW ? 'w' : 'r', - pgprot & _PAGE_USER ? 'u' : 's', - pgprot & _PAGE_PWT ? 't' : 'b', - pgprot & _PAGE_PCD ? 'u' : 'c', + pgprot & _PAGE_PRESENT ? 'p' : '-', + pgprot & _PAGE_RW ? 'w' : 'r', + pgprot & _PAGE_USER ? 'u' : 's', + pgprot & _PAGE_PWT ? 't' : 'b', + pgprot & _PAGE_PCD ? 'u' : 'c', pgprot & _PAGE_ACCESSED ? 'a' : '-', - pgprot & _PAGE_DIRTY ? 'd' : '-', - pgprot & _PAGE_PSE ? 'm' : 'k', - pgprot & _PAGE_GLOBAL ? 'g' : 'l' ); + pgprot & _PAGE_DIRTY ? 'd' : '-', + pgprot & _PAGE_PSE ? 'm' : 'k', + pgprot & _PAGE_GLOBAL ? 'g' : 'l'); #endif DRM_PROC_PRINT("\n"); } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } static int drm_vma_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int ret; + drm_device_t *dev = (drm_device_t *) data; + int ret; down(&dev->struct_sem); ret = drm__vma_info(buf, start, offset, request, eof, data); @@ -534,5 +546,3 @@ static int drm_vma_info(char *buf, char **start, off_t offset, int request, return ret; } #endif - - diff --git a/linux-core/drm_scatter.c b/linux-core/drm_scatter.c index 5611bada..c5b1aee4 100644 --- a/linux-core/drm_scatter.c +++ b/linux-core/drm_scatter.c @@ -1,5 +1,5 @@ /** - * \file drm_scatter.h + * \file drm_scatter.h * IOCTLs to manage scatter/gather memory * * \author Gareth Hughes @@ -33,36 +33,33 @@ #include #include + #include "drmP.h" #define DEBUG_SCATTER 0 -void drm_sg_cleanup( drm_sg_mem_t *entry ) +void drm_sg_cleanup(drm_sg_mem_t * entry) { struct page *page; int i; - for ( i = 0 ; i < entry->pages ; i++ ) { + for (i = 0; i < entry->pages; i++) { page = entry->pagelist[i]; - if ( page ) - ClearPageReserved( page ); + if (page) + ClearPageReserved(page); } - vfree( entry->virtual ); - - drm_free( entry->busaddr, - entry->pages * sizeof(*entry->busaddr), - DRM_MEM_PAGES ); - drm_free( entry->pagelist, - entry->pages * sizeof(*entry->pagelist), - DRM_MEM_PAGES ); - drm_free( entry, - sizeof(*entry), - DRM_MEM_SGLISTS ); + vfree(entry->virtual); + + drm_free(entry->busaddr, + entry->pages * sizeof(*entry->busaddr), DRM_MEM_PAGES); + drm_free(entry->pagelist, + entry->pages * sizeof(*entry->pagelist), DRM_MEM_PAGES); + drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS); } -int drm_sg_alloc( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_sg_alloc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -71,74 +68,69 @@ int drm_sg_alloc( struct inode *inode, struct file *filp, drm_sg_mem_t *entry; unsigned long pages, i, j; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); if (!drm_core_check_feature(dev, DRIVER_SG)) return -EINVAL; - if ( dev->sg ) + if (dev->sg) return -EINVAL; - if ( copy_from_user( &request, argp, sizeof(request) ) ) + if (copy_from_user(&request, argp, sizeof(request))) return -EFAULT; - entry = drm_alloc( sizeof(*entry), DRM_MEM_SGLISTS ); - if ( !entry ) + entry = drm_alloc(sizeof(*entry), DRM_MEM_SGLISTS); + if (!entry) return -ENOMEM; - memset( entry, 0, sizeof(*entry) ); + memset(entry, 0, sizeof(*entry)); pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE; - DRM_DEBUG( "sg size=%ld pages=%ld\n", request.size, pages ); + DRM_DEBUG("sg size=%ld pages=%ld\n", request.size, pages); entry->pages = pages; - entry->pagelist = drm_alloc( pages * sizeof(*entry->pagelist), - DRM_MEM_PAGES ); - if ( !entry->pagelist ) { - drm_free( entry, sizeof(*entry), DRM_MEM_SGLISTS ); + entry->pagelist = drm_alloc(pages * sizeof(*entry->pagelist), + DRM_MEM_PAGES); + if (!entry->pagelist) { + drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS); return -ENOMEM; } memset(entry->pagelist, 0, pages * sizeof(*entry->pagelist)); - entry->busaddr = drm_alloc( pages * sizeof(*entry->busaddr), - DRM_MEM_PAGES ); - if ( !entry->busaddr ) { - drm_free( entry->pagelist, - entry->pages * sizeof(*entry->pagelist), - DRM_MEM_PAGES ); - drm_free( entry, - sizeof(*entry), - DRM_MEM_SGLISTS ); + entry->busaddr = drm_alloc(pages * sizeof(*entry->busaddr), + DRM_MEM_PAGES); + if (!entry->busaddr) { + drm_free(entry->pagelist, + entry->pages * sizeof(*entry->pagelist), + DRM_MEM_PAGES); + drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS); return -ENOMEM; } - memset( (void *)entry->busaddr, 0, pages * sizeof(*entry->busaddr) ); - - entry->virtual = vmalloc_32( pages << PAGE_SHIFT ); - if ( !entry->virtual ) { - drm_free( entry->busaddr, - entry->pages * sizeof(*entry->busaddr), - DRM_MEM_PAGES ); - drm_free( entry->pagelist, - entry->pages * sizeof(*entry->pagelist), - DRM_MEM_PAGES ); - drm_free( entry, - sizeof(*entry), - DRM_MEM_SGLISTS ); + memset((void *)entry->busaddr, 0, pages * sizeof(*entry->busaddr)); + + entry->virtual = vmalloc_32(pages << PAGE_SHIFT); + if (!entry->virtual) { + drm_free(entry->busaddr, + entry->pages * sizeof(*entry->busaddr), DRM_MEM_PAGES); + drm_free(entry->pagelist, + entry->pages * sizeof(*entry->pagelist), + DRM_MEM_PAGES); + drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS); return -ENOMEM; } /* This also forces the mapping of COW pages, so our page list * will be valid. Please don't remove it... */ - memset( entry->virtual, 0, pages << PAGE_SHIFT ); + memset(entry->virtual, 0, pages << PAGE_SHIFT); entry->handle = (unsigned long)entry->virtual; - DRM_DEBUG( "sg alloc handle = %08lx\n", entry->handle ); - DRM_DEBUG( "sg alloc virtual = %p\n", entry->virtual ); + DRM_DEBUG("sg alloc handle = %08lx\n", entry->handle); + DRM_DEBUG("sg alloc virtual = %p\n", entry->virtual); - for ( i = entry->handle, j = 0 ; j < pages ; i += PAGE_SIZE, j++ ) { + for (i = entry->handle, j = 0; j < pages; i += PAGE_SIZE, j++) { entry->pagelist[j] = vmalloc_to_page((void *)i); if (!entry->pagelist[j]) goto failed; @@ -147,8 +139,8 @@ int drm_sg_alloc( struct inode *inode, struct file *filp, request.handle = entry->handle; - if ( copy_to_user( argp, &request, sizeof(request) ) ) { - drm_sg_cleanup( entry ); + if (copy_to_user(argp, &request, sizeof(request))) { + drm_sg_cleanup(entry); return -EFAULT; } @@ -159,50 +151,50 @@ int drm_sg_alloc( struct inode *inode, struct file *filp, * versa. */ { - int error = 0; + int error = 0; - for ( i = 0 ; i < pages ; i++ ) { - unsigned long *tmp; + for (i = 0; i < pages; i++) { + unsigned long *tmp; - tmp = page_address( entry->pagelist[i] ); - for ( j = 0 ; - j < PAGE_SIZE / sizeof(unsigned long) ; - j++, tmp++ ) { - *tmp = 0xcafebabe; - } - tmp = (unsigned long *)((u8 *)entry->virtual + - (PAGE_SIZE * i)); - for( j = 0 ; - j < PAGE_SIZE / sizeof(unsigned long) ; - j++, tmp++ ) { - if ( *tmp != 0xcafebabe && error == 0 ) { - error = 1; - DRM_ERROR( "Scatter allocation error, " - "pagelist does not match " - "virtual mapping\n" ); + tmp = page_address(entry->pagelist[i]); + for (j = 0; + j < PAGE_SIZE / sizeof(unsigned long); + j++, tmp++) { + *tmp = 0xcafebabe; + } + tmp = (unsigned long *)((u8 *) entry->virtual + + (PAGE_SIZE * i)); + for (j = 0; + j < PAGE_SIZE / sizeof(unsigned long); + j++, tmp++) { + if (*tmp != 0xcafebabe && error == 0) { + error = 1; + DRM_ERROR("Scatter allocation error, " + "pagelist does not match " + "virtual mapping\n"); + } + } + tmp = page_address(entry->pagelist[i]); + for (j = 0; + j < PAGE_SIZE / sizeof(unsigned long); + j++, tmp++) { + *tmp = 0; } } - tmp = page_address( entry->pagelist[i] ); - for(j = 0 ; - j < PAGE_SIZE / sizeof(unsigned long) ; - j++, tmp++) { - *tmp = 0; - } - } - if (error == 0) - DRM_ERROR( "Scatter allocation matches pagelist\n" ); + if (error == 0) + DRM_ERROR("Scatter allocation matches pagelist\n"); } #endif return 0; - failed: - drm_sg_cleanup( entry ); + failed: + drm_sg_cleanup(entry); return -ENOMEM; } -int drm_sg_free( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_sg_free(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -212,20 +204,20 @@ int drm_sg_free( struct inode *inode, struct file *filp, if (!drm_core_check_feature(dev, DRIVER_SG)) return -EINVAL; - if ( copy_from_user( &request, - (drm_scatter_gather_t __user *)arg, - sizeof(request) ) ) + if (copy_from_user(&request, + (drm_scatter_gather_t __user *) arg, + sizeof(request))) return -EFAULT; entry = dev->sg; dev->sg = NULL; - if ( !entry || entry->handle != request.handle ) + if (!entry || entry->handle != request.handle) return -EINVAL; - DRM_DEBUG( "sg free virtual = %p\n", entry->virtual ); + DRM_DEBUG("sg free virtual = %p\n", entry->virtual); - drm_sg_cleanup( entry ); + drm_sg_cleanup(entry); return 0; } diff --git a/linux-core/drm_stub.c b/linux-core/drm_stub.c index a213134e..6f4753dd 100644 --- a/linux-core/drm_stub.c +++ b/linux-core/drm_stub.c @@ -32,14 +32,15 @@ */ #include + #include "drmP.h" #include "drm_core.h" unsigned int cards_limit = 16; /* Enough for one machine */ unsigned int debug = 0; /* 1 to enable debug output */ -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); MODULE_PARM_DESC(cards_limit, "Maximum number of graphics cards"); MODULE_PARM_DESC(debug, "Enable debug output"); @@ -51,20 +52,22 @@ drm_minor_t *drm_minors; struct drm_sysfs_class *drm_class; struct proc_dir_entry *drm_proc_root; -static int fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct pci_device_id *ent, struct drm_driver_fn *driver_fn) +static int fill_in_dev(drm_device_t * dev, struct pci_dev *pdev, + const struct pci_device_id *ent, + struct drm_driver_fn *driver_fn) { int retcode; dev->count_lock = SPIN_LOCK_UNLOCKED; - init_timer( &dev->timer ); - sema_init( &dev->struct_sem, 1 ); - sema_init( &dev->ctxlist_sem, 1 ); + init_timer(&dev->timer); + sema_init(&dev->struct_sem, 1); + sema_init(&dev->ctxlist_sem, 1); - dev->name = DRIVER_NAME; - dev->pdev = pdev; + dev->name = DRIVER_NAME; + dev->pdev = pdev; #ifdef __alpha__ - dev->hose = pdev->sysdata; + dev->hose = pdev->sysdata; dev->pci_domain = dev->hose->bus->number; #else dev->pci_domain = 0; @@ -75,7 +78,8 @@ static int fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct pci dev->irq = pdev->irq; dev->maplist = drm_calloc(1, sizeof(*dev->maplist), DRM_MEM_MAPS); - if(dev->maplist == NULL) return -ENOMEM; + if (dev->maplist == NULL) + return -ENOMEM; INIT_LIST_HEAD(&dev->maplist->head); /* the DRM has 6 counters */ @@ -95,29 +99,29 @@ static int fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct pci if (drm_core_has_AGP(dev)) { dev->agp = drm_agp_init(); - if (drm_core_check_feature(dev, DRIVER_REQUIRE_AGP) && (dev->agp == NULL)) { - DRM_ERROR( "Cannot initialize the agpgart module.\n" ); + if (drm_core_check_feature(dev, DRIVER_REQUIRE_AGP) + && (dev->agp == NULL)) { + DRM_ERROR("Cannot initialize the agpgart module.\n"); retcode = -EINVAL; goto error_out_unreg; } - if (drm_core_has_MTRR(dev)) { if (dev->agp) - dev->agp->agp_mtrr = mtrr_add( dev->agp->agp_info.aper_base, - dev->agp->agp_info.aper_size*1024*1024, - MTRR_TYPE_WRCOMB, - 1 ); + dev->agp->agp_mtrr = + mtrr_add(dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size * + 1024 * 1024, MTRR_TYPE_WRCOMB, 1); } } - retcode = drm_ctxbitmap_init( dev ); - if( retcode ) { - DRM_ERROR( "Cannot allocate memory for context bitmap.\n" ); + retcode = drm_ctxbitmap_init(dev); + if (retcode) { + DRM_ERROR("Cannot allocate memory for context bitmap.\n"); goto error_out_unreg; } - dev->device = MKDEV(DRM_MAJOR, dev->minor ); + dev->device = MKDEV(DRM_MAJOR, dev->minor); /* postinit is a required function to display the signon banner */ /* drivers add secondary heads here if needed */ @@ -126,7 +130,7 @@ static int fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct pci return 0; - error_out_unreg: + error_out_unreg: drm_takedown(dev); return retcode; } @@ -142,7 +146,8 @@ static int fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct pci * then register the character device and inter module information. * Try and register, if we fail to register, backout previous work. */ -int drm_probe(struct pci_dev *pdev, const struct pci_device_id *ent, struct drm_driver_fn *driver_fn) +int drm_probe(struct pci_dev *pdev, const struct pci_device_id *ent, + struct drm_driver_fn *driver_fn) { struct class_device *dev_class; drm_device_t *dev; @@ -157,17 +162,21 @@ int drm_probe(struct pci_dev *pdev, const struct pci_device_id *ent, struct drm_ DRM_DEBUG("assigning minor %d\n", minor); dev = drm_calloc(1, sizeof(*dev), DRM_MEM_STUB); - if(!dev) + if (!dev) return -ENOMEM; - *minors = (drm_minor_t){.dev = dev, .class = DRM_MINOR_PRIMARY}; + *minors = (drm_minor_t) { + .dev = dev,.class = DRM_MINOR_PRIMARY}; dev->minor = minor; if ((ret = fill_in_dev(dev, pdev, ent, driver_fn))) { - printk (KERN_ERR "DRM: Fill_in_dev failed.\n"); + printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); goto err_g1; } - if ((ret = drm_proc_init(dev, minor, drm_proc_root, &minors->dev_root))) { - printk (KERN_ERR "DRM: Failed to initialize /proc/dri.\n"); + if ((ret = + drm_proc_init(dev, minor, drm_proc_root, + &minors->dev_root))) { + printk(KERN_ERR + "DRM: Failed to initialize /proc/dri.\n"); goto err_g1; } if (!drm_fb_loaded) { @@ -176,9 +185,13 @@ int drm_probe(struct pci_dev *pdev, const struct pci_device_id *ent, struct drm_ pci_enable_device(pdev); } dev_class = drm_sysfs_device_add(drm_class, - MKDEV(DRM_MAJOR, minor), DRM_PCI_DEV(pdev), "card%d", minor); + MKDEV(DRM_MAJOR, + minor), + DRM_PCI_DEV(pdev), + "card%d", minor); if (IS_ERR(dev_class)) { - printk (KERN_ERR "DRM: Error sysfs_device_add.\n"); + printk(KERN_ERR + "DRM: Error sysfs_device_add.\n"); ret = PTR_ERR(dev_class); goto err_g2; } @@ -189,15 +202,16 @@ int drm_probe(struct pci_dev *pdev, const struct pci_device_id *ent, struct drm_ } DRM_ERROR("out of minors\n"); return -ENOMEM; -err_g2: + err_g2: if (!drm_fb_loaded) { pci_set_drvdata(pdev, NULL); pci_release_regions(pdev); pci_disable_device(pdev); } drm_proc_cleanup(minor, drm_proc_root, minors->dev_root); -err_g1: - *minors = (drm_minor_t){.dev = NULL, .class = DRM_MINOR_FREE}; + err_g1: + *minors = (drm_minor_t) { + .dev = NULL,.class = DRM_MINOR_FREE}; drm_free(dev, sizeof(*dev), DRM_MEM_STUB); return ret; } @@ -210,11 +224,11 @@ EXPORT_SYMBOL(drm_probe); * \param sec-minor structure to hold the assigned minor * \return negative number on failure. * - * Search an empty entry and initialize it to the given parameters, and + * Search an empty entry and initialize it to the given parameters, and * create the proc init entry via proc_init(). This routines assigns * minor numbers to secondary heads of multi-headed cards */ -int drm_get_secondary_minor(drm_device_t *dev, drm_minor_t **sec_minor) +int drm_get_secondary_minor(drm_device_t * dev, drm_minor_t ** sec_minor) { drm_minor_t *minors = &drm_minors[0]; struct class_device *dev_class; @@ -226,16 +240,24 @@ int drm_get_secondary_minor(drm_device_t *dev, drm_minor_t **sec_minor) for (minor = 0; minor < cards_limit; minor++, minors++) { if (minors->class == DRM_MINOR_FREE) { - *minors = (drm_minor_t){.dev = dev, .class = DRM_MINOR_SECONDARY}; - if ((ret = drm_proc_init(dev, minor, drm_proc_root, &minors->dev_root))) { - printk (KERN_ERR "DRM: Failed to initialize /proc/dri.\n"); + *minors = (drm_minor_t) { + .dev = dev,.class = DRM_MINOR_SECONDARY}; + if ((ret = + drm_proc_init(dev, minor, drm_proc_root, + &minors->dev_root))) { + printk(KERN_ERR + "DRM: Failed to initialize /proc/dri.\n"); goto err_g1; } dev_class = drm_sysfs_device_add(drm_class, - MKDEV(DRM_MAJOR, minor), DRM_PCI_DEV(dev->pdev), "card%d", minor); + MKDEV(DRM_MAJOR, + minor), + DRM_PCI_DEV(dev->pdev), + "card%d", minor); if (IS_ERR(dev_class)) { - printk (KERN_ERR "DRM: Error sysfs_device_add.\n"); + printk(KERN_ERR + "DRM: Error sysfs_device_add.\n"); ret = PTR_ERR(dev_class); goto err_g2; } @@ -247,10 +269,11 @@ int drm_get_secondary_minor(drm_device_t *dev, drm_minor_t **sec_minor) } DRM_ERROR("out of minors\n"); return -ENOMEM; -err_g2: + err_g2: drm_proc_cleanup(minor, drm_proc_root, minors->dev_root); -err_g1: - *minors = (drm_minor_t){.dev = NULL, .class = DRM_MINOR_FREE}; + err_g1: + *minors = (drm_minor_t) { + .dev = NULL,.class = DRM_MINOR_FREE}; drm_free(dev, sizeof(*dev), DRM_MEM_STUB); return ret; } @@ -263,18 +286,19 @@ err_g1: * * Cleans up the proc resources. If it is the last minor then release the foreign * "drm" data, otherwise unregisters the "drm" data, frees the dev list and - * unregisters the character device. + * unregisters the character device. */ -int drm_put_minor(drm_device_t *dev) +int drm_put_minor(drm_device_t * dev) { drm_minor_t *minors = &drm_minors[dev->minor]; - + DRM_DEBUG("release primary minor %d\n", dev->minor); drm_proc_cleanup(dev->minor, drm_proc_root, minors->dev_root); drm_sysfs_device_remove(MKDEV(DRM_MAJOR, dev->minor)); - *minors = (drm_minor_t){.dev = NULL, .class = DRM_MINOR_FREE}; + *minors = (drm_minor_t) { + .dev = NULL,.class = DRM_MINOR_FREE}; drm_free(dev, sizeof(*dev), DRM_MEM_STUB); return 0; @@ -288,9 +312,9 @@ int drm_put_minor(drm_device_t *dev) * * Cleans up the proc resources. Not legal for this to be the * last minor released. - * + * */ -int drm_put_secondary_minor(drm_minor_t *sec_minor) +int drm_put_secondary_minor(drm_minor_t * sec_minor) { int minor = sec_minor - &drm_minors[0]; @@ -299,8 +323,8 @@ int drm_put_secondary_minor(drm_minor_t *sec_minor) drm_proc_cleanup(minor, drm_proc_root, sec_minor->dev_root); drm_sysfs_device_remove(MKDEV(DRM_MAJOR, minor)); - *sec_minor = (drm_minor_t){.dev = NULL, .class = DRM_MINOR_FREE}; + *sec_minor = (drm_minor_t) { + .dev = NULL,.class = DRM_MINOR_FREE}; return 0; } - diff --git a/linux-core/drm_sysfs.c b/linux-core/drm_sysfs.c index f623341b..85edcfc9 100644 --- a/linux-core/drm_sysfs.c +++ b/linux-core/drm_sysfs.c @@ -1,5 +1,5 @@ /* - * drm_sysfs.c - Modifications to drm_sysfs_class.c to support + * drm_sysfs.c - Modifications to drm_sysfs_class.c to support * extra sysfs attribute from DRM. Normal drm_sysfs_class * does not allow adding attributes. * @@ -55,9 +55,10 @@ static void drm_sysfs_class_release(struct class *class) /* Display the version of drm_core. This doesn't work right in current design */ static ssize_t version_show(struct class *dev, char *buf) { - return sprintf(buf, "%s %d.%d.%d %s\n", DRIVER_NAME, DRIVER_MAJOR, - DRIVER_MINOR, DRIVER_PATCHLEVEL, DRIVER_DATE); + return sprintf(buf, "%s %d.%d.%d %s\n", DRIVER_NAME, DRIVER_MAJOR, + DRIVER_MINOR, DRIVER_PATCHLEVEL, DRIVER_DATE); } + static CLASS_ATTR(version, S_IRUGO, version_show, NULL); /** @@ -100,7 +101,7 @@ struct drm_sysfs_class *drm_sysfs_create(struct module *owner, char *name) return cs; -error: + error: kfree(cs); return ERR_PTR(retval); } @@ -127,14 +128,16 @@ void drm_sysfs_destroy(struct drm_sysfs_class *cs) * @device: a pointer to a struct device that is assiociated with this class device. * @fmt: string for the class device's name * - * A struct class_device will be created in sysfs, registered to the specified - * class. A "dev" file will be created, showing the dev_t for the device. The + * A struct class_device will be created in sysfs, registered to the specified + * class. A "dev" file will be created, showing the dev_t for the device. The * pointer to the struct class_device will be returned from the call. Any further * sysfs files that might be required can be created using this pointer. * Note: the struct drm_sysfs_class passed to this function must have previously been * created with a call to drm_sysfs_create(). */ -struct class_device *drm_sysfs_device_add(struct drm_sysfs_class *cs, dev_t dev, struct device *device, const char *fmt, ...) +struct class_device *drm_sysfs_device_add(struct drm_sysfs_class *cs, dev_t dev, + struct device *device, + const char *fmt, ...) { va_list args; struct simple_dev *s_dev = NULL; @@ -171,7 +174,7 @@ struct class_device *drm_sysfs_device_add(struct drm_sysfs_class *cs, dev_t dev, return &s_dev->class_dev; -error: + error: kfree(s_dev); return ERR_PTR(retval); } @@ -203,4 +206,3 @@ void drm_sysfs_device_remove(dev_t dev) spin_unlock(&simple_dev_list_lock); } } - diff --git a/linux-core/drm_vm.c b/linux-core/drm_vm.c index e9ec7fac..6bfb4f10 100644 --- a/linux-core/drm_vm.c +++ b/linux-core/drm_vm.c @@ -1,7 +1,7 @@ /** * \file drm_vm.h * Memory mapping for DRM - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -35,40 +35,42 @@ #include "drmP.h" - /** * \c nopage method for AGP virtual memory. * * \param vma virtual memory area. * \param address access address. * \return pointer to the page structure. - * + * * Find the right map and if it's AGP memory find the real physical page to * map, get the page, increment the use count and return it. */ #if __OS_HAS_AGP static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, - unsigned long address) + unsigned long address) { - drm_file_t *priv = vma->vm_file->private_data; + drm_file_t *priv = vma->vm_file->private_data; drm_device_t *dev = priv->dev; - drm_map_t *map = NULL; - drm_map_list_t *r_list; + drm_map_t *map = NULL; + drm_map_list_t *r_list; struct list_head *list; /* - * Find the right map - */ + * Find the right map + */ if (!drm_core_has_AGP(dev)) goto vm_nopage_error; - if(!dev->agp || !dev->agp->cant_use_aperture) goto vm_nopage_error; + if (!dev->agp || !dev->agp->cant_use_aperture) + goto vm_nopage_error; list_for_each(list, &dev->maplist->head) { r_list = list_entry(list, drm_map_list_t, head); map = r_list->map; - if (!map) continue; - if (map->offset == VM_OFFSET(vma)) break; + if (!map) + continue; + if (map->offset == VM_OFFSET(vma)) + break; } if (map && map->type == _DRM_AGP) { @@ -79,48 +81,50 @@ static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, #ifdef __alpha__ /* - * Adjust to a bus-relative address - */ + * Adjust to a bus-relative address + */ baddr -= dev->hose->mem_space->start; #endif /* - * It's AGP memory - find the real physical page to map - */ - for(agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) { + * It's AGP memory - find the real physical page to map + */ + for (agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) { if (agpmem->bound <= baddr && - agpmem->bound + agpmem->pages * PAGE_SIZE > baddr) + agpmem->bound + agpmem->pages * PAGE_SIZE > baddr) break; } - if (!agpmem) goto vm_nopage_error; + if (!agpmem) + goto vm_nopage_error; /* - * Get the page, inc the use count, and return it - */ + * Get the page, inc the use count, and return it + */ offset = (baddr - agpmem->bound) >> PAGE_SHIFT; page = virt_to_page(__va(agpmem->memory->memory[offset])); get_page(page); -#if 0 +#if 0 /* page_count() not defined everywhere */ - DRM_DEBUG("baddr = 0x%lx page = 0x%p, offset = 0x%lx, count=%d\n", - baddr, __va(agpmem->memory->memory[offset]), offset, - page_count(page)); + DRM_DEBUG + ("baddr = 0x%lx page = 0x%p, offset = 0x%lx, count=%d\n", + baddr, __va(agpmem->memory->memory[offset]), offset, + page_count(page)); #endif return page; - } -vm_nopage_error: - return NOPAGE_SIGBUS; /* Disallow mremap */ + } + vm_nopage_error: + return NOPAGE_SIGBUS; /* Disallow mremap */ } -#else /* __OS_HAS_AGP */ +#else /* __OS_HAS_AGP */ static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, - unsigned long address) + unsigned long address) { return NOPAGE_SIGBUS; } -#endif /* __OS_HAS_AGP */ +#endif /* __OS_HAS_AGP */ /** * \c nopage method for shared virtual memory. @@ -128,22 +132,24 @@ static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, * \param vma virtual memory area. * \param address access address. * \return pointer to the page structure. - * + * * Get the the mapping, find the real physical page to map, get the page, and * return it. */ static __inline__ struct page *drm_do_vm_shm_nopage(struct vm_area_struct *vma, - unsigned long address) + unsigned long address) { - drm_map_t *map = (drm_map_t *)vma->vm_private_data; - unsigned long offset; - unsigned long i; - struct page *page; + drm_map_t *map = (drm_map_t *) vma->vm_private_data; + unsigned long offset; + unsigned long i; + struct page *page; - if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ - if (!map) return NOPAGE_OOM; /* Nothing allocated */ + if (address > vma->vm_end) + return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!map) + return NOPAGE_OOM; /* Nothing allocated */ - offset = address - vma->vm_start; + offset = address - vma->vm_start; i = (unsigned long)map->handle + offset; page = vmalloc_to_page((void *)i); if (!page) @@ -154,19 +160,18 @@ static __inline__ struct page *drm_do_vm_shm_nopage(struct vm_area_struct *vma, return page; } - /** * \c close method for shared virtual memory. - * + * * \param vma virtual memory area. - * + * * Deletes map information if we are the last * person to close a mapping and it's not in the global maplist. */ void drm_vm_shm_close(struct vm_area_struct *vma) { - drm_file_t *priv = vma->vm_file->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->dev; drm_vma_entry_t *pt, *prev, *next; drm_map_t *map; drm_map_list_t *r_list; @@ -182,7 +187,8 @@ void drm_vm_shm_close(struct vm_area_struct *vma) down(&dev->struct_sem); for (pt = dev->vmalist, prev = NULL; pt; pt = next) { next = pt->next; - if (pt->vma->vm_private_data == map) found_maps++; + if (pt->vma->vm_private_data == map) + found_maps++; if (pt->vma == vma) { if (prev) { prev->next = pt->next; @@ -195,8 +201,7 @@ void drm_vm_shm_close(struct vm_area_struct *vma) } } /* We were the only map that was found */ - if(found_maps == 1 && - map->flags & _DRM_REMOVABLE) { + if (found_maps == 1 && map->flags & _DRM_REMOVABLE) { /* Check to see if we are in the maplist, if we are not, then * we delete this mappings information. */ @@ -204,10 +209,11 @@ void drm_vm_shm_close(struct vm_area_struct *vma) list = &dev->maplist->head; list_for_each(list, &dev->maplist->head) { r_list = list_entry(list, drm_map_list_t, head); - if (r_list->map == map) found_maps++; + if (r_list->map == map) + found_maps++; } - if(!found_maps) { + if (!found_maps) { switch (map->type) { case _DRM_REGISTERS: case _DRM_FRAME_BUFFER: @@ -239,27 +245,29 @@ void drm_vm_shm_close(struct vm_area_struct *vma) * \param vma virtual memory area. * \param address access address. * \return pointer to the page structure. - * + * * Determine the page number from the page offset and get it from drm_device_dma::pagelist. */ static __inline__ struct page *drm_do_vm_dma_nopage(struct vm_area_struct *vma, - unsigned long address) + unsigned long address) { - drm_file_t *priv = vma->vm_file->private_data; - drm_device_t *dev = priv->dev; - drm_device_dma_t *dma = dev->dma; - unsigned long offset; - unsigned long page_nr; - struct page *page; - - if (!dma) return NOPAGE_SIGBUS; /* Error */ - if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ - if (!dma->pagelist) return NOPAGE_OOM ; /* Nothing allocated */ - - offset = address - vma->vm_start; /* vm_[pg]off[set] should be 0 */ - page_nr = offset >> PAGE_SHIFT; - page = virt_to_page((dma->pagelist[page_nr] + - (offset & (~PAGE_MASK)))); + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + unsigned long offset; + unsigned long page_nr; + struct page *page; + + if (!dma) + return NOPAGE_SIGBUS; /* Error */ + if (address > vma->vm_end) + return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!dma->pagelist) + return NOPAGE_OOM; /* Nothing allocated */ + + offset = address - vma->vm_start; /* vm_[pg]off[set] should be 0 */ + page_nr = offset >> PAGE_SHIFT; + page = virt_to_page((dma->pagelist[page_nr] + (offset & (~PAGE_MASK)))); get_page(page); @@ -273,13 +281,13 @@ static __inline__ struct page *drm_do_vm_dma_nopage(struct vm_area_struct *vma, * \param vma virtual memory area. * \param address access address. * \return pointer to the page structure. - * + * * Determine the map offset from the page offset and get it from drm_sg_mem::pagelist. */ static __inline__ struct page *drm_do_vm_sg_nopage(struct vm_area_struct *vma, - unsigned long address) + unsigned long address) { - drm_map_t *map = (drm_map_t *)vma->vm_private_data; + drm_map_t *map = (drm_map_t *) vma->vm_private_data; drm_file_t *priv = vma->vm_file->private_data; drm_device_t *dev = priv->dev; drm_sg_mem_t *entry = dev->sg; @@ -288,10 +296,12 @@ static __inline__ struct page *drm_do_vm_sg_nopage(struct vm_area_struct *vma, unsigned long page_offset; struct page *page; - if (!entry) return NOPAGE_SIGBUS; /* Error */ - if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ - if (!entry->pagelist) return NOPAGE_OOM ; /* Nothing allocated */ - + if (!entry) + return NOPAGE_SIGBUS; /* Error */ + if (address > vma->vm_end) + return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!entry->pagelist) + return NOPAGE_OOM; /* Nothing allocated */ offset = address - vma->vm_start; map_offset = map->offset - dev->sg->handle; @@ -302,107 +312,108 @@ static __inline__ struct page *drm_do_vm_sg_nopage(struct vm_area_struct *vma, return page; } - #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) static struct page *drm_vm_nopage(struct vm_area_struct *vma, - unsigned long address, - int *type) { - if (type) *type = VM_FAULT_MINOR; + unsigned long address, int *type) +{ + if (type) + *type = VM_FAULT_MINOR; return drm_do_vm_nopage(vma, address); } static struct page *drm_vm_shm_nopage(struct vm_area_struct *vma, - unsigned long address, - int *type) { - if (type) *type = VM_FAULT_MINOR; + unsigned long address, int *type) +{ + if (type) + *type = VM_FAULT_MINOR; return drm_do_vm_shm_nopage(vma, address); } static struct page *drm_vm_dma_nopage(struct vm_area_struct *vma, - unsigned long address, - int *type) { - if (type) *type = VM_FAULT_MINOR; + unsigned long address, int *type) +{ + if (type) + *type = VM_FAULT_MINOR; return drm_do_vm_dma_nopage(vma, address); } static struct page *drm_vm_sg_nopage(struct vm_area_struct *vma, - unsigned long address, - int *type) { - if (type) *type = VM_FAULT_MINOR; + unsigned long address, int *type) +{ + if (type) + *type = VM_FAULT_MINOR; return drm_do_vm_sg_nopage(vma, address); } -#else /* LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,0) */ +#else /* LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,0) */ static struct page *drm_vm_nopage(struct vm_area_struct *vma, - unsigned long address, - int unused) { + unsigned long address, int unused) +{ return drm_do_vm_nopage(vma, address); } static struct page *drm_vm_shm_nopage(struct vm_area_struct *vma, - unsigned long address, - int unused) { + unsigned long address, int unused) +{ return drm_do_vm_shm_nopage(vma, address); } static struct page *drm_vm_dma_nopage(struct vm_area_struct *vma, - unsigned long address, - int unused) { + unsigned long address, int unused) +{ return drm_do_vm_dma_nopage(vma, address); } static struct page *drm_vm_sg_nopage(struct vm_area_struct *vma, - unsigned long address, - int unused) { + unsigned long address, int unused) +{ return drm_do_vm_sg_nopage(vma, address); } #endif - /** AGP virtual memory operations */ -static struct vm_operations_struct drm_vm_ops = { +static struct vm_operations_struct drm_vm_ops = { .nopage = drm_vm_nopage, - .open = drm_vm_open, - .close = drm_vm_close, + .open = drm_vm_open, + .close = drm_vm_close, }; /** Shared virtual memory operations */ -static struct vm_operations_struct drm_vm_shm_ops = { +static struct vm_operations_struct drm_vm_shm_ops = { .nopage = drm_vm_shm_nopage, - .open = drm_vm_open, - .close = drm_vm_shm_close, + .open = drm_vm_open, + .close = drm_vm_shm_close, }; /** DMA virtual memory operations */ -static struct vm_operations_struct drm_vm_dma_ops = { +static struct vm_operations_struct drm_vm_dma_ops = { .nopage = drm_vm_dma_nopage, - .open = drm_vm_open, - .close = drm_vm_close, + .open = drm_vm_open, + .close = drm_vm_close, }; /** Scatter-gather virtual memory operations */ -static struct vm_operations_struct drm_vm_sg_ops = { +static struct vm_operations_struct drm_vm_sg_ops = { .nopage = drm_vm_sg_nopage, - .open = drm_vm_open, - .close = drm_vm_close, + .open = drm_vm_open, + .close = drm_vm_close, }; - /** * \c open method for shared virtual memory. - * + * * \param vma virtual memory area. - * + * * Create a new drm_vma_entry structure as the \p vma private data entry and * add it to drm_device::vmalist. */ void drm_vm_open(struct vm_area_struct *vma) { - drm_file_t *priv = vma->vm_file->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->dev; drm_vma_entry_t *vma_entry; DRM_DEBUG("0x%08lx,0x%08lx\n", @@ -412,26 +423,26 @@ void drm_vm_open(struct vm_area_struct *vma) vma_entry = drm_alloc(sizeof(*vma_entry), DRM_MEM_VMAS); if (vma_entry) { down(&dev->struct_sem); - vma_entry->vma = vma; + vma_entry->vma = vma; vma_entry->next = dev->vmalist; - vma_entry->pid = current->pid; - dev->vmalist = vma_entry; + vma_entry->pid = current->pid; + dev->vmalist = vma_entry; up(&dev->struct_sem); } } /** * \c close method for all virtual memory types. - * + * * \param vma virtual memory area. - * + * * Search the \p vma private data entry in drm_device::vmalist, unlink it, and * free it. */ void drm_vm_close(struct vm_area_struct *vma) { - drm_file_t *priv = vma->vm_file->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->dev; drm_vma_entry_t *pt, *prev; DRM_DEBUG("0x%08lx,0x%08lx\n", @@ -459,44 +470,44 @@ void drm_vm_close(struct vm_area_struct *vma) * \param filp file pointer. * \param vma virtual memory area. * \return zero on success or a negative number on failure. - * + * * Sets the virtual memory area operations structure to vm_dma_ops, the file * pointer, and calls vm_open(). */ int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev; drm_device_dma_t *dma; - unsigned long length = vma->vm_end - vma->vm_start; + unsigned long length = vma->vm_end - vma->vm_start; lock_kernel(); - dev = priv->dev; - dma = dev->dma; + dev = priv->dev; + dma = dev->dma; DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n", vma->vm_start, vma->vm_end, VM_OFFSET(vma)); - /* Length must match exact page count */ + /* Length must match exact page count */ if (!dma || (length >> PAGE_SHIFT) != dma->page_count) { unlock_kernel(); return -EINVAL; } unlock_kernel(); - vma->vm_ops = &drm_vm_dma_ops; + vma->vm_ops = &drm_vm_dma_ops; -#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ - vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */ +#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ + vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */ #else - vma->vm_flags |= VM_RESERVED; /* Don't swap */ + vma->vm_flags |= VM_RESERVED; /* Don't swap */ #endif - vma->vm_file = filp; /* Needed for drm_vm_open() */ + vma->vm_file = filp; /* Needed for drm_vm_open() */ drm_vm_open(vma); return 0; } -unsigned long drm_core_get_map_ofs(drm_map_t *map) +unsigned long drm_core_get_map_ofs(drm_map_t * map) { return map->offset; } @@ -518,7 +529,7 @@ EXPORT_SYMBOL(drm_core_get_reg_ofs); * \param filp file pointer. * \param vma virtual memory area. * \return zero on success or a negative number on failure. - * + * * If the virtual memory area has no offset associated with it then it's a DMA * area, so calls mmap_dma(). Otherwise searches the map in drm_device::maplist, * checks that the restricted flag is not set, sets the virtual memory operations @@ -527,17 +538,18 @@ EXPORT_SYMBOL(drm_core_get_reg_ofs); */ int drm_mmap(struct file *filp, struct vm_area_struct *vma) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_map_t *map = NULL; - drm_map_list_t *r_list; - unsigned long offset = 0; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_map_t *map = NULL; + drm_map_list_t *r_list; + unsigned long offset = 0; struct list_head *list; DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n", vma->vm_start, vma->vm_end, VM_OFFSET(vma)); - if ( !priv->authenticated ) return -EACCES; + if (!priv->authenticated) + return -EACCES; /* We check for "dma". On Apple's UniNorth, it's valid to have * the AGP mapped at physical address 0 @@ -545,62 +557,68 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma) */ if (!VM_OFFSET(vma) #if __OS_HAS_AGP - && (!dev->agp || dev->agp->agp_info.device->vendor != PCI_VENDOR_ID_APPLE) + && (!dev->agp + || dev->agp->agp_info.device->vendor != PCI_VENDOR_ID_APPLE) #endif ) return drm_mmap_dma(filp, vma); - /* A sequential search of a linked list is - fine here because: 1) there will only be - about 5-10 entries in the list and, 2) a - DRI client only has to do this mapping - once, so it doesn't have to be optimized - for performance, even if the list was a - bit longer. */ + /* A sequential search of a linked list is + fine here because: 1) there will only be + about 5-10 entries in the list and, 2) a + DRI client only has to do this mapping + once, so it doesn't have to be optimized + for performance, even if the list was a + bit longer. */ list_for_each(list, &dev->maplist->head) { unsigned long off; r_list = list_entry(list, drm_map_list_t, head); map = r_list->map; - if (!map) continue; + if (!map) + continue; off = dev->fn_tbl->get_map_ofs(map); - if (off == VM_OFFSET(vma)) break; + if (off == VM_OFFSET(vma)) + break; } - if (!map || ((map->flags&_DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN))) + if (!map || ((map->flags & _DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN))) return -EPERM; - /* Check for valid size. */ - if (map->size < vma->vm_end - vma->vm_start) return -EINVAL; + /* Check for valid size. */ + if (map->size < vma->vm_end - vma->vm_start) + return -EINVAL; if (!capable(CAP_SYS_ADMIN) && (map->flags & _DRM_READ_ONLY)) { vma->vm_flags &= ~(VM_WRITE | VM_MAYWRITE); #if defined(__i386__) || defined(__x86_64__) pgprot_val(vma->vm_page_prot) &= ~_PAGE_RW; #else - /* Ye gads this is ugly. With more thought - we could move this up higher and use - `protection_map' instead. */ - vma->vm_page_prot = __pgprot(pte_val(pte_wrprotect( - __pte(pgprot_val(vma->vm_page_prot))))); + /* Ye gads this is ugly. With more thought + we could move this up higher and use + `protection_map' instead. */ + vma->vm_page_prot = + __pgprot(pte_val + (pte_wrprotect + (__pte(pgprot_val(vma->vm_page_prot))))); #endif } switch (map->type) { - case _DRM_AGP: - if (drm_core_has_AGP(dev) && dev->agp->cant_use_aperture) { - /* - * On some platforms we can't talk to bus dma address from the CPU, so for - * memory of type DRM_AGP, we'll deal with sorting out the real physical - * pages and mappings in nopage() - */ + case _DRM_AGP: + if (drm_core_has_AGP(dev) && dev->agp->cant_use_aperture) { + /* + * On some platforms we can't talk to bus dma address from the CPU, so for + * memory of type DRM_AGP, we'll deal with sorting out the real physical + * pages and mappings in nopage() + */ #if defined(__powerpc__) - pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE; + pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE; #endif - vma->vm_ops = &drm_vm_ops; - break; - } - /* fall through to _DRM_FRAME_BUFFER... */ + vma->vm_ops = &drm_vm_ops; + break; + } + /* fall through to _DRM_FRAME_BUFFER... */ case _DRM_FRAME_BUFFER: case _DRM_REGISTERS: if (VM_OFFSET(vma) >= __pa(high_memory)) { @@ -610,13 +628,15 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma) pgprot_val(vma->vm_page_prot) &= ~_PAGE_PWT; } #elif defined(__powerpc__) - pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE | _PAGE_GUARDED; + pgprot_val(vma->vm_page_prot) |= + _PAGE_NO_CACHE | _PAGE_GUARDED; #endif vma->vm_flags |= VM_IO; /* not in core dump */ } #if defined(__ia64__) if (map->type != _DRM_AGP) - vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + vma->vm_page_prot = + pgprot_writecombine(vma->vm_page_prot); #endif offset = dev->fn_tbl->get_reg_ofs(dev); #ifdef __sparc__ @@ -630,7 +650,7 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma) vma->vm_end - vma->vm_start, vma->vm_page_prot)) #endif - return -EAGAIN; + return -EAGAIN; DRM_DEBUG(" Type = %d; start = 0x%lx, end = 0x%lx," " offset = 0x%lx\n", map->type, @@ -640,9 +660,9 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma) case _DRM_SHM: vma->vm_ops = &drm_vm_shm_ops; vma->vm_private_data = (void *)map; - /* Don't let this area swap. Change when - DRM_KERNEL advisory is supported. */ -#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ + /* Don't let this area swap. Change when + DRM_KERNEL advisory is supported. */ +#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ vma->vm_flags |= VM_LOCKED; #else vma->vm_flags |= VM_RESERVED; @@ -651,22 +671,22 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma) case _DRM_SCATTER_GATHER: vma->vm_ops = &drm_vm_sg_ops; vma->vm_private_data = (void *)map; -#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ +#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ vma->vm_flags |= VM_LOCKED; #else vma->vm_flags |= VM_RESERVED; #endif - break; + break; default: return -EINVAL; /* This should never happen. */ } -#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ - vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */ +#if LINUX_VERSION_CODE <= 0x02040e /* KERNEL_VERSION(2,4,14) */ + vma->vm_flags |= VM_LOCKED | VM_SHM; /* Don't swap */ #else - vma->vm_flags |= VM_RESERVED; /* Don't swap */ + vma->vm_flags |= VM_RESERVED; /* Don't swap */ #endif - vma->vm_file = filp; /* Needed for drm_vm_open() */ + vma->vm_file = filp; /* Needed for drm_vm_open() */ drm_vm_open(vma); return 0; } diff --git a/linux-core/ffb_context.c b/linux-core/ffb_context.c index b4ce2a09..a7d5025b 100644 --- a/linux-core/ffb_context.c +++ b/linux-core/ffb_context.c @@ -10,13 +10,10 @@ #include #include -#include "ffb.h" #include "drmP.h" - #include "ffb_drv.h" -static int DRM(alloc_queue)(drm_device_t *dev, int is_2d_only) -{ +static int DRM(alloc_queue) (drm_device_t * dev, int is_2d_only) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int i; @@ -37,7 +34,7 @@ static int DRM(alloc_queue)(drm_device_t *dev, int is_2d_only) return i + 1; } -static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) +static void ffb_save_context(ffb_dev_priv_t * fpriv, int idx) { ffb_fbcPtr ffb = fpriv->regs; struct ffb_hw_context *ctx; @@ -94,36 +91,36 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) /* Capture rendering attributes. */ - ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */ - ctx->wid = upa_readl(&ffb->wid); /* Current WID */ - ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */ - ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */ - ctx->consty = upa_readl(&ffb->consty); /* Constant Y */ - ctx->constz = upa_readl(&ffb->constz); /* Constant Z */ - ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */ - ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */ + ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */ + ctx->wid = upa_readl(&ffb->wid); /* Current WID */ + ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */ + ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */ + ctx->consty = upa_readl(&ffb->consty); /* Constant Y */ + ctx->constz = upa_readl(&ffb->constz); /* Constant Z */ + ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */ + ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */ ctx->vclipmin = upa_readl(&ffb->vclipmin); /* Primary XY clip, minimum */ ctx->vclipmax = upa_readl(&ffb->vclipmax); /* Primary XY clip, maximum */ ctx->vclipzmin = upa_readl(&ffb->vclipzmin); /* Primary Z clip, minimum */ ctx->vclipzmax = upa_readl(&ffb->vclipzmax); /* Primary Z clip, maximum */ - ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */ - ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */ - ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */ - ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */ - ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */ + ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */ + ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */ + ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */ + ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */ + ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */ ctx->blendc1 = upa_readl(&ffb->blendc1); /* Alpha Blend Color 1 */ ctx->blendc2 = upa_readl(&ffb->blendc2); /* Alpha Blend Color 2 */ - ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */ - ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */ - ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */ + ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */ + ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */ + ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */ ctx->matchab = upa_readl(&ffb->matchab); /* Buffer A/B Match Ops */ - ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */ - ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */ - ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */ - ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */ - ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */ - ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */ - ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */ + ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */ + ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */ + ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */ + ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */ + ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */ + ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */ + ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */ /* Auxiliary Clips. */ ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min); @@ -135,9 +132,9 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min); ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max); - ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */ - ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */ - ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */ + ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */ + ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */ + ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */ ctx->fontinc = upa_readl(&ffb->fontinc); /* Font X/Y Increment */ /* These registers/features only exist on FFB2 and later chips. */ @@ -145,12 +142,12 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) ctx->dcss1 = upa_readl(&ffb->dcss1); /* Depth Cue Scale Slope 1 */ ctx->dcss2 = upa_readl(&ffb->dcss2); /* Depth Cue Scale Slope 2 */ ctx->dcss2 = upa_readl(&ffb->dcss3); /* Depth Cue Scale Slope 3 */ - ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */ - ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */ - ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */ - ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */ - ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */ - ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */ + ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */ + ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */ + ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */ + ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */ + ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */ + ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */ /* And stencil/stencilctl only exists on FFB2+ and later * due to the introduction of 3DRAM-III. @@ -170,7 +167,7 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) ctx->ucsr = upa_readl(&ffb->ucsr); } -static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) +static void ffb_restore_context(ffb_dev_priv_t * fpriv, int old, int idx) { ffb_fbcPtr ffb = fpriv->regs; struct ffb_hw_context *ctx; @@ -193,7 +190,7 @@ static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) upa_writel(ctx->ppc, &ffb->ppc); upa_writel(ctx->wid, &ffb->wid); - upa_writel(ctx->fg, &ffb->fg); + upa_writel(ctx->fg, &ffb->fg); upa_writel(ctx->bg, &ffb->bg); upa_writel(ctx->xclip, &ffb->xclip); upa_writel(ctx->fbc, &ffb->fbc); @@ -237,36 +234,36 @@ static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) /* Restore rendering attributes. */ - upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */ - upa_writel(ctx->wid, &ffb->wid); /* Current WID */ - upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */ - upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */ - upa_writel(ctx->consty, &ffb->consty); /* Constant Y */ - upa_writel(ctx->constz, &ffb->constz); /* Constant Z */ - upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */ - upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */ + upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */ + upa_writel(ctx->wid, &ffb->wid); /* Current WID */ + upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */ + upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */ + upa_writel(ctx->consty, &ffb->consty); /* Constant Y */ + upa_writel(ctx->constz, &ffb->constz); /* Constant Z */ + upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */ + upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */ upa_writel(ctx->vclipmin, &ffb->vclipmin); /* Primary XY clip, minimum */ upa_writel(ctx->vclipmax, &ffb->vclipmax); /* Primary XY clip, maximum */ upa_writel(ctx->vclipzmin, &ffb->vclipzmin); /* Primary Z clip, minimum */ upa_writel(ctx->vclipzmax, &ffb->vclipzmax); /* Primary Z clip, maximum */ - upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */ - upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */ - upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */ - upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */ - upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */ + upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */ + upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */ + upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */ + upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */ + upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */ upa_writel(ctx->blendc1, &ffb->blendc1); /* Alpha Blend Color 1 */ upa_writel(ctx->blendc2, &ffb->blendc2); /* Alpha Blend Color 2 */ - upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */ - upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */ - upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */ + upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */ + upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */ + upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */ upa_writel(ctx->matchab, &ffb->matchab); /* Buffer A/B Match Ops */ - upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */ - upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */ - upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */ - upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */ - upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */ - upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */ - upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */ + upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */ + upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */ + upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */ + upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */ + upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */ + upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */ + upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */ /* Auxiliary Clips. */ upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min); @@ -278,9 +275,9 @@ static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min); upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max); - upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */ - upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */ - upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */ + upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */ + upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */ + upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */ upa_writel(ctx->fontinc, &ffb->fontinc); /* Font X/Y Increment */ /* These registers/features only exist on FFB2 and later chips. */ @@ -354,91 +351,83 @@ static void FFBWait(ffb_fbcPtr ffb) } while (--limit); } -int DRM(context_switch)(drm_device_t *dev, int old, int new) -{ +int DRM(context_switch) (drm_device_t * dev, int old, int new) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; #if DRM_DMA_HISTOGRAM - dev->ctx_start = get_cycles(); + dev->ctx_start = get_cycles(); #endif - - DRM_DEBUG("Context switch from %d to %d\n", old, new); - if (new == dev->last_context || - dev->last_context == 0) { + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new == dev->last_context || dev->last_context == 0) { dev->last_context = new; - return 0; + return 0; } - + FFBWait(fpriv->regs); ffb_save_context(fpriv, old); ffb_restore_context(fpriv, old, new); FFBWait(fpriv->regs); - + dev->last_context = new; - return 0; + return 0; } -int DRM(resctx)(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) -{ - drm_ctx_res_t res; - drm_ctx_t ctx; - int i; +int DRM(resctx) (struct inode * inode, struct file * filp, unsigned int cmd, + unsigned long arg) { + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); - if (copy_from_user(&res, (drm_ctx_res_t __user *)arg, sizeof(res))) + if (copy_from_user(&res, (drm_ctx_res_t __user *) arg, sizeof(res))) return -EFAULT; if (res.count >= DRM_RESERVED_CONTEXTS) { memset(&ctx, 0, sizeof(ctx)); for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { ctx.handle = i; - if (copy_to_user(&res.contexts[i], - &i, - sizeof(i))) + if (copy_to_user(&res.contexts[i], &i, sizeof(i))) return -EFAULT; } } res.count = DRM_RESERVED_CONTEXTS; - if (copy_to_user((drm_ctx_res_t __user *)arg, &res, sizeof(res))) + if (copy_to_user((drm_ctx_res_t __user *) arg, &res, sizeof(res))) return -EFAULT; return 0; } - -int DRM(addctx)(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) -{ - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_ctx_t ctx; +int DRM(addctx) (struct inode * inode, struct file * filp, unsigned int cmd, + unsigned long arg) { + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; int idx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; - idx = DRM(alloc_queue)(dev, (ctx.flags & _DRM_CONTEXT_2DONLY)); + idx = DRM(alloc_queue) (dev, (ctx.flags & _DRM_CONTEXT_2DONLY)); if (idx < 0) return -ENFILE; DRM_DEBUG("%d\n", ctx.handle); ctx.handle = idx; - if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx))) + if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx))) return -EFAULT; return 0; } -int DRM(modctx)(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) -{ - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; +int DRM(modctx) (struct inode * inode, struct file * filp, unsigned int cmd, + unsigned long arg) { + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; struct ffb_hw_context *hwctx; drm_ctx_t ctx; int idx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; idx = ctx.handle; @@ -457,17 +446,16 @@ int DRM(modctx)(struct inode *inode, struct file *filp, unsigned int cmd, return 0; } -int DRM(getctx)(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) -{ - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; +int DRM(getctx) (struct inode * inode, struct file * filp, unsigned int cmd, + unsigned long arg) { + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; struct ffb_hw_context *hwctx; drm_ctx_t ctx; int idx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; idx = ctx.handle; @@ -483,47 +471,44 @@ int DRM(getctx)(struct inode *inode, struct file *filp, unsigned int cmd, else ctx.flags = 0; - if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx))) + if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx))) return -EFAULT; return 0; } -int DRM(switchctx)(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) -{ - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_ctx_t ctx; +int DRM(switchctx) (struct inode * inode, struct file * filp, unsigned int cmd, + unsigned long arg) { + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); - return DRM(context_switch)(dev, dev->last_context, ctx.handle); + return DRM(context_switch) (dev, dev->last_context, ctx.handle); } -int DRM(newctx)(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) -{ - drm_ctx_t ctx; +int DRM(newctx) (struct inode * inode, struct file * filp, unsigned int cmd, + unsigned long arg) { + drm_ctx_t ctx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); return 0; } -int DRM(rmctx)(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) -{ - drm_ctx_t ctx; - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; +int DRM(rmctx) (struct inode * inode, struct file * filp, unsigned int cmd, + unsigned long arg) { + drm_ctx_t ctx; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int idx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); @@ -538,7 +523,7 @@ int DRM(rmctx)(struct inode *inode, struct file *filp, unsigned int cmd, return 0; } -static void ffb_driver_release(drm_device_t *dev) +static void ffb_driver_release(drm_device_t * dev) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int context = _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock); @@ -546,28 +531,30 @@ static void ffb_driver_release(drm_device_t *dev) idx = context - 1; if (fpriv && - context != DRM_KERNEL_CONTEXT && - fpriv->hw_state[idx] != NULL) { + context != DRM_KERNEL_CONTEXT && fpriv->hw_state[idx] != NULL) { kfree(fpriv->hw_state[idx]); fpriv->hw_state[idx] = NULL; - } + } } -static int ffb_driver_presetup(drm_device_t *dev) +static int ffb_driver_presetup(drm_device_t * dev) { int ret; ret = ffb_presetup(dev); - if (_ret != 0) return ret; + if (_ret != 0) + return ret; } -static void ffb_driver_pretakedown(drm_device_t *dev) +static void ffb_driver_pretakedown(drm_device_t * dev) { - if (dev->dev_private) kfree(dev->dev_private); + if (dev->dev_private) + kfree(dev->dev_private); } -static void ffb_driver_postcleanup(drm_device_t *dev) +static void ffb_driver_postcleanup(drm_device_t * dev) { - if (ffb_position != NULL) kfree(ffb_position); + if (ffb_position != NULL) + kfree(ffb_position); } static int ffb_driver_kernel_context_switch_unlock(struct drm_device *dev) @@ -576,25 +563,25 @@ static int ffb_driver_kernel_context_switch_unlock(struct drm_device *dev) { __volatile__ unsigned int *plock = &dev->lock.hw_lock->lock; unsigned int old, new, prev, ctx; - + ctx = lock.context; do { - old = *plock; - new = ctx; + old = *plock; + new = ctx; prev = cmpxchg(plock, old, new); } while (prev != old); } wake_up_interruptible(&dev->lock.lock_queue); } -unsigned long ffb_driver_get_map_ofs(drm_map_t *map) +unsigned long ffb_driver_get_map_ofs(drm_map_t * map) { return (map->offset & 0xffffffff); } -unsigned long ffb_driver_get_reg_ofs(drm_device_t *dev) +unsigned long ffb_driver_get_reg_ofs(drm_device_t * dev) { - ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *)dev->dev_private; + ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *) dev->dev_private; if (ffb_priv) return ffb_priv->card_phys_base; diff --git a/linux-core/ffb_drv.c b/linux-core/ffb_drv.c index d0a32041..60cd8f74 100644 --- a/linux-core/ffb_drv.c +++ b/linux-core/ffb_drv.c @@ -5,17 +5,15 @@ */ #include -#include "ffb.h" -#include "drmP.h" - -#include "ffb_drv.h" - #include #include #include #include #include +#include "drmP.h" +#include "ffb_drv.h" + #define DRIVER_AUTHOR "David S. Miller" #define DRIVER_NAME "ffb" @@ -86,7 +84,7 @@ static void get_ffb_type(ffb_dev_priv_t *ffb_priv, int instance) }; } -static void ffb_apply_upa_parent_ranges(int parent, +static void ffb_apply_upa_parent_ranges(int parent, struct linux_prom64_registers *regs) { struct linux_prom64_ranges ranges[PROMREG_MAX]; @@ -136,7 +134,7 @@ static int ffb_init_one(drm_device_t *dev, int prom_node, int parent_node, get_ffb_type(ffb_priv, instance); for (i = 0; i < FFB_MAX_CTXS; i++) ffb_priv->hw_state[i] = NULL; - + return 0; } @@ -279,7 +277,7 @@ int ffb_presetup(drm_device_t *dev) static int postinit( struct drm_device *dev, unsigned long flags ) { DRM(fops).get_unmapped_area = ffb_get_unmapped_area; - + DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", DRIVER_NAME, DRIVER_MAJOR, diff --git a/linux-core/ffb_drv.h b/linux-core/ffb_drv.h index 54384524..8761634e 100644 --- a/linux-core/ffb_drv.h +++ b/linux-core/ffb_drv.h @@ -78,11 +78,11 @@ typedef struct _ffb_fbc { /* fastfill(NX) */ /*0x78*/unsigned int pad6[2]; /* Reserved */ /*0x80*/unsigned int pad7[32]; /* Reserved */ - + /* Setup Unit's vertex state register */ /*100*/ volatile unsigned int suvtx; /*104*/ unsigned int pad8[63]; /* Reserved */ - + /* Frame Buffer Control Registers */ /*200*/ volatile unsigned int ppc; /* Pixel Processor Control */ /*204*/ volatile unsigned int wid; /* Current WID */ @@ -125,7 +125,7 @@ typedef struct _ffb_fbc { /*298*/ volatile unsigned int ypmask; /* Y PlaneMask */ /*29c*/ volatile unsigned int zpmask; /* Z PlaneMask */ /*2a0*/ ffb_auxclip auxclip[4]; /* Auxilliary Viewport Clip */ - + /* New 3dRAM III support regs */ /*2c0*/ volatile unsigned int rawblend2; /*2c4*/ volatile unsigned int rawpreblend; @@ -143,7 +143,7 @@ typedef struct _ffb_fbc { /*2f4*/ volatile unsigned int rawcmp; /*2f8*/ volatile unsigned int rawwac; /*2fc*/ volatile unsigned int fbramid; - + /*300*/ volatile unsigned int drawop; /* Draw OPeration */ /*304*/ unsigned int pad10[2]; /* Reserved */ /*30c*/ volatile unsigned int lpat; /* Line Pattern control */ diff --git a/linux-core/i810_dma.c b/linux-core/i810_dma.c index fce012b7..0f1f4400 100644 --- a/linux-core/i810_dma.c +++ b/linux-core/i810_dma.c @@ -30,13 +30,14 @@ * */ +#include /* For task queue support */ +#include +#include + #include "drmP.h" #include "drm.h" #include "i810_drm.h" #include "i810_drv.h" -#include /* For task queue support */ -#include -#include #ifdef DO_MUNMAP_4_ARGS #define DO_MUNMAP(m, a, l) do_munmap(m, a, l, 1) @@ -51,108 +52,107 @@ #define I810_BUF_UNMAPPED 0 #define I810_BUF_MAPPED 1 -static inline void i810_print_status_page(drm_device_t *dev) +static inline void i810_print_status_page(drm_device_t * dev) { - drm_device_dma_t *dma = dev->dma; - drm_i810_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_i810_private_t *dev_priv = dev->dev_private; u32 *temp = dev_priv->hw_status_page; - int i; - - DRM_DEBUG( "hw_status: Interrupt Status : %x\n", temp[0]); - DRM_DEBUG( "hw_status: LpRing Head ptr : %x\n", temp[1]); - DRM_DEBUG( "hw_status: IRing Head ptr : %x\n", temp[2]); - DRM_DEBUG( "hw_status: Reserved : %x\n", temp[3]); - DRM_DEBUG( "hw_status: Last Render: %x\n", temp[4]); - DRM_DEBUG( "hw_status: Driver Counter : %d\n", temp[5]); - for(i = 6; i < dma->buf_count + 6; i++) { - DRM_DEBUG( "buffer status idx : %d used: %d\n", i - 6, temp[i]); + int i; + + DRM_DEBUG("hw_status: Interrupt Status : %x\n", temp[0]); + DRM_DEBUG("hw_status: LpRing Head ptr : %x\n", temp[1]); + DRM_DEBUG("hw_status: IRing Head ptr : %x\n", temp[2]); + DRM_DEBUG("hw_status: Reserved : %x\n", temp[3]); + DRM_DEBUG("hw_status: Last Render: %x\n", temp[4]); + DRM_DEBUG("hw_status: Driver Counter : %d\n", temp[5]); + for (i = 6; i < dma->buf_count + 6; i++) { + DRM_DEBUG("buffer status idx : %d used: %d\n", i - 6, temp[i]); } } -static drm_buf_t *i810_freelist_get(drm_device_t *dev) +static drm_buf_t *i810_freelist_get(drm_device_t * dev) { - drm_device_dma_t *dma = dev->dma; - int i; - int used; + drm_device_dma_t *dma = dev->dma; + int i; + int used; /* Linear search might not be the best solution */ - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i810_buf_priv_t *buf_priv = buf->dev_private; + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; /* In use is already a pointer */ - used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, + used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, I810_BUF_CLIENT); if (used == I810_BUF_FREE) { return buf; } } - return NULL; + return NULL; } /* This should only be called if the buffer is not sent to the hardware * yet, the hardware updates in use for us once its on the ring buffer. */ -static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf) +static int i810_freelist_put(drm_device_t * dev, drm_buf_t * buf) { - drm_i810_buf_priv_t *buf_priv = buf->dev_private; - int used; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + int used; - /* In use is already a pointer */ - used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE); + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE); if (used != I810_BUF_CLIENT) { - DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); - return -EINVAL; + DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); + return -EINVAL; } - return 0; + return 0; } int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev; - drm_i810_private_t *dev_priv; - drm_buf_t *buf; + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_i810_private_t *dev_priv; + drm_buf_t *buf; drm_i810_buf_priv_t *buf_priv; lock_kernel(); - dev = priv->dev; + dev = priv->dev; dev_priv = dev->dev_private; - buf = dev_priv->mmap_buffer; + buf = dev_priv->mmap_buffer; buf_priv = buf->dev_private; vma->vm_flags |= (VM_IO | VM_DONTCOPY); vma->vm_file = filp; - buf_priv->currently_mapped = I810_BUF_MAPPED; + buf_priv->currently_mapped = I810_BUF_MAPPED; unlock_kernel(); if (remap_page_range(DRM_RPR_ARG(vma) vma->vm_start, VM_OFFSET(vma), - vma->vm_end - vma->vm_start, - vma->vm_page_prot)) return -EAGAIN; + vma->vm_end - vma->vm_start, vma->vm_page_prot)) + return -EAGAIN; return 0; } -static int i810_map_buffer(drm_buf_t *buf, struct file *filp) +static int i810_map_buffer(drm_buf_t * buf, struct file *filp) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_i810_buf_priv_t *buf_priv = buf->dev_private; - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; int retcode = 0; - if (buf_priv->currently_mapped == I810_BUF_MAPPED) + if (buf_priv->currently_mapped == I810_BUF_MAPPED) return -EINVAL; - down_write( ¤t->mm->mmap_sem ); + down_write(¤t->mm->mmap_sem); dev_priv->mmap_buffer = buf; buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total, - PROT_READ|PROT_WRITE, - MAP_SHARED, - buf->bus_address); + PROT_READ | PROT_WRITE, + MAP_SHARED, buf->bus_address); dev_priv->mmap_buffer = NULL; if ((unsigned long)buf_priv->virtual > -1024UL) { @@ -161,12 +161,12 @@ static int i810_map_buffer(drm_buf_t *buf, struct file *filp) retcode = (signed int)buf_priv->virtual; buf_priv->virtual = NULL; } - up_write( ¤t->mm->mmap_sem ); + up_write(¤t->mm->mmap_sem); return retcode; } -static int i810_unmap_buffer(drm_buf_t *buf) +static int i810_unmap_buffer(drm_buf_t * buf) { drm_i810_buf_priv_t *buf_priv = buf->dev_private; int retcode = 0; @@ -180,43 +180,43 @@ static int i810_unmap_buffer(drm_buf_t *buf) (size_t) buf->total); up_write(¤t->mm->mmap_sem); - buf_priv->currently_mapped = I810_BUF_UNMAPPED; - buf_priv->virtual = NULL; + buf_priv->currently_mapped = I810_BUF_UNMAPPED; + buf_priv->virtual = NULL; return retcode; } -static int i810_dma_get_buffer(drm_device_t *dev, drm_i810_dma_t *d, +static int i810_dma_get_buffer(drm_device_t * dev, drm_i810_dma_t * d, struct file *filp) { - drm_buf_t *buf; + drm_buf_t *buf; drm_i810_buf_priv_t *buf_priv; int retcode = 0; buf = i810_freelist_get(dev); if (!buf) { retcode = -ENOMEM; - DRM_DEBUG("retcode=%d\n", retcode); + DRM_DEBUG("retcode=%d\n", retcode); return retcode; } retcode = i810_map_buffer(buf, filp); if (retcode) { i810_freelist_put(dev, buf); - DRM_ERROR("mapbuf failed, retcode %d\n", retcode); + DRM_ERROR("mapbuf failed, retcode %d\n", retcode); return retcode; } buf->filp = filp; buf_priv = buf->dev_private; d->granted = 1; - d->request_idx = buf->idx; - d->request_size = buf->total; - d->virtual = buf_priv->virtual; + d->request_idx = buf->idx; + d->request_size = buf->total; + d->virtual = buf_priv->virtual; return retcode; } -int i810_dma_cleanup(drm_device_t *dev) +int i810_dma_cleanup(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; @@ -229,164 +229,166 @@ int i810_dma_cleanup(drm_device_t *dev) if (dev->dev_private) { int i; - drm_i810_private_t *dev_priv = - (drm_i810_private_t *) dev->dev_private; + drm_i810_private_t *dev_priv = + (drm_i810_private_t *) dev->dev_private; if (dev_priv->ring.virtual_start) { - drm_ioremapfree((void *) dev_priv->ring.virtual_start, - dev_priv->ring.Size, dev); + drm_ioremapfree((void *)dev_priv->ring.virtual_start, + dev_priv->ring.Size, dev); } - if (dev_priv->hw_status_page) { - pci_free_consistent(dev->pdev, PAGE_SIZE, + if (dev_priv->hw_status_page) { + pci_free_consistent(dev->pdev, PAGE_SIZE, dev_priv->hw_status_page, dev_priv->dma_status_page); - /* Need to rewrite hardware status page */ - I810_WRITE(0x02080, 0x1ffff000); + /* Need to rewrite hardware status page */ + I810_WRITE(0x02080, 0x1ffff000); } - drm_free(dev->dev_private, sizeof(drm_i810_private_t), + drm_free(dev->dev_private, sizeof(drm_i810_private_t), DRM_MEM_DRIVER); - dev->dev_private = NULL; + dev->dev_private = NULL; for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; + drm_buf_t *buf = dma->buflist[i]; drm_i810_buf_priv_t *buf_priv = buf->dev_private; - if ( buf_priv->kernel_virtual && buf->total ) - drm_ioremapfree(buf_priv->kernel_virtual, buf->total, dev); + if (buf_priv->kernel_virtual && buf->total) + drm_ioremapfree(buf_priv->kernel_virtual, + buf->total, dev); } } - return 0; + return 0; } -static int i810_wait_ring(drm_device_t *dev, int n) +static int i810_wait_ring(drm_device_t * dev, int n) { - drm_i810_private_t *dev_priv = dev->dev_private; - drm_i810_ring_buffer_t *ring = &(dev_priv->ring); - int iters = 0; - unsigned long end; + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_ring_buffer_t *ring = &(dev_priv->ring); + int iters = 0; + unsigned long end; unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - end = jiffies + (HZ*3); - while (ring->space < n) { - ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - ring->space = ring->head - (ring->tail+8); - if (ring->space < 0) ring->space += ring->Size; - + end = jiffies + (HZ * 3); + while (ring->space < n) { + ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->space = ring->head - (ring->tail + 8); + if (ring->space < 0) + ring->space += ring->Size; + if (ring->head != last_head) { - end = jiffies + (HZ*3); + end = jiffies + (HZ * 3); last_head = ring->head; } - - iters++; + + iters++; if (time_before(end, jiffies)) { - DRM_ERROR("space: %d wanted %d\n", ring->space, n); - DRM_ERROR("lockup\n"); - goto out_wait_ring; + DRM_ERROR("space: %d wanted %d\n", ring->space, n); + DRM_ERROR("lockup\n"); + goto out_wait_ring; } udelay(1); } -out_wait_ring: - return iters; + out_wait_ring: + return iters; } -static void i810_kernel_lost_context(drm_device_t *dev) +static void i810_kernel_lost_context(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; - drm_i810_ring_buffer_t *ring = &(dev_priv->ring); + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_ring_buffer_t *ring = &(dev_priv->ring); - ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - ring->tail = I810_READ(LP_RING + RING_TAIL); - ring->space = ring->head - (ring->tail+8); - if (ring->space < 0) ring->space += ring->Size; + ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->tail = I810_READ(LP_RING + RING_TAIL); + ring->space = ring->head - (ring->tail + 8); + if (ring->space < 0) + ring->space += ring->Size; } -static int i810_freelist_init(drm_device_t *dev, drm_i810_private_t *dev_priv) +static int i810_freelist_init(drm_device_t * dev, drm_i810_private_t * dev_priv) { - drm_device_dma_t *dma = dev->dma; - int my_idx = 24; - u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx); - int i; + drm_device_dma_t *dma = dev->dma; + int my_idx = 24; + u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx); + int i; if (dma->buf_count > 1019) { - /* Not enough space in the status page for the freelist */ - return -EINVAL; + /* Not enough space in the status page for the freelist */ + return -EINVAL; } - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i810_buf_priv_t *buf_priv = buf->dev_private; + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; - buf_priv->in_use = hw_status++; - buf_priv->my_use_idx = my_idx; - my_idx += 4; + buf_priv->in_use = hw_status++; + buf_priv->my_use_idx = my_idx; + my_idx += 4; - *buf_priv->in_use = I810_BUF_FREE; + *buf_priv->in_use = I810_BUF_FREE; buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, - buf->total, dev); + buf->total, dev); } return 0; } -static int i810_dma_initialize(drm_device_t *dev, - drm_i810_private_t *dev_priv, - drm_i810_init_t *init) +static int i810_dma_initialize(drm_device_t * dev, + drm_i810_private_t * dev_priv, + drm_i810_init_t * init) { struct list_head *list; - memset(dev_priv, 0, sizeof(drm_i810_private_t)); + memset(dev_priv, 0, sizeof(drm_i810_private_t)); list_for_each(list, &dev->maplist->head) { drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); if (r_list->map && r_list->map->type == _DRM_SHM && - r_list->map->flags & _DRM_CONTAINS_LOCK ) { + r_list->map->flags & _DRM_CONTAINS_LOCK) { dev_priv->sarea_map = r_list->map; - break; - } - } + break; + } + } if (!dev_priv->sarea_map) { dev->dev_private = (void *)dev_priv; - i810_dma_cleanup(dev); - DRM_ERROR("can not find sarea!\n"); - return -EINVAL; + i810_dma_cleanup(dev); + DRM_ERROR("can not find sarea!\n"); + return -EINVAL; } dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); if (!dev_priv->mmio_map) { dev->dev_private = (void *)dev_priv; - i810_dma_cleanup(dev); - DRM_ERROR("can not find mmio map!\n"); - return -EINVAL; + i810_dma_cleanup(dev); + DRM_ERROR("can not find mmio map!\n"); + return -EINVAL; } dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); if (!dev->agp_buffer_map) { dev->dev_private = (void *)dev_priv; - i810_dma_cleanup(dev); - DRM_ERROR("can not find dma buffer map!\n"); - return -EINVAL; + i810_dma_cleanup(dev); + DRM_ERROR("can not find dma buffer map!\n"); + return -EINVAL; } dev_priv->sarea_priv = (drm_i810_sarea_t *) - ((u8 *)dev_priv->sarea_map->handle + - init->sarea_priv_offset); + ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset); - dev_priv->ring.Start = init->ring_start; - dev_priv->ring.End = init->ring_end; - dev_priv->ring.Size = init->ring_size; + dev_priv->ring.Start = init->ring_start; + dev_priv->ring.End = init->ring_end; + dev_priv->ring.Size = init->ring_size; - dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + - init->ring_start, - init->ring_size, dev); + dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + + init->ring_start, + init->ring_size, dev); - if (dev_priv->ring.virtual_start == NULL) { - dev->dev_private = (void *) dev_priv; - i810_dma_cleanup(dev); - DRM_ERROR("can not ioremap virtual address for" + if (dev_priv->ring.virtual_start == NULL) { + dev->dev_private = (void *)dev_priv; + i810_dma_cleanup(dev); + DRM_ERROR("can not ioremap virtual address for" " ring buffer\n"); - return -ENOMEM; + return -ENOMEM; } - dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; + dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; dev_priv->w = init->w; dev_priv->h = init->h; @@ -402,33 +404,33 @@ static int i810_dma_initialize(drm_device_t *dev, dev_priv->back_di1 = init->back_offset | init->pitch_bits; dev_priv->zi1 = init->depth_offset | init->pitch_bits; - /* Program Hardware Status Page */ - dev_priv->hw_status_page = - pci_alloc_consistent(dev->pdev, PAGE_SIZE, - &dev_priv->dma_status_page); - if (!dev_priv->hw_status_page) { + /* Program Hardware Status Page */ + dev_priv->hw_status_page = + pci_alloc_consistent(dev->pdev, PAGE_SIZE, + &dev_priv->dma_status_page); + if (!dev_priv->hw_status_page) { dev->dev_private = (void *)dev_priv; i810_dma_cleanup(dev); DRM_ERROR("Can not allocate hardware status page\n"); return -ENOMEM; } - memset(dev_priv->hw_status_page, 0, PAGE_SIZE); - DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); + memset(dev_priv->hw_status_page, 0, PAGE_SIZE); + DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); I810_WRITE(0x02080, dev_priv->dma_status_page); - DRM_DEBUG("Enabled hardware status page\n"); + DRM_DEBUG("Enabled hardware status page\n"); - /* Now we need to init our freelist */ + /* Now we need to init our freelist */ if (i810_freelist_init(dev, dev_priv) != 0) { dev->dev_private = (void *)dev_priv; - i810_dma_cleanup(dev); - DRM_ERROR("Not enough space in the status page for" + i810_dma_cleanup(dev); + DRM_ERROR("Not enough space in the status page for" " the freelist\n"); - return -ENOMEM; + return -ENOMEM; } dev->dev_private = (void *)dev_priv; - return 0; + return 0; } /* i810 DRM version 1.1 used a smaller init structure with different @@ -442,12 +444,12 @@ static int i810_dma_initialize(drm_device_t *dev, * If it isn't then we have a v1.1 client. Fix up params. * If it is, then we have a 1.2 client... get the rest of the data. */ -int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg) +int i810_dma_init_compat(drm_i810_init_t * init, unsigned long arg) { /* Get v1.1 init data */ - if (copy_from_user(init, (drm_i810_pre12_init_t __user *)arg, - sizeof(drm_i810_pre12_init_t))) { + if (copy_from_user(init, (drm_i810_pre12_init_t __user *) arg, + sizeof(drm_i810_pre12_init_t))) { return -EFAULT; } @@ -455,7 +457,7 @@ int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg) /* This is a v1.2 client, just get the v1.2 init data */ DRM_INFO("Using POST v1.2 init.\n"); - if (copy_from_user(init, (drm_i810_init_t __user *)arg, + if (copy_from_user(init, (drm_i810_init_t __user *) arg, sizeof(drm_i810_init_t))) { return -EFAULT; } @@ -463,12 +465,12 @@ int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg) /* This is a v1.1 client, fix the params */ DRM_INFO("Using PRE v1.2 init.\n"); - init->pitch_bits = init->h; - init->pitch = init->w; - init->h = init->overlay_physical; - init->w = init->overlay_offset; - init->overlay_physical = 0; - init->overlay_offset = 0; + init->pitch_bits = init->h; + init->pitch = init->w; + init->h = init->overlay_physical; + init->w = init->overlay_offset; + init->overlay_physical = 0; + init->overlay_offset = 0; } return 0; @@ -477,232 +479,225 @@ int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg) int i810_dma_init(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_i810_private_t *dev_priv; - drm_i810_init_t init; - int retcode = 0; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i810_private_t *dev_priv; + drm_i810_init_t init; + int retcode = 0; /* Get only the init func */ - if (copy_from_user(&init, (void __user *)arg, sizeof(drm_i810_init_func_t))) + if (copy_from_user + (&init, (void __user *)arg, sizeof(drm_i810_init_func_t))) return -EFAULT; - switch(init.func) { - case I810_INIT_DMA: - /* This case is for backward compatibility. It - * handles XFree 4.1.0 and 4.2.0, and has to - * do some parameter checking as described below. - * It will someday go away. - */ - retcode = i810_dma_init_compat(&init, arg); - if (retcode) - return retcode; - - dev_priv = drm_alloc(sizeof(drm_i810_private_t), - DRM_MEM_DRIVER); - if (dev_priv == NULL) - return -ENOMEM; - retcode = i810_dma_initialize(dev, dev_priv, &init); - break; - - default: - case I810_INIT_DMA_1_4: - DRM_INFO("Using v1.4 init.\n"); - if (copy_from_user(&init, (drm_i810_init_t __user *)arg, - sizeof(drm_i810_init_t))) { - return -EFAULT; - } - dev_priv = drm_alloc(sizeof(drm_i810_private_t), - DRM_MEM_DRIVER); - if (dev_priv == NULL) - return -ENOMEM; - retcode = i810_dma_initialize(dev, dev_priv, &init); - break; - - case I810_CLEANUP_DMA: - DRM_INFO("DMA Cleanup\n"); - retcode = i810_dma_cleanup(dev); - break; + switch (init.func) { + case I810_INIT_DMA: + /* This case is for backward compatibility. It + * handles XFree 4.1.0 and 4.2.0, and has to + * do some parameter checking as described below. + * It will someday go away. + */ + retcode = i810_dma_init_compat(&init, arg); + if (retcode) + return retcode; + + dev_priv = drm_alloc(sizeof(drm_i810_private_t), + DRM_MEM_DRIVER); + if (dev_priv == NULL) + return -ENOMEM; + retcode = i810_dma_initialize(dev, dev_priv, &init); + break; + + default: + case I810_INIT_DMA_1_4: + DRM_INFO("Using v1.4 init.\n"); + if (copy_from_user(&init, (drm_i810_init_t __user *) arg, + sizeof(drm_i810_init_t))) { + return -EFAULT; + } + dev_priv = drm_alloc(sizeof(drm_i810_private_t), + DRM_MEM_DRIVER); + if (dev_priv == NULL) + return -ENOMEM; + retcode = i810_dma_initialize(dev, dev_priv, &init); + break; + + case I810_CLEANUP_DMA: + DRM_INFO("DMA Cleanup\n"); + retcode = i810_dma_cleanup(dev); + break; } - return retcode; + return retcode; } - - /* Most efficient way to verify state for the i810 is as it is * emitted. Non-conformant state is silently dropped. * * Use 'volatile' & local var tmp to force the emitted values to be * identical to the verified ones. */ -static void i810EmitContextVerified( drm_device_t *dev, - volatile unsigned int *code ) +static void i810EmitContextVerified(drm_device_t * dev, + volatile unsigned int *code) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; - BEGIN_LP_RING( I810_CTX_SETUP_SIZE ); + BEGIN_LP_RING(I810_CTX_SETUP_SIZE); - OUT_RING( GFX_OP_COLOR_FACTOR ); - OUT_RING( code[I810_CTXREG_CF1] ); + OUT_RING(GFX_OP_COLOR_FACTOR); + OUT_RING(code[I810_CTXREG_CF1]); - OUT_RING( GFX_OP_STIPPLE ); - OUT_RING( code[I810_CTXREG_ST1] ); + OUT_RING(GFX_OP_STIPPLE); + OUT_RING(code[I810_CTXREG_ST1]); - for ( i = 4 ; i < I810_CTX_SETUP_SIZE ; i++ ) { + for (i = 4; i < I810_CTX_SETUP_SIZE; i++) { tmp = code[i]; - if ((tmp & (7<<29)) == (3<<29) && - (tmp & (0x1f<<24)) < (0x1d<<24)) - { - OUT_RING( tmp ); + if ((tmp & (7 << 29)) == (3 << 29) && + (tmp & (0x1f << 24)) < (0x1d << 24)) { + OUT_RING(tmp); j++; - } - else printk("constext state dropped!!!\n"); + } else + printk("constext state dropped!!!\n"); } if (j & 1) - OUT_RING( 0 ); + OUT_RING(0); ADVANCE_LP_RING(); } -static void i810EmitTexVerified( drm_device_t *dev, - volatile unsigned int *code ) +static void i810EmitTexVerified(drm_device_t * dev, volatile unsigned int *code) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; - BEGIN_LP_RING( I810_TEX_SETUP_SIZE ); + BEGIN_LP_RING(I810_TEX_SETUP_SIZE); - OUT_RING( GFX_OP_MAP_INFO ); - OUT_RING( code[I810_TEXREG_MI1] ); - OUT_RING( code[I810_TEXREG_MI2] ); - OUT_RING( code[I810_TEXREG_MI3] ); + OUT_RING(GFX_OP_MAP_INFO); + OUT_RING(code[I810_TEXREG_MI1]); + OUT_RING(code[I810_TEXREG_MI2]); + OUT_RING(code[I810_TEXREG_MI3]); - for ( i = 4 ; i < I810_TEX_SETUP_SIZE ; i++ ) { + for (i = 4; i < I810_TEX_SETUP_SIZE; i++) { tmp = code[i]; - if ((tmp & (7<<29)) == (3<<29) && - (tmp & (0x1f<<24)) < (0x1d<<24)) - { - OUT_RING( tmp ); + if ((tmp & (7 << 29)) == (3 << 29) && + (tmp & (0x1f << 24)) < (0x1d << 24)) { + OUT_RING(tmp); j++; - } - else printk("texture state dropped!!!\n"); + } else + printk("texture state dropped!!!\n"); } if (j & 1) - OUT_RING( 0 ); + OUT_RING(0); ADVANCE_LP_RING(); } - /* Need to do some additional checking when setting the dest buffer. */ -static void i810EmitDestVerified( drm_device_t *dev, - volatile unsigned int *code ) +static void i810EmitDestVerified(drm_device_t * dev, + volatile unsigned int *code) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; unsigned int tmp; RING_LOCALS; - BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 ); + BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2); tmp = code[I810_DESTREG_DI1]; if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { - OUT_RING( CMD_OP_DESTBUFFER_INFO ); - OUT_RING( tmp ); + OUT_RING(CMD_OP_DESTBUFFER_INFO); + OUT_RING(tmp); } else - DRM_DEBUG("bad di1 %x (allow %x or %x)\n", - tmp, dev_priv->front_di1, dev_priv->back_di1); + DRM_DEBUG("bad di1 %x (allow %x or %x)\n", + tmp, dev_priv->front_di1, dev_priv->back_di1); /* invarient: */ - OUT_RING( CMD_OP_Z_BUFFER_INFO ); - OUT_RING( dev_priv->zi1 ); + OUT_RING(CMD_OP_Z_BUFFER_INFO); + OUT_RING(dev_priv->zi1); - OUT_RING( GFX_OP_DESTBUFFER_VARS ); - OUT_RING( code[I810_DESTREG_DV1] ); + OUT_RING(GFX_OP_DESTBUFFER_VARS); + OUT_RING(code[I810_DESTREG_DV1]); - OUT_RING( GFX_OP_DRAWRECT_INFO ); - OUT_RING( code[I810_DESTREG_DR1] ); - OUT_RING( code[I810_DESTREG_DR2] ); - OUT_RING( code[I810_DESTREG_DR3] ); - OUT_RING( code[I810_DESTREG_DR4] ); - OUT_RING( 0 ); + OUT_RING(GFX_OP_DRAWRECT_INFO); + OUT_RING(code[I810_DESTREG_DR1]); + OUT_RING(code[I810_DESTREG_DR2]); + OUT_RING(code[I810_DESTREG_DR3]); + OUT_RING(code[I810_DESTREG_DR4]); + OUT_RING(0); ADVANCE_LP_RING(); } - - -static void i810EmitState( drm_device_t *dev ) +static void i810EmitState(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; - drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; - + DRM_DEBUG("%s %x\n", __FUNCTION__, dirty); if (dirty & I810_UPLOAD_BUFFERS) { - i810EmitDestVerified( dev, sarea_priv->BufferState ); + i810EmitDestVerified(dev, sarea_priv->BufferState); sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS; } if (dirty & I810_UPLOAD_CTX) { - i810EmitContextVerified( dev, sarea_priv->ContextState ); + i810EmitContextVerified(dev, sarea_priv->ContextState); sarea_priv->dirty &= ~I810_UPLOAD_CTX; } if (dirty & I810_UPLOAD_TEX0) { - i810EmitTexVerified( dev, sarea_priv->TexState[0] ); + i810EmitTexVerified(dev, sarea_priv->TexState[0]); sarea_priv->dirty &= ~I810_UPLOAD_TEX0; } if (dirty & I810_UPLOAD_TEX1) { - i810EmitTexVerified( dev, sarea_priv->TexState[1] ); + i810EmitTexVerified(dev, sarea_priv->TexState[1]); sarea_priv->dirty &= ~I810_UPLOAD_TEX1; } } - - /* need to verify */ -static void i810_dma_dispatch_clear( drm_device_t *dev, int flags, - unsigned int clear_color, - unsigned int clear_zval ) +static void i810_dma_dispatch_clear(drm_device_t * dev, int flags, + unsigned int clear_color, + unsigned int clear_zval) { - drm_i810_private_t *dev_priv = dev->dev_private; - drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; int pitch = dev_priv->pitch; int cpp = 2; int i; RING_LOCALS; - - if ( dev_priv->current_page == 1 ) { - unsigned int tmp = flags; - + + if (dev_priv->current_page == 1) { + unsigned int tmp = flags; + flags &= ~(I810_FRONT | I810_BACK); - if (tmp & I810_FRONT) flags |= I810_BACK; - if (tmp & I810_BACK) flags |= I810_FRONT; + if (tmp & I810_FRONT) + flags |= I810_BACK; + if (tmp & I810_BACK) + flags |= I810_FRONT; } - i810_kernel_lost_context(dev); + i810_kernel_lost_context(dev); - if (nbox > I810_NR_SAREA_CLIPRECTS) - nbox = I810_NR_SAREA_CLIPRECTS; + if (nbox > I810_NR_SAREA_CLIPRECTS) + nbox = I810_NR_SAREA_CLIPRECTS; - for (i = 0 ; i < nbox ; i++, pbox++) { + for (i = 0; i < nbox; i++, pbox++) { unsigned int x = pbox->x1; unsigned int y = pbox->y1; unsigned int width = (pbox->x2 - x) * cpp; @@ -711,52 +706,48 @@ static void i810_dma_dispatch_clear( drm_device_t *dev, int flags, if (pbox->x1 > pbox->x2 || pbox->y1 > pbox->y2 || - pbox->x2 > dev_priv->w || - pbox->y2 > dev_priv->h) + pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) continue; - if ( flags & I810_FRONT ) { - BEGIN_LP_RING( 6 ); - OUT_RING( BR00_BITBLT_CLIENT | - BR00_OP_COLOR_BLT | 0x3 ); - OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); - OUT_RING( (height << 16) | width ); - OUT_RING( start ); - OUT_RING( clear_color ); - OUT_RING( 0 ); + if (flags & I810_FRONT) { + BEGIN_LP_RING(6); + OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); + OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); + OUT_RING((height << 16) | width); + OUT_RING(start); + OUT_RING(clear_color); + OUT_RING(0); ADVANCE_LP_RING(); } - if ( flags & I810_BACK ) { - BEGIN_LP_RING( 6 ); - OUT_RING( BR00_BITBLT_CLIENT | - BR00_OP_COLOR_BLT | 0x3 ); - OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); - OUT_RING( (height << 16) | width ); - OUT_RING( dev_priv->back_offset + start ); - OUT_RING( clear_color ); - OUT_RING( 0 ); + if (flags & I810_BACK) { + BEGIN_LP_RING(6); + OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); + OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); + OUT_RING((height << 16) | width); + OUT_RING(dev_priv->back_offset + start); + OUT_RING(clear_color); + OUT_RING(0); ADVANCE_LP_RING(); } - if ( flags & I810_DEPTH ) { - BEGIN_LP_RING( 6 ); - OUT_RING( BR00_BITBLT_CLIENT | - BR00_OP_COLOR_BLT | 0x3 ); - OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); - OUT_RING( (height << 16) | width ); - OUT_RING( dev_priv->depth_offset + start ); - OUT_RING( clear_zval ); - OUT_RING( 0 ); + if (flags & I810_DEPTH) { + BEGIN_LP_RING(6); + OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); + OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); + OUT_RING((height << 16) | width); + OUT_RING(dev_priv->depth_offset + start); + OUT_RING(clear_zval); + OUT_RING(0); ADVANCE_LP_RING(); } } } -static void i810_dma_dispatch_swap( drm_device_t *dev ) +static void i810_dma_dispatch_swap(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; - drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; int pitch = dev_priv->pitch; @@ -766,75 +757,71 @@ static void i810_dma_dispatch_swap( drm_device_t *dev ) DRM_DEBUG("swapbuffers\n"); - i810_kernel_lost_context(dev); + i810_kernel_lost_context(dev); - if (nbox > I810_NR_SAREA_CLIPRECTS) - nbox = I810_NR_SAREA_CLIPRECTS; + if (nbox > I810_NR_SAREA_CLIPRECTS) + nbox = I810_NR_SAREA_CLIPRECTS; - for (i = 0 ; i < nbox; i++, pbox++) - { + for (i = 0; i < nbox; i++, pbox++) { unsigned int w = pbox->x2 - pbox->x1; unsigned int h = pbox->y2 - pbox->y1; - unsigned int dst = pbox->x1*cpp + pbox->y1*pitch; + unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch; unsigned int start = dst; if (pbox->x1 > pbox->x2 || pbox->y1 > pbox->y2 || - pbox->x2 > dev_priv->w || - pbox->y2 > dev_priv->h) + pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) continue; - BEGIN_LP_RING( 6 ); - OUT_RING( BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4 ); - OUT_RING( pitch | (0xCC << 16)); - OUT_RING( (h << 16) | (w * cpp)); + BEGIN_LP_RING(6); + OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4); + OUT_RING(pitch | (0xCC << 16)); + OUT_RING((h << 16) | (w * cpp)); if (dev_priv->current_page == 0) - OUT_RING(dev_priv->front_offset + start); + OUT_RING(dev_priv->front_offset + start); else - OUT_RING(dev_priv->back_offset + start); - OUT_RING( pitch ); + OUT_RING(dev_priv->back_offset + start); + OUT_RING(pitch); if (dev_priv->current_page == 0) - OUT_RING(dev_priv->back_offset + start); + OUT_RING(dev_priv->back_offset + start); else - OUT_RING(dev_priv->front_offset + start); + OUT_RING(dev_priv->front_offset + start); ADVANCE_LP_RING(); } } - -static void i810_dma_dispatch_vertex(drm_device_t *dev, - drm_buf_t *buf, - int discard, - int used) +static void i810_dma_dispatch_vertex(drm_device_t * dev, + drm_buf_t * buf, int discard, int used) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; drm_i810_buf_priv_t *buf_priv = buf->dev_private; - drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_clip_rect_t *box = sarea_priv->boxes; - int nbox = sarea_priv->nbox; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_clip_rect_t *box = sarea_priv->boxes; + int nbox = sarea_priv->nbox; unsigned long address = (unsigned long)buf->bus_address; unsigned long start = address - dev->agp->base; int i = 0; - RING_LOCALS; + RING_LOCALS; - i810_kernel_lost_context(dev); + i810_kernel_lost_context(dev); - if (nbox > I810_NR_SAREA_CLIPRECTS) + if (nbox > I810_NR_SAREA_CLIPRECTS) nbox = I810_NR_SAREA_CLIPRECTS; - if (used > 4*1024) + if (used > 4 * 1024) used = 0; if (sarea_priv->dirty) - i810EmitState( dev ); + i810EmitState(dev); if (buf_priv->currently_mapped == I810_BUF_MAPPED) { unsigned int prim = (sarea_priv->vertex_prim & PR_MASK); - *(u32 *)buf_priv->kernel_virtual = ((GFX_OP_PRIMITIVE | prim | ((used/4)-2))); + *(u32 *) buf_priv->kernel_virtual = + ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2))); if (used & 4) { - *(u32 *)((u32)buf_priv->kernel_virtual + used) = 0; + *(u32 *) ((u32) buf_priv->kernel_virtual + used) = 0; used += 4; } @@ -845,19 +832,20 @@ static void i810_dma_dispatch_vertex(drm_device_t *dev, do { if (i < nbox) { BEGIN_LP_RING(4); - OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | - SC_ENABLE ); - OUT_RING( GFX_OP_SCISSOR_INFO ); - OUT_RING( box[i].x1 | (box[i].y1<<16) ); - OUT_RING( (box[i].x2-1) | ((box[i].y2-1)<<16) ); + OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | + SC_ENABLE); + OUT_RING(GFX_OP_SCISSOR_INFO); + OUT_RING(box[i].x1 | (box[i].y1 << 16)); + OUT_RING((box[i].x2 - + 1) | ((box[i].y2 - 1) << 16)); ADVANCE_LP_RING(); } BEGIN_LP_RING(4); - OUT_RING( CMD_OP_BATCH_BUFFER ); - OUT_RING( start | BB1_PROTECTED ); - OUT_RING( start + used - 4 ); - OUT_RING( 0 ); + OUT_RING(CMD_OP_BATCH_BUFFER); + OUT_RING(start | BB1_PROTECTED); + OUT_RING(start + used - 4); + OUT_RING(0); ADVANCE_LP_RING(); } while (++i < nbox); @@ -866,59 +854,59 @@ static void i810_dma_dispatch_vertex(drm_device_t *dev, if (discard) { dev_priv->counter++; - (void) cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, - I810_BUF_HARDWARE); + (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, + I810_BUF_HARDWARE); BEGIN_LP_RING(8); - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( 20 ); - OUT_RING( dev_priv->counter ); - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( buf_priv->my_use_idx ); - OUT_RING( I810_BUF_FREE ); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(20); + OUT_RING(dev_priv->counter); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(buf_priv->my_use_idx); + OUT_RING(I810_BUF_FREE); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); ADVANCE_LP_RING(); } } -static void i810_dma_dispatch_flip( drm_device_t *dev ) +static void i810_dma_dispatch_flip(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; int pitch = dev_priv->pitch; RING_LOCALS; - DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", - __FUNCTION__, - dev_priv->current_page, - dev_priv->sarea_priv->pf_current_page); - - i810_kernel_lost_context(dev); + DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, + dev_priv->sarea_priv->pf_current_page); + + i810_kernel_lost_context(dev); - BEGIN_LP_RING( 2 ); - OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); - OUT_RING( 0 ); + BEGIN_LP_RING(2); + OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); + OUT_RING(0); ADVANCE_LP_RING(); - BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 ); + BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2); /* On i815 at least ASYNC is buggy */ /* pitch<<5 is from 11.2.8 p158, its the pitch / 8 then left shifted 8, so (pitch >> 3) << 8 */ - OUT_RING( CMD_OP_FRONTBUFFER_INFO | (pitch<<5) /*| ASYNC_FLIP */ ); - if ( dev_priv->current_page == 0 ) { - OUT_RING( dev_priv->back_offset ); + OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ ); + if (dev_priv->current_page == 0) { + OUT_RING(dev_priv->back_offset); dev_priv->current_page = 1; } else { - OUT_RING( dev_priv->front_offset ); + OUT_RING(dev_priv->front_offset); dev_priv->current_page = 0; } OUT_RING(0); ADVANCE_LP_RING(); BEGIN_LP_RING(2); - OUT_RING( CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP ); - OUT_RING( 0 ); + OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP); + OUT_RING(0); ADVANCE_LP_RING(); /* Increment the frame counter. The client-side 3D driver must @@ -929,46 +917,46 @@ static void i810_dma_dispatch_flip( drm_device_t *dev ) } -void i810_dma_quiescent(drm_device_t *dev) +void i810_dma_quiescent(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; - RING_LOCALS; + drm_i810_private_t *dev_priv = dev->dev_private; + RING_LOCALS; /* printk("%s\n", __FUNCTION__); */ - i810_kernel_lost_context(dev); + i810_kernel_lost_context(dev); - BEGIN_LP_RING(4); - OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); - OUT_RING( 0 ); - ADVANCE_LP_RING(); + BEGIN_LP_RING(4); + OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); + OUT_RING(0); + ADVANCE_LP_RING(); - i810_wait_ring( dev, dev_priv->ring.Size - 8 ); + i810_wait_ring(dev, dev_priv->ring.Size - 8); } -static int i810_flush_queue(drm_device_t *dev) +static int i810_flush_queue(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; - int i, ret = 0; - RING_LOCALS; - + int i, ret = 0; + RING_LOCALS; + /* printk("%s\n", __FUNCTION__); */ - i810_kernel_lost_context(dev); + i810_kernel_lost_context(dev); - BEGIN_LP_RING(2); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); - ADVANCE_LP_RING(); + BEGIN_LP_RING(2); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); + ADVANCE_LP_RING(); - i810_wait_ring( dev, dev_priv->ring.Size - 8 ); + i810_wait_ring(dev, dev_priv->ring.Size - 8); - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i810_buf_priv_t *buf_priv = buf->dev_private; + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE, I810_BUF_FREE); @@ -979,26 +967,29 @@ static int i810_flush_queue(drm_device_t *dev) DRM_DEBUG("still on client\n"); } - return ret; + return ret; } /* Must be called with the lock held */ void i810_reclaim_buffers(struct file *filp) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_device_dma_t *dma = dev->dma; - int i; + int i; - if (!dma) return; - if (!dev->dev_private) return; - if (!dma->buflist) return; + if (!dma) + return; + if (!dev->dev_private) + return; + if (!dma->buflist) + return; - i810_flush_queue(dev); + i810_flush_queue(dev); for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i810_buf_priv_t *buf_priv = buf->dev_private; + drm_buf_t *buf = dma->buflist[i]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; if (buf->filp == filp && buf_priv) { int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, @@ -1007,7 +998,7 @@ void i810_reclaim_buffers(struct file *filp) if (used == I810_BUF_CLIENT) DRM_DEBUG("reclaimed from client\n"); if (buf_priv->currently_mapped == I810_BUF_MAPPED) - buf_priv->currently_mapped = I810_BUF_UNMAPPED; + buf_priv->currently_mapped = I810_BUF_UNMAPPED; } } } @@ -1015,32 +1006,32 @@ void i810_reclaim_buffers(struct file *filp) int i810_flush_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i810_flush_ioctl called without lock held\n"); return -EINVAL; } - i810_flush_queue(dev); - return 0; + i810_flush_queue(dev); + return 0; } - int i810_dma_vertex(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_device_dma_t *dma = dev->dma; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) - dev_priv->sarea_priv; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; drm_i810_vertex_t vertex; - if (copy_from_user(&vertex, (drm_i810_vertex_t __user *)arg, sizeof(vertex))) + if (copy_from_user + (&vertex, (drm_i810_vertex_t __user *) arg, sizeof(vertex))) return -EFAULT; if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { @@ -1051,31 +1042,30 @@ int i810_dma_vertex(struct inode *inode, struct file *filp, DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n", vertex.idx, vertex.used, vertex.discard); - if (vertex.idx < 0 || vertex.idx > dma->buf_count) + if (vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL; - i810_dma_dispatch_vertex( dev, - dma->buflist[ vertex.idx ], - vertex.discard, vertex.used ); + i810_dma_dispatch_vertex(dev, + dma->buflist[vertex.idx], + vertex.discard, vertex.used); - atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]); + atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]); atomic_inc(&dev->counts[_DRM_STAT_DMA]); - sarea_priv->last_enqueue = dev_priv->counter-1; - sarea_priv->last_dispatch = (int) hw_status[5]; + sarea_priv->last_enqueue = dev_priv->counter - 1; + sarea_priv->last_dispatch = (int)hw_status[5]; return 0; } - - int i810_clear_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i810_clear_t clear; - if (copy_from_user(&clear, (drm_i810_clear_t __user *)arg, sizeof(clear))) + if (copy_from_user + (&clear, (drm_i810_clear_t __user *) arg, sizeof(clear))) return -EFAULT; if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { @@ -1083,19 +1073,18 @@ int i810_clear_bufs(struct inode *inode, struct file *filp, return -EINVAL; } - /* GH: Someone's doing nasty things... */ - if (!dev->dev_private) { - return -EINVAL; - } + /* GH: Someone's doing nasty things... */ + if (!dev->dev_private) { + return -EINVAL; + } - i810_dma_dispatch_clear( dev, clear.flags, - clear.clear_color, - clear.clear_depth ); - return 0; + i810_dma_dispatch_clear(dev, clear.flags, + clear.clear_color, clear.clear_depth); + return 0; } int i810_swap_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; @@ -1107,37 +1096,37 @@ int i810_swap_bufs(struct inode *inode, struct file *filp, return -EINVAL; } - i810_dma_dispatch_swap( dev ); - return 0; + i810_dma_dispatch_swap(dev); + return 0; } int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) - dev_priv->sarea_priv; - - sarea_priv->last_dispatch = (int) hw_status[5]; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + + sarea_priv->last_dispatch = (int)hw_status[5]; return 0; } int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - int retcode = 0; - drm_i810_dma_t d; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) - dev_priv->sarea_priv; - - if (copy_from_user(&d, (drm_i810_dma_t __user *)arg, sizeof(d))) + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode = 0; + drm_i810_dma_t d; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + + if (copy_from_user(&d, (drm_i810_dma_t __user *) arg, sizeof(d))) return -EFAULT; if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { @@ -1152,17 +1141,15 @@ int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n", current->pid, retcode, d.granted); - if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d))) + if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d))) return -EFAULT; - sarea_priv->last_dispatch = (int) hw_status[5]; + sarea_priv->last_dispatch = (int)hw_status[5]; return retcode; } int i810_copybuf(struct inode *inode, - struct file *filp, - unsigned int cmd, - unsigned long arg) + struct file *filp, unsigned int cmd, unsigned long arg) { /* Never copy - 2.4.x doesn't need it */ return 0; @@ -1175,8 +1162,8 @@ int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd, return 0; } -static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used, - unsigned int last_render) +static void i810_dma_dispatch_mc(drm_device_t * dev, drm_buf_t * buf, int used, + unsigned int last_render) { drm_i810_private_t *dev_priv = dev->dev_private; drm_i810_buf_priv_t *buf_priv = buf->dev_private; @@ -1188,19 +1175,17 @@ static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used, i810_kernel_lost_context(dev); - u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, - I810_BUF_HARDWARE); + u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE); if (u != I810_BUF_CLIENT) { DRM_DEBUG("MC found buffer that isn't mine!\n"); } - if (used > 4*1024) + if (used > 4 * 1024) used = 0; sarea_priv->dirty = 0x7f; - DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", - address, used); + DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", address, used); dev_priv->counter++; DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter); @@ -1211,46 +1196,45 @@ static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used, if (buf_priv->currently_mapped == I810_BUF_MAPPED) { if (used & 4) { - *(u32 *)((u32)buf_priv->virtual + used) = 0; + *(u32 *) ((u32) buf_priv->virtual + used) = 0; used += 4; } i810_unmap_buffer(buf); } BEGIN_LP_RING(4); - OUT_RING( CMD_OP_BATCH_BUFFER ); - OUT_RING( start | BB1_PROTECTED ); - OUT_RING( start + used - 4 ); - OUT_RING( 0 ); + OUT_RING(CMD_OP_BATCH_BUFFER); + OUT_RING(start | BB1_PROTECTED); + OUT_RING(start + used - 4); + OUT_RING(0); ADVANCE_LP_RING(); - BEGIN_LP_RING(8); - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( buf_priv->my_use_idx ); - OUT_RING( I810_BUF_FREE ); - OUT_RING( 0 ); - - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( 16 ); - OUT_RING( last_render ); - OUT_RING( 0 ); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(buf_priv->my_use_idx); + OUT_RING(I810_BUF_FREE); + OUT_RING(0); + + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(16); + OUT_RING(last_render); + OUT_RING(0); ADVANCE_LP_RING(); } int i810_dma_mc(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_device_dma_t *dma = dev->dma; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; u32 *hw_status = dev_priv->hw_status_page; drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) - dev_priv->sarea_priv; + dev_priv->sarea_priv; drm_i810_mc_t mc; - if (copy_from_user(&mc, (drm_i810_mc_t __user *)arg, sizeof(mc))) + if (copy_from_user(&mc, (drm_i810_mc_t __user *) arg, sizeof(mc))) return -EFAULT; if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { @@ -1262,47 +1246,48 @@ int i810_dma_mc(struct inode *inode, struct file *filp, return -EINVAL; i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used, - mc.last_render ); + mc.last_render); atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]); atomic_inc(&dev->counts[_DRM_STAT_DMA]); - sarea_priv->last_enqueue = dev_priv->counter-1; - sarea_priv->last_dispatch = (int) hw_status[5]; + sarea_priv->last_enqueue = dev_priv->counter - 1; + sarea_priv->last_dispatch = (int)hw_status[5]; return 0; } int i810_rstatus(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; - return (int)(((u32 *)(dev_priv->hw_status_page))[4]); + return (int)(((u32 *) (dev_priv->hw_status_page))[4]); } int i810_ov0_info(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; drm_i810_overlay_t data; data.offset = dev_priv->overlay_offset; data.physical = dev_priv->overlay_physical; - if (copy_to_user((drm_i810_overlay_t __user *)arg,&data,sizeof(data))) + if (copy_to_user + ((drm_i810_overlay_t __user *) arg, &data, sizeof(data))) return -EFAULT; return 0; } int i810_fstatus(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i810_fstatus called without lock held\n"); @@ -1312,43 +1297,41 @@ int i810_fstatus(struct inode *inode, struct file *filp, } int i810_ov0_flip(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i810_ov0_flip called without lock held\n"); return -EINVAL; } - //Tell the overlay to update - I810_WRITE(0x30000,dev_priv->overlay_physical | 0x80000000); + I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000); return 0; } - /* Not sure why this isn't set all the time: - */ -static void i810_do_init_pageflip( drm_device_t *dev ) + */ +static void i810_do_init_pageflip(drm_device_t * dev) { drm_i810_private_t *dev_priv = dev->dev_private; - + DRM_DEBUG("%s\n", __FUNCTION__); dev_priv->page_flipping = 1; dev_priv->current_page = 0; dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; } -int i810_do_cleanup_pageflip( drm_device_t *dev ) +int i810_do_cleanup_pageflip(drm_device_t * dev) { drm_i810_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); if (dev_priv->current_page != 0) - i810_dma_dispatch_flip( dev ); + i810_dma_dispatch_flip(dev); dev_priv->page_flipping = 0; return 0; @@ -1368,25 +1351,25 @@ int i810_flip_bufs(struct inode *inode, struct file *filp, return -EINVAL; } - if (!dev_priv->page_flipping) - i810_do_init_pageflip( dev ); + if (!dev_priv->page_flipping) + i810_do_init_pageflip(dev); - i810_dma_dispatch_flip( dev ); - return 0; + i810_dma_dispatch_flip(dev); + return 0; } -void i810_driver_pretakedown(drm_device_t *dev) +void i810_driver_pretakedown(drm_device_t * dev) { - i810_dma_cleanup( dev ); + i810_dma_cleanup(dev); } -void i810_driver_release(drm_device_t *dev, struct file *filp) +void i810_driver_release(drm_device_t * dev, struct file *filp) { i810_reclaim_buffers(filp); } -int i810_driver_dma_quiescent(drm_device_t *dev) +int i810_driver_dma_quiescent(drm_device_t * dev) { - i810_dma_quiescent( dev ); + i810_dma_quiescent(dev); return 0; } diff --git a/linux-core/i810_drm.h b/linux-core/i810_drm.h index 95703f3d..beec4a2a 100644 --- a/linux-core/i810_drm.h +++ b/linux-core/i810_drm.h @@ -19,21 +19,20 @@ #define I810_LOG_MIN_TEX_REGION_SIZE 16 #endif -#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ -#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ +#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ +#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ #define I810_UPLOAD_CTX 0x4 #define I810_UPLOAD_BUFFERS 0x8 #define I810_UPLOAD_TEX0 0x10 #define I810_UPLOAD_TEX1 0x20 #define I810_UPLOAD_CLIPRECTS 0x40 - /* Indices into buf.Setup where various bits of state are mirrored per * context and per buffer. These can be fired at the card as a unit, * or in a piecewise fashion as required. */ -/* Destbuffer state +/* Destbuffer state * - backbuffer linear offset and pitch -- invarient in the current dri * - zbuffer linear offset and pitch -- also invarient * - drawing origin in back and depth buffers. @@ -55,13 +54,13 @@ /* Context state */ #define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ -#define I810_CTXREG_CF1 1 -#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ +#define I810_CTXREG_CF1 1 +#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ #define I810_CTXREG_ST1 3 #define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ #define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ #define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ -#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ +#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ #define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ #define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ #define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ @@ -74,14 +73,14 @@ #define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ #define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ #define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ -#define I810_CTX_SETUP_SIZE 20 +#define I810_CTX_SETUP_SIZE 20 /* Texture state (per tex unit) */ #define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ -#define I810_TEXREG_MI1 1 -#define I810_TEXREG_MI2 2 -#define I810_TEXREG_MI3 3 +#define I810_TEXREG_MI1 1 +#define I810_TEXREG_MI2 2 +#define I810_TEXREG_MI3 3 #define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ #define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ #define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ @@ -98,7 +97,7 @@ typedef enum _drm_i810_init_func { I810_INIT_DMA = 0x01, I810_CLEANUP_DMA = 0x02, I810_INIT_DMA_1_4 = 0x03 - } drm_i810_init_func_t; +} drm_i810_init_func_t; /* This is the init structure after v1.2 */ typedef struct _drm_i810_init { @@ -122,17 +121,17 @@ typedef struct _drm_i810_init { unsigned int w; unsigned int h; unsigned int pitch; - unsigned int pitch_bits; + unsigned int pitch_bits; } drm_i810_init_t; /* This is the init structure prior to v1.2 */ typedef struct _drm_i810_pre12_init { - drm_i810_init_func_t func; + drm_i810_init_func_t func; #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) int ring_map_idx; int buffer_map_idx; #else - unsigned int mmio_offset; + unsigned int mmio_offset; unsigned int buffers_offset; #endif int sarea_priv_offset; @@ -145,23 +144,23 @@ typedef struct _drm_i810_pre12_init { unsigned int w; unsigned int h; unsigned int pitch; - unsigned int pitch_bits; + unsigned int pitch_bits; } drm_i810_pre12_init_t; /* Warning: If you change the SAREA structure you must change the Xserver * structure as well */ typedef struct _drm_i810_tex_region { - unsigned char next, prev; /* indices to form a circular LRU */ + unsigned char next, prev; /* indices to form a circular LRU */ unsigned char in_use; /* owned by a client, or free? */ int age; /* tracked by clients to update local LRU's */ } drm_i810_tex_region_t; typedef struct _drm_i810_sarea { - unsigned int ContextState[I810_CTX_SETUP_SIZE]; - unsigned int BufferState[I810_DEST_SETUP_SIZE]; - unsigned int TexState[2][I810_TEX_SETUP_SIZE]; - unsigned int dirty; + unsigned int ContextState[I810_CTX_SETUP_SIZE]; + unsigned int BufferState[I810_DEST_SETUP_SIZE]; + unsigned int TexState[2][I810_TEX_SETUP_SIZE]; + unsigned int dirty; unsigned int nbox; drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS]; @@ -179,22 +178,22 @@ typedef struct _drm_i810_sarea { * texture space, and can make informed decisions as to which * areas to kick out. There is no need to choose whether to * kick out your own texture or someone else's - simply eject - * them all in LRU order. + * them all in LRU order. */ - - drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS+1]; - /* Last elt is sentinal */ - int texAge; /* last time texture was uploaded */ - int last_enqueue; /* last time a buffer was enqueued */ + + drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1]; + /* Last elt is sentinal */ + int texAge; /* last time texture was uploaded */ + int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ - int last_quiescent; /* */ + int last_quiescent; /* */ int ctxOwner; /* last context to upload state */ int vertex_prim; - int pf_enabled; /* is pageflipping allowed? */ + int pf_enabled; /* is pageflipping allowed? */ int pf_active; - int pf_current_page; /* which buffer is being displayed? */ + int pf_current_page; /* which buffer is being displayed? */ } drm_i810_sarea_t; /* WARNING: If you change any of these defines, make sure to change the @@ -248,13 +247,13 @@ typedef struct _drm_i810_clear { * new set of cliprects. */ typedef struct _drm_i810_vertex { - int idx; /* buffer index */ + int idx; /* buffer index */ int used; /* nr bytes in use */ int discard; /* client is finished with the buffer? */ } drm_i810_vertex_t; typedef struct _drm_i810_copy_t { - int idx; /* buffer index */ + int idx; /* buffer index */ int used; /* nr bytes in use */ void *address; /* Address to copy from */ } drm_i810_copy_t; @@ -269,7 +268,6 @@ typedef struct _drm_i810_copy_t { #define PR_RECTS (0x7<<18) #define PR_MASK (0x7<<18) - typedef struct drm_i810_dma { void *virtual; int request_idx; @@ -278,17 +276,16 @@ typedef struct drm_i810_dma { } drm_i810_dma_t; typedef struct _drm_i810_overlay_t { - unsigned int offset; /* Address of the Overlay Regs */ + unsigned int offset; /* Address of the Overlay Regs */ unsigned int physical; } drm_i810_overlay_t; typedef struct _drm_i810_mc { - int idx; /* buffer index */ - int used; /* nr bytes in use */ - int num_blocks; /* number of GFXBlocks */ - int *length; /* List of lengths for GFXBlocks (FUTURE)*/ - unsigned int last_render; /* Last Render Request */ + int idx; /* buffer index */ + int used; /* nr bytes in use */ + int num_blocks; /* number of GFXBlocks */ + int *length; /* List of lengths for GFXBlocks (FUTURE) */ + unsigned int last_render; /* Last Render Request */ } drm_i810_mc_t; - -#endif /* _I810_DRM_H_ */ +#endif /* _I810_DRM_H_ */ diff --git a/linux-core/i810_drv.c b/linux-core/i810_drv.c index b42df4c1..1081d9c8 100644 --- a/linux-core/i810_drv.c +++ b/linux-core/i810_drv.c @@ -38,7 +38,7 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { /* i810 has 4 more counters */ dev->counters += 4; @@ -46,29 +46,27 @@ static int postinit( struct drm_device *dev, unsigned long flags ) dev->types[7] = _DRM_STAT_PRIMARY; dev->types[8] = _DRM_STAT_SECONDARY; dev->types[9] = _DRM_STAT_DMA; - - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->minor, - pci_pretty_name(dev->pdev) - ); + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -77,25 +75,27 @@ static struct pci_device_id pciidlist[] = { }; static drm_ioctl_desc_t ioctls[] = { - [DRM_IOCTL_NR(DRM_I810_INIT)] = { i810_dma_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_I810_VERTEX)] = { i810_dma_vertex, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_CLEAR)] = { i810_clear_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_FLUSH)] = { i810_flush_ioctl, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_GETAGE)] = { i810_getage, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_GETBUF)] = { i810_getbuf, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_SWAP)] = { i810_swap_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_COPY)] = { i810_copybuf, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = { i810_docopy, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = { i810_ov0_info, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = { i810_fstatus, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = { i810_ov0_flip, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_MC)] = { i810_dma_mc, 1, 1 }, - [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = { i810_rstatus, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_FLIP)] = { i810_flip_bufs, 1, 0 } + [DRM_IOCTL_NR(DRM_I810_INIT)] = {i810_dma_init, 1, 1}, + [DRM_IOCTL_NR(DRM_I810_VERTEX)] = {i810_dma_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_CLEAR)] = {i810_clear_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_FLUSH)] = {i810_flush_ioctl, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_GETAGE)] = {i810_getage, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_GETBUF)] = {i810_getbuf, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_SWAP)] = {i810_swap_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_COPY)] = {i810_copybuf, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = {i810_docopy, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = {i810_ov0_info, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = {i810_fstatus, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = {i810_ov0_flip, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_MC)] = {i810_dma_mc, 1, 1}, + [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = {i810_rstatus, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_FLIP)] = {i810_flip_bufs, 1, 0} }; static struct drm_driver_fn driver_fn = { - .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, + .driver_features = + DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | + DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, .dev_priv_size = sizeof(drm_i810_buf_priv_t), .pretakedown = i810_driver_pretakedown, .release = i810_driver_release, @@ -108,13 +108,14 @@ static struct drm_driver_fn driver_fn = { .ioctls = ioctls, .num_ioctls = DRM_ARRAY_SIZE(ioctls), .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = i810_mmap_buffers, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = i810_mmap_buffers, + .fasync = drm_fasync, + } + , }; static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -123,10 +124,10 @@ static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) } static struct pci_driver driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - .probe = probe, - .remove = __devexit_p(drm_cleanup_pci), + .name = DRIVER_NAME, + .id_table = pciidlist, + .probe = probe, + .remove = __devexit_p(drm_cleanup_pci), }; static int __init i810_init(void) @@ -142,6 +143,6 @@ static void __exit i810_exit(void) module_init(i810_init); module_exit(i810_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/linux-core/i810_drv.h b/linux-core/i810_drv.h index d867429d..e09ffe92 100644 --- a/linux-core/i810_drv.h +++ b/linux-core/i810_drv.h @@ -56,14 +56,14 @@ #define DRIVER_PATCHLEVEL 0 typedef struct drm_i810_buf_priv { - u32 *in_use; - int my_use_idx; + u32 *in_use; + int my_use_idx; int currently_mapped; void *virtual; void *kernel_virtual; } drm_i810_buf_priv_t; -typedef struct _drm_i810_ring_buffer{ +typedef struct _drm_i810_ring_buffer { int tail_mask; unsigned long Start; unsigned long End; @@ -79,16 +79,15 @@ typedef struct drm_i810_private { drm_map_t *mmio_map; drm_i810_sarea_t *sarea_priv; - drm_i810_ring_buffer_t ring; + drm_i810_ring_buffer_t ring; - void *hw_status_page; - unsigned long counter; + void *hw_status_page; + unsigned long counter; dma_addr_t dma_status_page; drm_buf_t *mmap_buffer; - u32 front_di1, back_di1, zi1; int back_offset; @@ -97,7 +96,7 @@ typedef struct drm_i810_private { int overlay_physical; int w, h; int pitch; - int back_pitch; + int back_pitch; int depth_pitch; int do_boxes; @@ -107,24 +106,24 @@ typedef struct drm_i810_private { int page_flipping; wait_queue_head_t irq_queue; - atomic_t irq_received; - atomic_t irq_emitted; - - int front_offset; + atomic_t irq_received; + atomic_t irq_emitted; + + int front_offset; } drm_i810_private_t; /* i810_dma.c */ -extern int i810_dma_schedule(drm_device_t *dev, int locked); -extern int i810_getbuf(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int i810_dma_init(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int i810_dma_cleanup(drm_device_t *dev); -extern int i810_flush_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); +extern int i810_dma_schedule(drm_device_t * dev, int locked); +extern int i810_getbuf(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_dma_init(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_dma_cleanup(drm_device_t * dev); +extern int i810_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); extern void i810_reclaim_buffers(struct file *filp); -extern int i810_getage(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); +extern int i810_getage(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); extern int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma); /* Obsolete: @@ -139,32 +138,31 @@ extern int i810_docopy(struct inode *inode, struct file *filp, extern int i810_rstatus(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int i810_ov0_info(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); + unsigned int cmd, unsigned long arg); extern int i810_fstatus(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int i810_ov0_flip(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); + unsigned int cmd, unsigned long arg); extern int i810_dma_mc(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); - + unsigned int cmd, unsigned long arg); -extern void i810_dma_quiescent(drm_device_t *dev); +extern void i810_dma_quiescent(drm_device_t * dev); extern int i810_dma_vertex(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); + unsigned int cmd, unsigned long arg); extern int i810_swap_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); + unsigned int cmd, unsigned long arg); extern int i810_clear_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); + unsigned int cmd, unsigned long arg); extern int i810_flip_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); + unsigned int cmd, unsigned long arg); -extern int i810_driver_dma_quiescent(drm_device_t *dev); -extern void i810_driver_release(drm_device_t *dev, struct file *filp); -extern void i810_driver_pretakedown(drm_device_t *dev); +extern int i810_driver_dma_quiescent(drm_device_t * dev); +extern void i810_driver_release(drm_device_t * dev, struct file *filp); +extern void i810_driver_pretakedown(drm_device_t * dev); #define I810_BASE(reg) ((unsigned long) \ dev_priv->mmio_map->handle) @@ -214,7 +212,6 @@ extern void i810_driver_pretakedown(drm_device_t *dev); #define INST_OP_FLUSH 0x02000000 #define INST_FLUSH_MAP_CACHE 0x00000001 - #define BB1_START_ADDR_MASK (~0x7) #define BB1_PROTECTED (1<<0) #define BB1_UNPROTECTED (0<<0) @@ -273,8 +270,8 @@ extern void i810_driver_pretakedown(drm_device_t *dev); #define BR00_OP_SRC_COPY_BLT 0x10C00000 #define BR13_SOLID_PATTERN 0x80000000 -#define WAIT_FOR_PLANE_A_SCANLINES (1<<1) -#define WAIT_FOR_PLANE_A_FLIP (1<<2) +#define WAIT_FOR_PLANE_A_SCANLINES (1<<1) +#define WAIT_FOR_PLANE_A_FLIP (1<<2) #define WAIT_FOR_VBLANK (1<<3) #endif diff --git a/linux-core/i830_dma.c b/linux-core/i830_dma.c index 835f675e..f7f136e4 100644 --- a/linux-core/i830_dma.c +++ b/linux-core/i830_dma.c @@ -11,11 +11,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -31,14 +31,15 @@ * */ +#include /* For task queue support */ +#include /* For FASTCALL on unlock_page() */ +#include +#include + #include "drmP.h" #include "drm.h" #include "i830_drm.h" #include "i830_drv.h" -#include /* For task queue support */ -#include /* For FASTCALL on unlock_page() */ -#include -#include #ifdef DO_MUNMAP_4_ARGS #define DO_MUNMAP(m, a, l) do_munmap(m, a, l, 1) @@ -53,108 +54,109 @@ #define I830_BUF_UNMAPPED 0 #define I830_BUF_MAPPED 1 -static inline void i830_print_status_page(drm_device_t *dev) +static inline void i830_print_status_page(drm_device_t * dev) { - drm_device_dma_t *dma = dev->dma; - drm_i830_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_i830_private_t *dev_priv = dev->dev_private; u32 *temp = dev_priv->hw_status_page; - int i; + int i; - DRM_DEBUG( "hw_status: Interrupt Status : %x\n", temp[0]); - DRM_DEBUG( "hw_status: LpRing Head ptr : %x\n", temp[1]); - DRM_DEBUG( "hw_status: IRing Head ptr : %x\n", temp[2]); - DRM_DEBUG( "hw_status: Reserved : %x\n", temp[3]); - DRM_DEBUG( "hw_status: Driver Counter : %d\n", temp[5]); - for(i = 9; i < dma->buf_count + 9; i++) { - DRM_DEBUG( "buffer status idx : %d used: %d\n", i - 9, temp[i]); + DRM_DEBUG("hw_status: Interrupt Status : %x\n", temp[0]); + DRM_DEBUG("hw_status: LpRing Head ptr : %x\n", temp[1]); + DRM_DEBUG("hw_status: IRing Head ptr : %x\n", temp[2]); + DRM_DEBUG("hw_status: Reserved : %x\n", temp[3]); + DRM_DEBUG("hw_status: Driver Counter : %d\n", temp[5]); + for (i = 9; i < dma->buf_count + 9; i++) { + DRM_DEBUG("buffer status idx : %d used: %d\n", i - 9, temp[i]); } } -static drm_buf_t *i830_freelist_get(drm_device_t *dev) +static drm_buf_t *i830_freelist_get(drm_device_t * dev) { - drm_device_dma_t *dma = dev->dma; - int i; - int used; - + drm_device_dma_t *dma = dev->dma; + int i; + int used; + /* Linear search might not be the best solution */ - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i830_buf_priv_t *buf_priv = buf->dev_private; + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; /* In use is already a pointer */ - used = cmpxchg(buf_priv->in_use, I830_BUF_FREE, + used = cmpxchg(buf_priv->in_use, I830_BUF_FREE, I830_BUF_CLIENT); - if(used == I830_BUF_FREE) { + if (used == I830_BUF_FREE) { return buf; } } - return NULL; + return NULL; } /* This should only be called if the buffer is not sent to the hardware * yet, the hardware updates in use for us once its on the ring buffer. */ -static int i830_freelist_put(drm_device_t *dev, drm_buf_t *buf) +static int i830_freelist_put(drm_device_t * dev, drm_buf_t * buf) { - drm_i830_buf_priv_t *buf_priv = buf->dev_private; - int used; - - /* In use is already a pointer */ - used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE); - if(used != I830_BUF_CLIENT) { - DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); - return -EINVAL; - } - - return 0; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + int used; + + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE); + if (used != I830_BUF_CLIENT) { + DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); + return -EINVAL; + } + + return 0; } int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev; - drm_i830_private_t *dev_priv; - drm_buf_t *buf; + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_i830_private_t *dev_priv; + drm_buf_t *buf; drm_i830_buf_priv_t *buf_priv; lock_kernel(); - dev = priv->dev; + dev = priv->dev; dev_priv = dev->dev_private; - buf = dev_priv->mmap_buffer; + buf = dev_priv->mmap_buffer; buf_priv = buf->dev_private; - + vma->vm_flags |= (VM_IO | VM_DONTCOPY); vma->vm_file = filp; - - buf_priv->currently_mapped = I830_BUF_MAPPED; + + buf_priv->currently_mapped = I830_BUF_MAPPED; unlock_kernel(); if (remap_page_range(DRM_RPR_ARG(vma) vma->vm_start, VM_OFFSET(vma), - vma->vm_end - vma->vm_start, - vma->vm_page_prot)) return -EAGAIN; + vma->vm_end - vma->vm_start, vma->vm_page_prot)) + return -EAGAIN; return 0; } -static int i830_map_buffer(drm_buf_t *buf, struct file *filp) +static int i830_map_buffer(drm_buf_t * buf, struct file *filp) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_i830_buf_priv_t *buf_priv = buf->dev_private; - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; unsigned long virtual; int retcode = 0; - if(buf_priv->currently_mapped == I830_BUF_MAPPED) return -EINVAL; + if (buf_priv->currently_mapped == I830_BUF_MAPPED) + return -EINVAL; - down_write( ¤t->mm->mmap_sem ); + down_write(¤t->mm->mmap_sem); dev_priv->mmap_buffer = buf; - virtual = do_mmap(filp, 0, buf->total, PROT_READ|PROT_WRITE, - MAP_SHARED, buf->bus_address); + virtual = do_mmap(filp, 0, buf->total, PROT_READ | PROT_WRITE, + MAP_SHARED, buf->bus_address); dev_priv->mmap_buffer = NULL; - if (IS_ERR((void *)virtual)) { /* ugh */ + if (IS_ERR((void *)virtual)) { /* ugh */ /* Real error */ DRM_ERROR("mmap error\n"); retcode = virtual; @@ -162,17 +164,17 @@ static int i830_map_buffer(drm_buf_t *buf, struct file *filp) } else { buf_priv->virtual = (void __user *)virtual; } - up_write( ¤t->mm->mmap_sem ); + up_write(¤t->mm->mmap_sem); return retcode; } -static int i830_unmap_buffer(drm_buf_t *buf) +static int i830_unmap_buffer(drm_buf_t * buf) { drm_i830_buf_priv_t *buf_priv = buf->dev_private; int retcode = 0; - if(buf_priv->currently_mapped != I830_BUF_MAPPED) + if (buf_priv->currently_mapped != I830_BUF_MAPPED) return -EINVAL; down_write(¤t->mm->mmap_sem); @@ -181,43 +183,43 @@ static int i830_unmap_buffer(drm_buf_t *buf) (size_t) buf->total); up_write(¤t->mm->mmap_sem); - buf_priv->currently_mapped = I830_BUF_UNMAPPED; - buf_priv->virtual = NULL; + buf_priv->currently_mapped = I830_BUF_UNMAPPED; + buf_priv->virtual = NULL; return retcode; } -static int i830_dma_get_buffer(drm_device_t *dev, drm_i830_dma_t *d, +static int i830_dma_get_buffer(drm_device_t * dev, drm_i830_dma_t * d, struct file *filp) { - drm_buf_t *buf; + drm_buf_t *buf; drm_i830_buf_priv_t *buf_priv; int retcode = 0; buf = i830_freelist_get(dev); if (!buf) { retcode = -ENOMEM; - DRM_DEBUG("retcode=%d\n", retcode); + DRM_DEBUG("retcode=%d\n", retcode); return retcode; } - + retcode = i830_map_buffer(buf, filp); - if(retcode) { + if (retcode) { i830_freelist_put(dev, buf); - DRM_ERROR("mapbuf failed, retcode %d\n", retcode); + DRM_ERROR("mapbuf failed, retcode %d\n", retcode); return retcode; } buf->filp = filp; - buf_priv = buf->dev_private; + buf_priv = buf->dev_private; d->granted = 1; - d->request_idx = buf->idx; - d->request_size = buf->total; - d->virtual = buf_priv->virtual; + d->request_idx = buf->idx; + d->request_size = buf->total; + d->virtual = buf_priv->virtual; return retcode; } -int i830_dma_cleanup(drm_device_t *dev) +int i830_dma_cleanup(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; @@ -225,147 +227,151 @@ int i830_dma_cleanup(drm_device_t *dev) * may not have been called from userspace and after dev_private * is freed, it's too late. */ - if (dev->irq_enabled) drm_irq_uninstall(dev); + if (dev->irq_enabled) + drm_irq_uninstall(dev); if (dev->dev_private) { int i; - drm_i830_private_t *dev_priv = - (drm_i830_private_t *) dev->dev_private; - - if (dev_priv->ring.virtual_start) { - drm_ioremapfree((void *) dev_priv->ring.virtual_start, - dev_priv->ring.Size, dev); + drm_i830_private_t *dev_priv = + (drm_i830_private_t *) dev->dev_private; + + if (dev_priv->ring.virtual_start) { + drm_ioremapfree((void *)dev_priv->ring.virtual_start, + dev_priv->ring.Size, dev); } - if (dev_priv->hw_status_page) { + if (dev_priv->hw_status_page) { pci_free_consistent(dev->pdev, PAGE_SIZE, dev_priv->hw_status_page, dev_priv->dma_status_page); - /* Need to rewrite hardware status page */ - I830_WRITE(0x02080, 0x1ffff000); + /* Need to rewrite hardware status page */ + I830_WRITE(0x02080, 0x1ffff000); } - drm_free(dev->dev_private, sizeof(drm_i830_private_t), + drm_free(dev->dev_private, sizeof(drm_i830_private_t), DRM_MEM_DRIVER); - dev->dev_private = NULL; + dev->dev_private = NULL; for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; + drm_buf_t *buf = dma->buflist[i]; drm_i830_buf_priv_t *buf_priv = buf->dev_private; - if ( buf_priv->kernel_virtual && buf->total ) - drm_ioremapfree(buf_priv->kernel_virtual, buf->total, dev); + if (buf_priv->kernel_virtual && buf->total) + drm_ioremapfree(buf_priv->kernel_virtual, + buf->total, dev); } } - return 0; + return 0; } -int i830_wait_ring(drm_device_t *dev, int n, const char *caller) +int i830_wait_ring(drm_device_t * dev, int n, const char *caller) { - drm_i830_private_t *dev_priv = dev->dev_private; - drm_i830_ring_buffer_t *ring = &(dev_priv->ring); - int iters = 0; - unsigned long end; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_ring_buffer_t *ring = &(dev_priv->ring); + int iters = 0; + unsigned long end; unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - end = jiffies + (HZ*3); - while (ring->space < n) { - ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - ring->space = ring->head - (ring->tail+8); - if (ring->space < 0) ring->space += ring->Size; - + end = jiffies + (HZ * 3); + while (ring->space < n) { + ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->space = ring->head - (ring->tail + 8); + if (ring->space < 0) + ring->space += ring->Size; + if (ring->head != last_head) { - end = jiffies + (HZ*3); + end = jiffies + (HZ * 3); last_head = ring->head; } - - iters++; - if(time_before(end, jiffies)) { - DRM_ERROR("space: %d wanted %d\n", ring->space, n); - DRM_ERROR("lockup\n"); - goto out_wait_ring; + + iters++; + if (time_before(end, jiffies)) { + DRM_ERROR("space: %d wanted %d\n", ring->space, n); + DRM_ERROR("lockup\n"); + goto out_wait_ring; } udelay(1); dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT; } -out_wait_ring: - return iters; + out_wait_ring: + return iters; } -static void i830_kernel_lost_context(drm_device_t *dev) +static void i830_kernel_lost_context(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; - drm_i830_ring_buffer_t *ring = &(dev_priv->ring); - - ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR; - ring->space = ring->head - (ring->tail+8); - if (ring->space < 0) ring->space += ring->Size; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_ring_buffer_t *ring = &(dev_priv->ring); + + ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR; + ring->space = ring->head - (ring->tail + 8); + if (ring->space < 0) + ring->space += ring->Size; if (ring->head == ring->tail) dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY; } -static int i830_freelist_init(drm_device_t *dev, drm_i830_private_t *dev_priv) +static int i830_freelist_init(drm_device_t * dev, drm_i830_private_t * dev_priv) { - drm_device_dma_t *dma = dev->dma; - int my_idx = 36; - u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx); - int i; + drm_device_dma_t *dma = dev->dma; + int my_idx = 36; + u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx); + int i; - if(dma->buf_count > 1019) { - /* Not enough space in the status page for the freelist */ - return -EINVAL; + if (dma->buf_count > 1019) { + /* Not enough space in the status page for the freelist */ + return -EINVAL; } - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i830_buf_priv_t *buf_priv = buf->dev_private; + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; - buf_priv->in_use = hw_status++; - buf_priv->my_use_idx = my_idx; - my_idx += 4; + buf_priv->in_use = hw_status++; + buf_priv->my_use_idx = my_idx; + my_idx += 4; - *buf_priv->in_use = I830_BUF_FREE; + *buf_priv->in_use = I830_BUF_FREE; - buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, - buf->total, dev); + buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, + buf->total, dev); } return 0; } -static int i830_dma_initialize(drm_device_t *dev, - drm_i830_private_t *dev_priv, - drm_i830_init_t *init) +static int i830_dma_initialize(drm_device_t * dev, + drm_i830_private_t * dev_priv, + drm_i830_init_t * init) { struct list_head *list; - memset(dev_priv, 0, sizeof(drm_i830_private_t)); + memset(dev_priv, 0, sizeof(drm_i830_private_t)); list_for_each(list, &dev->maplist->head) { drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); - if( r_list->map && + if (r_list->map && r_list->map->type == _DRM_SHM && - r_list->map->flags & _DRM_CONTAINS_LOCK ) { + r_list->map->flags & _DRM_CONTAINS_LOCK) { dev_priv->sarea_map = r_list->map; - break; - } - } + break; + } + } - if(!dev_priv->sarea_map) { + if (!dev_priv->sarea_map) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("can not find sarea!\n"); return -EINVAL; } dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); - if(!dev_priv->mmio_map) { + if (!dev_priv->mmio_map) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("can not find mmio map!\n"); return -EINVAL; } dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if(!dev->agp_buffer_map) { + if (!dev->agp_buffer_map) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("can not find dma buffer map!\n"); @@ -373,27 +379,26 @@ static int i830_dma_initialize(drm_device_t *dev, } dev_priv->sarea_priv = (drm_i830_sarea_t *) - ((u8 *)dev_priv->sarea_map->handle + - init->sarea_priv_offset); + ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset); - dev_priv->ring.Start = init->ring_start; - dev_priv->ring.End = init->ring_end; - dev_priv->ring.Size = init->ring_size; + dev_priv->ring.Start = init->ring_start; + dev_priv->ring.End = init->ring_end; + dev_priv->ring.Size = init->ring_size; - dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + - init->ring_start, - init->ring_size, dev); + dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + + init->ring_start, + init->ring_size, dev); - if (dev_priv->ring.virtual_start == NULL) { - dev->dev_private = (void *) dev_priv; - i830_dma_cleanup(dev); - DRM_ERROR("can not ioremap virtual address for" + if (dev_priv->ring.virtual_start == NULL) { + dev->dev_private = (void *)dev_priv; + i830_dma_cleanup(dev); + DRM_ERROR("can not ioremap virtual address for" " ring buffer\n"); - return -ENOMEM; + return -ENOMEM; } - dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; - + dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; + dev_priv->w = init->w; dev_priv->h = init->h; dev_priv->pitch = init->pitch; @@ -405,10 +410,10 @@ static int i830_dma_initialize(drm_device_t *dev, dev_priv->back_di1 = init->back_offset | init->pitch_bits; dev_priv->zi1 = init->depth_offset | init->pitch_bits; - DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1); + DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1); DRM_DEBUG("back_offset %x\n", dev_priv->back_offset); - DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1); - DRM_DEBUG("pitch_bits %x\n", init->pitch_bits); + DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1); + DRM_DEBUG("pitch_bits %x\n", init->pitch_bits); dev_priv->cpp = init->cpp; /* We are using separate values as placeholders for mechanisms for @@ -420,63 +425,64 @@ static int i830_dma_initialize(drm_device_t *dev, dev_priv->do_boxes = 0; dev_priv->use_mi_batchbuffer_start = 0; - /* Program Hardware Status Page */ - dev_priv->hw_status_page = - pci_alloc_consistent(dev->pdev, PAGE_SIZE, - &dev_priv->dma_status_page); - if (!dev_priv->hw_status_page) { + /* Program Hardware Status Page */ + dev_priv->hw_status_page = + pci_alloc_consistent(dev->pdev, PAGE_SIZE, + &dev_priv->dma_status_page); + if (!dev_priv->hw_status_page) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("Can not allocate hardware status page\n"); return -ENOMEM; } - memset(dev_priv->hw_status_page, 0, PAGE_SIZE); + memset(dev_priv->hw_status_page, 0, PAGE_SIZE); DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); - - I830_WRITE(0x02080, dev_priv->dma_status_page); + + I830_WRITE(0x02080, dev_priv->dma_status_page); DRM_DEBUG("Enabled hardware status page\n"); - - /* Now we need to init our freelist */ - if(i830_freelist_init(dev, dev_priv) != 0) { + + /* Now we need to init our freelist */ + if (i830_freelist_init(dev, dev_priv) != 0) { dev->dev_private = (void *)dev_priv; - i830_dma_cleanup(dev); - DRM_ERROR("Not enough space in the status page for" + i830_dma_cleanup(dev); + DRM_ERROR("Not enough space in the status page for" " the freelist\n"); - return -ENOMEM; + return -ENOMEM; } dev->dev_private = (void *)dev_priv; - return 0; + return 0; } int i830_dma_init(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_i830_private_t *dev_priv; - drm_i830_init_t init; - int retcode = 0; - - if (copy_from_user(&init, (void * __user) arg, sizeof(init))) + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i830_private_t *dev_priv; + drm_i830_init_t init; + int retcode = 0; + + if (copy_from_user(&init, (void *__user)arg, sizeof(init))) return -EFAULT; - - switch(init.func) { - case I830_INIT_DMA: - dev_priv = drm_alloc(sizeof(drm_i830_private_t), - DRM_MEM_DRIVER); - if(dev_priv == NULL) return -ENOMEM; - retcode = i830_dma_initialize(dev, dev_priv, &init); - break; - case I830_CLEANUP_DMA: - retcode = i830_dma_cleanup(dev); - break; - default: - retcode = -EINVAL; - break; - } - - return retcode; + + switch (init.func) { + case I830_INIT_DMA: + dev_priv = drm_alloc(sizeof(drm_i830_private_t), + DRM_MEM_DRIVER); + if (dev_priv == NULL) + return -ENOMEM; + retcode = i830_dma_initialize(dev, dev_priv, &init); + break; + case I830_CLEANUP_DMA: + retcode = i830_dma_cleanup(dev); + break; + default: + retcode = -EINVAL; + break; + } + + return retcode; } #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) @@ -486,92 +492,89 @@ int i830_dma_init(struct inode *inode, struct file *filp, /* Most efficient way to verify state for the i830 is as it is * emitted. Non-conformant state is silently dropped. */ -static void i830EmitContextVerified( drm_device_t *dev, - unsigned int *code ) +static void i830EmitContextVerified(drm_device_t * dev, unsigned int *code) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; - BEGIN_LP_RING( I830_CTX_SETUP_SIZE + 4 ); + BEGIN_LP_RING(I830_CTX_SETUP_SIZE + 4); - for ( i = 0 ; i < I830_CTXREG_BLENDCOLR0 ; i++ ) { + for (i = 0; i < I830_CTXREG_BLENDCOLR0; i++) { tmp = code[i]; - if ((tmp & (7<<29)) == CMD_3D && - (tmp & (0x1f<<24)) < (0x1d<<24)) { - OUT_RING( tmp ); + if ((tmp & (7 << 29)) == CMD_3D && + (tmp & (0x1f << 24)) < (0x1d << 24)) { + OUT_RING(tmp); j++; } else { DRM_ERROR("Skipping %d\n", i); } } - OUT_RING( STATE3D_CONST_BLEND_COLOR_CMD ); - OUT_RING( code[I830_CTXREG_BLENDCOLR] ); + OUT_RING(STATE3D_CONST_BLEND_COLOR_CMD); + OUT_RING(code[I830_CTXREG_BLENDCOLR]); j += 2; - for ( i = I830_CTXREG_VF ; i < I830_CTXREG_MCSB0 ; i++ ) { + for (i = I830_CTXREG_VF; i < I830_CTXREG_MCSB0; i++) { tmp = code[i]; - if ((tmp & (7<<29)) == CMD_3D && - (tmp & (0x1f<<24)) < (0x1d<<24)) { - OUT_RING( tmp ); + if ((tmp & (7 << 29)) == CMD_3D && + (tmp & (0x1f << 24)) < (0x1d << 24)) { + OUT_RING(tmp); j++; } else { DRM_ERROR("Skipping %d\n", i); } } - OUT_RING( STATE3D_MAP_COORD_SETBIND_CMD ); - OUT_RING( code[I830_CTXREG_MCSB1] ); + OUT_RING(STATE3D_MAP_COORD_SETBIND_CMD); + OUT_RING(code[I830_CTXREG_MCSB1]); j += 2; - if (j & 1) - OUT_RING( 0 ); + if (j & 1) + OUT_RING(0); ADVANCE_LP_RING(); } -static void i830EmitTexVerified( drm_device_t *dev, unsigned int *code ) +static void i830EmitTexVerified(drm_device_t * dev, unsigned int *code) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; if (code[I830_TEXREG_MI0] == GFX_OP_MAP_INFO || - (code[I830_TEXREG_MI0] & ~(0xf*LOAD_TEXTURE_MAP0)) == - (STATE3D_LOAD_STATE_IMMEDIATE_2|4)) { - - BEGIN_LP_RING( I830_TEX_SETUP_SIZE ); - - OUT_RING( code[I830_TEXREG_MI0] ); /* TM0LI */ - OUT_RING( code[I830_TEXREG_MI1] ); /* TM0S0 */ - OUT_RING( code[I830_TEXREG_MI2] ); /* TM0S1 */ - OUT_RING( code[I830_TEXREG_MI3] ); /* TM0S2 */ - OUT_RING( code[I830_TEXREG_MI4] ); /* TM0S3 */ - OUT_RING( code[I830_TEXREG_MI5] ); /* TM0S4 */ - - for ( i = 6 ; i < I830_TEX_SETUP_SIZE ; i++ ) { + (code[I830_TEXREG_MI0] & ~(0xf * LOAD_TEXTURE_MAP0)) == + (STATE3D_LOAD_STATE_IMMEDIATE_2 | 4)) { + + BEGIN_LP_RING(I830_TEX_SETUP_SIZE); + + OUT_RING(code[I830_TEXREG_MI0]); /* TM0LI */ + OUT_RING(code[I830_TEXREG_MI1]); /* TM0S0 */ + OUT_RING(code[I830_TEXREG_MI2]); /* TM0S1 */ + OUT_RING(code[I830_TEXREG_MI3]); /* TM0S2 */ + OUT_RING(code[I830_TEXREG_MI4]); /* TM0S3 */ + OUT_RING(code[I830_TEXREG_MI5]); /* TM0S4 */ + + for (i = 6; i < I830_TEX_SETUP_SIZE; i++) { tmp = code[i]; - OUT_RING( tmp ); + OUT_RING(tmp); j++; - } + } - if (j & 1) - OUT_RING( 0 ); + if (j & 1) + OUT_RING(0); ADVANCE_LP_RING(); - } - else + } else printk("rejected packet %x\n", code[0]); } -static void i830EmitTexBlendVerified( drm_device_t *dev, - unsigned int *code, - unsigned int num) +static void i830EmitTexBlendVerified(drm_device_t * dev, + unsigned int *code, unsigned int num) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; @@ -579,59 +582,54 @@ static void i830EmitTexBlendVerified( drm_device_t *dev, if (!num) return; - BEGIN_LP_RING( num + 1 ); + BEGIN_LP_RING(num + 1); - for ( i = 0 ; i < num ; i++ ) { + for (i = 0; i < num; i++) { tmp = code[i]; - OUT_RING( tmp ); + OUT_RING(tmp); j++; } - if (j & 1) - OUT_RING( 0 ); + if (j & 1) + OUT_RING(0); ADVANCE_LP_RING(); } -static void i830EmitTexPalette( drm_device_t *dev, - unsigned int *palette, - int number, - int is_shared ) +static void i830EmitTexPalette(drm_device_t * dev, + unsigned int *palette, int number, int is_shared) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; int i; RING_LOCALS; return; - BEGIN_LP_RING( 258 ); + BEGIN_LP_RING(258); - if(is_shared == 1) { + if (is_shared == 1) { OUT_RING(CMD_OP_MAP_PALETTE_LOAD | - MAP_PALETTE_NUM(0) | - MAP_PALETTE_BOTH); + MAP_PALETTE_NUM(0) | MAP_PALETTE_BOTH); } else { OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number)); } - for(i = 0; i < 256; i++) { + for (i = 0; i < 256; i++) { OUT_RING(palette[i]); } OUT_RING(0); - /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop! + /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop! */ } /* Need to do some additional checking when setting the dest buffer. */ -static void i830EmitDestVerified( drm_device_t *dev, - unsigned int *code ) -{ - drm_i830_private_t *dev_priv = dev->dev_private; +static void i830EmitDestVerified(drm_device_t * dev, unsigned int *code) +{ + drm_i830_private_t *dev_priv = dev->dev_private; unsigned int tmp; RING_LOCALS; - BEGIN_LP_RING( I830_DEST_SETUP_SIZE + 10 ); - + BEGIN_LP_RING(I830_DEST_SETUP_SIZE + 10); tmp = code[I830_DESTREG_CBUFADDR]; if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { @@ -640,18 +638,18 @@ static void i830EmitDestVerified( drm_device_t *dev, OUT_RING(0); } - OUT_RING( CMD_OP_DESTBUFFER_INFO ); - OUT_RING( BUF_3D_ID_COLOR_BACK | - BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) | - BUF_3D_USE_FENCE); - OUT_RING( tmp ); - OUT_RING( 0 ); - - OUT_RING( CMD_OP_DESTBUFFER_INFO ); - OUT_RING( BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE | - BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp)); - OUT_RING( dev_priv->zi1 ); - OUT_RING( 0 ); + OUT_RING(CMD_OP_DESTBUFFER_INFO); + OUT_RING(BUF_3D_ID_COLOR_BACK | + BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) | + BUF_3D_USE_FENCE); + OUT_RING(tmp); + OUT_RING(0); + + OUT_RING(CMD_OP_DESTBUFFER_INFO); + OUT_RING(BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE | + BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp)); + OUT_RING(dev_priv->zi1); + OUT_RING(0); } else { DRM_ERROR("bad di1 %x (allow %x or %x)\n", tmp, dev_priv->front_di1, dev_priv->back_di1); @@ -660,83 +658,80 @@ static void i830EmitDestVerified( drm_device_t *dev, /* invarient: */ + OUT_RING(GFX_OP_DESTBUFFER_VARS); + OUT_RING(code[I830_DESTREG_DV1]); - OUT_RING( GFX_OP_DESTBUFFER_VARS ); - OUT_RING( code[I830_DESTREG_DV1] ); - - OUT_RING( GFX_OP_DRAWRECT_INFO ); - OUT_RING( code[I830_DESTREG_DR1] ); - OUT_RING( code[I830_DESTREG_DR2] ); - OUT_RING( code[I830_DESTREG_DR3] ); - OUT_RING( code[I830_DESTREG_DR4] ); + OUT_RING(GFX_OP_DRAWRECT_INFO); + OUT_RING(code[I830_DESTREG_DR1]); + OUT_RING(code[I830_DESTREG_DR2]); + OUT_RING(code[I830_DESTREG_DR3]); + OUT_RING(code[I830_DESTREG_DR4]); /* Need to verify this */ tmp = code[I830_DESTREG_SENABLE]; - if((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) { - OUT_RING( tmp ); + if ((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) { + OUT_RING(tmp); } else { DRM_ERROR("bad scissor enable\n"); - OUT_RING( 0 ); + OUT_RING(0); } - OUT_RING( GFX_OP_SCISSOR_RECT ); - OUT_RING( code[I830_DESTREG_SR1] ); - OUT_RING( code[I830_DESTREG_SR2] ); - OUT_RING( 0 ); + OUT_RING(GFX_OP_SCISSOR_RECT); + OUT_RING(code[I830_DESTREG_SR1]); + OUT_RING(code[I830_DESTREG_SR2]); + OUT_RING(0); ADVANCE_LP_RING(); } -static void i830EmitStippleVerified( drm_device_t *dev, - unsigned int *code ) +static void i830EmitStippleVerified(drm_device_t * dev, unsigned int *code) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; RING_LOCALS; - BEGIN_LP_RING( 2 ); - OUT_RING( GFX_OP_STIPPLE ); - OUT_RING( code[1] ); - ADVANCE_LP_RING(); + BEGIN_LP_RING(2); + OUT_RING(GFX_OP_STIPPLE); + OUT_RING(code[1]); + ADVANCE_LP_RING(); } - -static void i830EmitState( drm_device_t *dev ) +static void i830EmitState(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; - drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; DRM_DEBUG("%s %x\n", __FUNCTION__, dirty); if (dirty & I830_UPLOAD_BUFFERS) { - i830EmitDestVerified( dev, sarea_priv->BufferState ); + i830EmitDestVerified(dev, sarea_priv->BufferState); sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS; } if (dirty & I830_UPLOAD_CTX) { - i830EmitContextVerified( dev, sarea_priv->ContextState ); + i830EmitContextVerified(dev, sarea_priv->ContextState); sarea_priv->dirty &= ~I830_UPLOAD_CTX; } if (dirty & I830_UPLOAD_TEX0) { - i830EmitTexVerified( dev, sarea_priv->TexState[0] ); + i830EmitTexVerified(dev, sarea_priv->TexState[0]); sarea_priv->dirty &= ~I830_UPLOAD_TEX0; } if (dirty & I830_UPLOAD_TEX1) { - i830EmitTexVerified( dev, sarea_priv->TexState[1] ); + i830EmitTexVerified(dev, sarea_priv->TexState[1]); sarea_priv->dirty &= ~I830_UPLOAD_TEX1; } if (dirty & I830_UPLOAD_TEXBLEND0) { - i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[0], - sarea_priv->TexBlendStateWordsUsed[0]); + i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[0], + sarea_priv->TexBlendStateWordsUsed[0]); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0; } if (dirty & I830_UPLOAD_TEXBLEND1) { - i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[1], - sarea_priv->TexBlendStateWordsUsed[1]); + i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[1], + sarea_priv->TexBlendStateWordsUsed[1]); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1; } @@ -769,36 +764,32 @@ static void i830EmitState( drm_device_t *dev ) /* 1.3: */ if (dirty & I830_UPLOAD_STIPPLE) { - i830EmitStippleVerified( dev, - sarea_priv->StippleState); + i830EmitStippleVerified(dev, sarea_priv->StippleState); sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE; } if (dirty & I830_UPLOAD_TEX2) { - i830EmitTexVerified( dev, sarea_priv->TexState2 ); + i830EmitTexVerified(dev, sarea_priv->TexState2); sarea_priv->dirty &= ~I830_UPLOAD_TEX2; } if (dirty & I830_UPLOAD_TEX3) { - i830EmitTexVerified( dev, sarea_priv->TexState3 ); + i830EmitTexVerified(dev, sarea_priv->TexState3); sarea_priv->dirty &= ~I830_UPLOAD_TEX3; } - if (dirty & I830_UPLOAD_TEXBLEND2) { - i830EmitTexBlendVerified( - dev, - sarea_priv->TexBlendState2, - sarea_priv->TexBlendStateWordsUsed2); + i830EmitTexBlendVerified(dev, + sarea_priv->TexBlendState2, + sarea_priv->TexBlendStateWordsUsed2); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2; } if (dirty & I830_UPLOAD_TEXBLEND3) { - i830EmitTexBlendVerified( - dev, - sarea_priv->TexBlendState3, - sarea_priv->TexBlendStateWordsUsed3); + i830EmitTexBlendVerified(dev, + sarea_priv->TexBlendState3, + sarea_priv->TexBlendStateWordsUsed3); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3; } } @@ -807,97 +798,96 @@ static void i830EmitState( drm_device_t *dev ) * Performance monitoring functions */ -static void i830_fill_box( drm_device_t *dev, - int x, int y, int w, int h, - int r, int g, int b ) +static void i830_fill_box(drm_device_t * dev, + int x, int y, int w, int h, int r, int g, int b) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; u32 color; unsigned int BR13, CMD; RING_LOCALS; - BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1<<24); + BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1 << 24); CMD = XY_COLOR_BLT_CMD; x += dev_priv->sarea_priv->boxes[0].x1; y += dev_priv->sarea_priv->boxes[0].y1; if (dev_priv->cpp == 4) { - BR13 |= (1<<25); + BR13 |= (1 << 25); CMD |= (XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB); - color = (((0xff) << 24) | (r << 16) | (g << 8) | b); + color = (((0xff) << 24) | (r << 16) | (g << 8) | b); } else { color = (((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | - ((b & 0xf8) >> 3)); + ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); } - BEGIN_LP_RING( 6 ); - OUT_RING( CMD ); - OUT_RING( BR13 ); - OUT_RING( (y << 16) | x ); - OUT_RING( ((y+h) << 16) | (x+w) ); + BEGIN_LP_RING(6); + OUT_RING(CMD); + OUT_RING(BR13); + OUT_RING((y << 16) | x); + OUT_RING(((y + h) << 16) | (x + w)); - if ( dev_priv->current_page == 1 ) { - OUT_RING( dev_priv->front_offset ); - } else { - OUT_RING( dev_priv->back_offset ); - } + if (dev_priv->current_page == 1) { + OUT_RING(dev_priv->front_offset); + } else { + OUT_RING(dev_priv->back_offset); + } - OUT_RING( color ); + OUT_RING(color); ADVANCE_LP_RING(); } -static void i830_cp_performance_boxes( drm_device_t *dev ) +static void i830_cp_performance_boxes(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; /* Purple box for page flipping */ - if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP ) - i830_fill_box( dev, 4, 4, 8, 8, 255, 0, 255 ); + if (dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP) + i830_fill_box(dev, 4, 4, 8, 8, 255, 0, 255); /* Red box if we have to wait for idle at any point */ - if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT ) - i830_fill_box( dev, 16, 4, 8, 8, 255, 0, 0 ); + if (dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT) + i830_fill_box(dev, 16, 4, 8, 8, 255, 0, 0); /* Blue box: lost context? */ - if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT ) - i830_fill_box( dev, 28, 4, 8, 8, 0, 0, 255 ); + if (dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT) + i830_fill_box(dev, 28, 4, 8, 8, 0, 0, 255); /* Yellow box for texture swaps */ - if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD ) - i830_fill_box( dev, 40, 4, 8, 8, 255, 255, 0 ); + if (dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD) + i830_fill_box(dev, 40, 4, 8, 8, 255, 255, 0); /* Green box if hardware never idles (as far as we can tell) */ - if ( !(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY) ) - i830_fill_box( dev, 64, 4, 8, 8, 0, 255, 0 ); + if (!(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY)) + i830_fill_box(dev, 64, 4, 8, 8, 0, 255, 0); - - /* Draw bars indicating number of buffers allocated + /* Draw bars indicating number of buffers allocated * (not a great measure, easily confused) */ if (dev_priv->dma_used) { int bar = dev_priv->dma_used / 10240; - if (bar > 100) bar = 100; - if (bar < 1) bar = 1; - i830_fill_box( dev, 4, 16, bar, 4, 196, 128, 128 ); + if (bar > 100) + bar = 100; + if (bar < 1) + bar = 1; + i830_fill_box(dev, 4, 16, bar, 4, 196, 128, 128); dev_priv->dma_used = 0; } dev_priv->sarea_priv->perf_boxes = 0; } -static void i830_dma_dispatch_clear( drm_device_t *dev, int flags, +static void i830_dma_dispatch_clear(drm_device_t * dev, int flags, unsigned int clear_color, unsigned int clear_zval, unsigned int clear_depthmask) { - drm_i830_private_t *dev_priv = dev->dev_private; - drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; int pitch = dev_priv->pitch; @@ -906,90 +896,90 @@ static void i830_dma_dispatch_clear( drm_device_t *dev, int flags, unsigned int BR13, CMD, D_CMD; RING_LOCALS; - - if ( dev_priv->current_page == 1 ) { + if (dev_priv->current_page == 1) { unsigned int tmp = flags; flags &= ~(I830_FRONT | I830_BACK); - if ( tmp & I830_FRONT ) flags |= I830_BACK; - if ( tmp & I830_BACK ) flags |= I830_FRONT; + if (tmp & I830_FRONT) + flags |= I830_BACK; + if (tmp & I830_BACK) + flags |= I830_FRONT; } - i830_kernel_lost_context(dev); + i830_kernel_lost_context(dev); - switch(cpp) { - case 2: - BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24); + switch (cpp) { + case 2: + BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24); D_CMD = CMD = XY_COLOR_BLT_CMD; break; case 4: - BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24) | (1<<25); - CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | + BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24) | (1 << 25); + CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB); D_CMD = XY_COLOR_BLT_CMD; - if(clear_depthmask & 0x00ffffff) + if (clear_depthmask & 0x00ffffff) D_CMD |= XY_COLOR_BLT_WRITE_RGB; - if(clear_depthmask & 0xff000000) + if (clear_depthmask & 0xff000000) D_CMD |= XY_COLOR_BLT_WRITE_ALPHA; break; default: - BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24); + BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24); D_CMD = CMD = XY_COLOR_BLT_CMD; break; } - if (nbox > I830_NR_SAREA_CLIPRECTS) - nbox = I830_NR_SAREA_CLIPRECTS; + if (nbox > I830_NR_SAREA_CLIPRECTS) + nbox = I830_NR_SAREA_CLIPRECTS; - for (i = 0 ; i < nbox ; i++, pbox++) { + for (i = 0; i < nbox; i++, pbox++) { if (pbox->x1 > pbox->x2 || pbox->y1 > pbox->y2 || - pbox->x2 > dev_priv->w || - pbox->y2 > dev_priv->h) + pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) continue; - if ( flags & I830_FRONT ) { - DRM_DEBUG("clear front\n"); - BEGIN_LP_RING( 6 ); - OUT_RING( CMD ); - OUT_RING( BR13 ); - OUT_RING( (pbox->y1 << 16) | pbox->x1 ); - OUT_RING( (pbox->y2 << 16) | pbox->x2 ); - OUT_RING( dev_priv->front_offset ); - OUT_RING( clear_color ); + if (flags & I830_FRONT) { + DRM_DEBUG("clear front\n"); + BEGIN_LP_RING(6); + OUT_RING(CMD); + OUT_RING(BR13); + OUT_RING((pbox->y1 << 16) | pbox->x1); + OUT_RING((pbox->y2 << 16) | pbox->x2); + OUT_RING(dev_priv->front_offset); + OUT_RING(clear_color); ADVANCE_LP_RING(); } - if ( flags & I830_BACK ) { + if (flags & I830_BACK) { DRM_DEBUG("clear back\n"); - BEGIN_LP_RING( 6 ); - OUT_RING( CMD ); - OUT_RING( BR13 ); - OUT_RING( (pbox->y1 << 16) | pbox->x1 ); - OUT_RING( (pbox->y2 << 16) | pbox->x2 ); - OUT_RING( dev_priv->back_offset ); - OUT_RING( clear_color ); + BEGIN_LP_RING(6); + OUT_RING(CMD); + OUT_RING(BR13); + OUT_RING((pbox->y1 << 16) | pbox->x1); + OUT_RING((pbox->y2 << 16) | pbox->x2); + OUT_RING(dev_priv->back_offset); + OUT_RING(clear_color); ADVANCE_LP_RING(); } - if ( flags & I830_DEPTH ) { + if (flags & I830_DEPTH) { DRM_DEBUG("clear depth\n"); - BEGIN_LP_RING( 6 ); - OUT_RING( D_CMD ); - OUT_RING( BR13 ); - OUT_RING( (pbox->y1 << 16) | pbox->x1 ); - OUT_RING( (pbox->y2 << 16) | pbox->x2 ); - OUT_RING( dev_priv->depth_offset ); - OUT_RING( clear_zval ); + BEGIN_LP_RING(6); + OUT_RING(D_CMD); + OUT_RING(BR13); + OUT_RING((pbox->y1 << 16) | pbox->x1); + OUT_RING((pbox->y2 << 16) | pbox->x2); + OUT_RING(dev_priv->depth_offset); + OUT_RING(clear_zval); ADVANCE_LP_RING(); } } } -static void i830_dma_dispatch_swap( drm_device_t *dev ) +static void i830_dma_dispatch_swap(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; - drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; int pitch = dev_priv->pitch; @@ -1000,202 +990,192 @@ static void i830_dma_dispatch_swap( drm_device_t *dev ) DRM_DEBUG("swapbuffers\n"); - i830_kernel_lost_context(dev); + i830_kernel_lost_context(dev); if (dev_priv->do_boxes) - i830_cp_performance_boxes( dev ); + i830_cp_performance_boxes(dev); - switch(cpp) { - case 2: - BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24); + switch (cpp) { + case 2: + BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24); CMD = XY_SRC_COPY_BLT_CMD; break; case 4: - BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24) | (1<<25); + BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25); CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | XY_SRC_COPY_BLT_WRITE_RGB); break; default: - BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24); + BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24); CMD = XY_SRC_COPY_BLT_CMD; break; } + if (nbox > I830_NR_SAREA_CLIPRECTS) + nbox = I830_NR_SAREA_CLIPRECTS; - if (nbox > I830_NR_SAREA_CLIPRECTS) - nbox = I830_NR_SAREA_CLIPRECTS; - - for (i = 0 ; i < nbox; i++, pbox++) - { + for (i = 0; i < nbox; i++, pbox++) { if (pbox->x1 > pbox->x2 || pbox->y1 > pbox->y2 || - pbox->x2 > dev_priv->w || - pbox->y2 > dev_priv->h) + pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) continue; - + DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n", - pbox->x1, pbox->y1, - pbox->x2, pbox->y2); + pbox->x1, pbox->y1, pbox->x2, pbox->y2); - BEGIN_LP_RING( 8 ); - OUT_RING( CMD ); - OUT_RING( BR13 ); - OUT_RING( (pbox->y1 << 16) | pbox->x1 ); - OUT_RING( (pbox->y2 << 16) | pbox->x2 ); + BEGIN_LP_RING(8); + OUT_RING(CMD); + OUT_RING(BR13); + OUT_RING((pbox->y1 << 16) | pbox->x1); + OUT_RING((pbox->y2 << 16) | pbox->x2); - if (dev_priv->current_page == 0) - OUT_RING( dev_priv->front_offset ); + if (dev_priv->current_page == 0) + OUT_RING(dev_priv->front_offset); else - OUT_RING( dev_priv->back_offset ); + OUT_RING(dev_priv->back_offset); - OUT_RING( (pbox->y1 << 16) | pbox->x1 ); - OUT_RING( BR13 & 0xffff ); + OUT_RING((pbox->y1 << 16) | pbox->x1); + OUT_RING(BR13 & 0xffff); - if (dev_priv->current_page == 0) - OUT_RING( dev_priv->back_offset ); + if (dev_priv->current_page == 0) + OUT_RING(dev_priv->back_offset); else - OUT_RING( dev_priv->front_offset ); + OUT_RING(dev_priv->front_offset); ADVANCE_LP_RING(); } } -static void i830_dma_dispatch_flip( drm_device_t *dev ) +static void i830_dma_dispatch_flip(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; RING_LOCALS; - DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", - __FUNCTION__, - dev_priv->current_page, - dev_priv->sarea_priv->pf_current_page); + DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, + dev_priv->sarea_priv->pf_current_page); - i830_kernel_lost_context(dev); + i830_kernel_lost_context(dev); if (dev_priv->do_boxes) { dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP; - i830_cp_performance_boxes( dev ); + i830_cp_performance_boxes(dev); } - - BEGIN_LP_RING( 2 ); - OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); - OUT_RING( 0 ); + BEGIN_LP_RING(2); + OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); + OUT_RING(0); ADVANCE_LP_RING(); - BEGIN_LP_RING( 6 ); - OUT_RING( CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP ); - OUT_RING( 0 ); - if ( dev_priv->current_page == 0 ) { - OUT_RING( dev_priv->back_offset ); + BEGIN_LP_RING(6); + OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); + OUT_RING(0); + if (dev_priv->current_page == 0) { + OUT_RING(dev_priv->back_offset); dev_priv->current_page = 1; } else { - OUT_RING( dev_priv->front_offset ); + OUT_RING(dev_priv->front_offset); dev_priv->current_page = 0; } OUT_RING(0); ADVANCE_LP_RING(); - - BEGIN_LP_RING( 2 ); - OUT_RING( MI_WAIT_FOR_EVENT | - MI_WAIT_FOR_PLANE_A_FLIP ); - OUT_RING( 0 ); + BEGIN_LP_RING(2); + OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); + OUT_RING(0); ADVANCE_LP_RING(); - dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; } -static void i830_dma_dispatch_vertex(drm_device_t *dev, - drm_buf_t *buf, - int discard, - int used) +static void i830_dma_dispatch_vertex(drm_device_t * dev, + drm_buf_t * buf, int discard, int used) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_buf_priv_t *buf_priv = buf->dev_private; - drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_clip_rect_t *box = sarea_priv->boxes; - int nbox = sarea_priv->nbox; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_clip_rect_t *box = sarea_priv->boxes; + int nbox = sarea_priv->nbox; unsigned long address = (unsigned long)buf->bus_address; - unsigned long start = address - dev->agp->base; + unsigned long start = address - dev->agp->base; int i = 0, u; - RING_LOCALS; + RING_LOCALS; - i830_kernel_lost_context(dev); + i830_kernel_lost_context(dev); - if (nbox > I830_NR_SAREA_CLIPRECTS) + if (nbox > I830_NR_SAREA_CLIPRECTS) nbox = I830_NR_SAREA_CLIPRECTS; if (discard) { - u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, + u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_HARDWARE); - if(u != I830_BUF_CLIENT) { + if (u != I830_BUF_CLIENT) { DRM_DEBUG("xxxx 2\n"); } } - if (used > 4*1023) + if (used > 4 * 1023) used = 0; if (sarea_priv->dirty) - i830EmitState( dev ); + i830EmitState(dev); - DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n", + DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n", address, used, nbox); - dev_priv->counter++; - DRM_DEBUG( "dispatch counter : %ld\n", dev_priv->counter); - DRM_DEBUG( "i830_dma_dispatch\n"); - DRM_DEBUG( "start : %lx\n", start); - DRM_DEBUG( "used : %d\n", used); - DRM_DEBUG( "start + used - 4 : %ld\n", start + used - 4); + dev_priv->counter++; + DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter); + DRM_DEBUG("i830_dma_dispatch\n"); + DRM_DEBUG("start : %lx\n", start); + DRM_DEBUG("used : %d\n", used); + DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4); if (buf_priv->currently_mapped == I830_BUF_MAPPED) { u32 *vp = buf_priv->kernel_virtual; vp[0] = (GFX_OP_PRIMITIVE | - sarea_priv->vertex_prim | - ((used/4)-2)); + sarea_priv->vertex_prim | ((used / 4) - 2)); if (dev_priv->use_mi_batchbuffer_start) { - vp[used/4] = MI_BATCH_BUFFER_END; - used += 4; + vp[used / 4] = MI_BATCH_BUFFER_END; + used += 4; } - + if (used & 4) { - vp[used/4] = 0; + vp[used / 4] = 0; used += 4; } i830_unmap_buffer(buf); } - + if (used) { do { if (i < nbox) { BEGIN_LP_RING(6); - OUT_RING( GFX_OP_DRAWRECT_INFO ); - OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR1] ); - OUT_RING( box[i].x1 | (box[i].y1<<16) ); - OUT_RING( box[i].x2 | (box[i].y2<<16) ); - OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR4] ); - OUT_RING( 0 ); + OUT_RING(GFX_OP_DRAWRECT_INFO); + OUT_RING(sarea_priv-> + BufferState[I830_DESTREG_DR1]); + OUT_RING(box[i].x1 | (box[i].y1 << 16)); + OUT_RING(box[i].x2 | (box[i].y2 << 16)); + OUT_RING(sarea_priv-> + BufferState[I830_DESTREG_DR4]); + OUT_RING(0); ADVANCE_LP_RING(); } if (dev_priv->use_mi_batchbuffer_start) { BEGIN_LP_RING(2); - OUT_RING( MI_BATCH_BUFFER_START | (2<<6) ); - OUT_RING( start | MI_BATCH_NON_SECURE ); + OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); + OUT_RING(start | MI_BATCH_NON_SECURE); ADVANCE_LP_RING(); - } - else { + } else { BEGIN_LP_RING(4); - OUT_RING( MI_BATCH_BUFFER ); - OUT_RING( start | MI_BATCH_NON_SECURE ); - OUT_RING( start + used - 4 ); - OUT_RING( 0 ); + OUT_RING(MI_BATCH_BUFFER); + OUT_RING(start | MI_BATCH_NON_SECURE); + OUT_RING(start + used - 4); + OUT_RING(0); ADVANCE_LP_RING(); } @@ -1205,61 +1185,60 @@ static void i830_dma_dispatch_vertex(drm_device_t *dev, if (discard) { dev_priv->counter++; - (void) cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, - I830_BUF_HARDWARE); + (void)cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, + I830_BUF_HARDWARE); BEGIN_LP_RING(8); - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( 20 ); - OUT_RING( dev_priv->counter ); - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( buf_priv->my_use_idx ); - OUT_RING( I830_BUF_FREE ); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(20); + OUT_RING(dev_priv->counter); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(buf_priv->my_use_idx); + OUT_RING(I830_BUF_FREE); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); ADVANCE_LP_RING(); } } - -void i830_dma_quiescent(drm_device_t *dev) +void i830_dma_quiescent(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; - RING_LOCALS; + drm_i830_private_t *dev_priv = dev->dev_private; + RING_LOCALS; - i830_kernel_lost_context(dev); + i830_kernel_lost_context(dev); - BEGIN_LP_RING(4); - OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); - OUT_RING( 0 ); - ADVANCE_LP_RING(); + BEGIN_LP_RING(4); + OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); + OUT_RING(0); + ADVANCE_LP_RING(); - i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ ); + i830_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__); } -static int i830_flush_queue(drm_device_t *dev) +static int i830_flush_queue(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; - int i, ret = 0; - RING_LOCALS; - - i830_kernel_lost_context(dev); - - BEGIN_LP_RING(2); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); - ADVANCE_LP_RING(); - - i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ ); - - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i830_buf_priv_t *buf_priv = buf->dev_private; - - int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE, + int i, ret = 0; + RING_LOCALS; + + i830_kernel_lost_context(dev); + + BEGIN_LP_RING(2); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); + ADVANCE_LP_RING(); + + i830_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__); + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + + int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE, I830_BUF_FREE); if (used == I830_BUF_HARDWARE) @@ -1268,70 +1247,74 @@ static int i830_flush_queue(drm_device_t *dev) DRM_DEBUG("still on client\n"); } - return ret; + return ret; } /* Must be called with the lock held */ -void i830_reclaim_buffers( struct file *filp ) +void i830_reclaim_buffers(struct file *filp) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_device_dma_t *dma = dev->dma; - int i; + int i; - if (!dma) return; - if (!dev->dev_private) return; - if (!dma->buflist) return; + if (!dma) + return; + if (!dev->dev_private) + return; + if (!dma->buflist) + return; - i830_flush_queue(dev); + i830_flush_queue(dev); for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i830_buf_priv_t *buf_priv = buf->dev_private; - + drm_buf_t *buf = dma->buflist[i]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + if (buf->filp == filp && buf_priv) { - int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, + int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE); if (used == I830_BUF_CLIENT) DRM_DEBUG("reclaimed from client\n"); - if(buf_priv->currently_mapped == I830_BUF_MAPPED) - buf_priv->currently_mapped = I830_BUF_UNMAPPED; + if (buf_priv->currently_mapped == I830_BUF_MAPPED) + buf_priv->currently_mapped = I830_BUF_UNMAPPED; } } } -int i830_flush_ioctl(struct inode *inode, struct file *filp, +int i830_flush_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; - if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_flush_ioctl called without lock held\n"); return -EINVAL; } - i830_flush_queue(dev); - return 0; + i830_flush_queue(dev); + return 0; } int i830_dma_vertex(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_device_dma_t *dma = dev->dma; - drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) - dev_priv->sarea_priv; + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) + dev_priv->sarea_priv; drm_i830_vertex_t vertex; - if (copy_from_user(&vertex, (drm_i830_vertex_t __user *)arg, sizeof(vertex))) + if (copy_from_user + (&vertex, (drm_i830_vertex_t __user *) arg, sizeof(vertex))) return -EFAULT; - if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_dma_vertex called without lock held\n"); return -EINVAL; } @@ -1339,29 +1322,31 @@ int i830_dma_vertex(struct inode *inode, struct file *filp, DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n", vertex.idx, vertex.used, vertex.discard); - if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL; + if (vertex.idx < 0 || vertex.idx > dma->buf_count) + return -EINVAL; + + i830_dma_dispatch_vertex(dev, + dma->buflist[vertex.idx], + vertex.discard, vertex.used); - i830_dma_dispatch_vertex( dev, - dma->buflist[ vertex.idx ], - vertex.discard, vertex.used ); + sarea_priv->last_enqueue = dev_priv->counter - 1; + sarea_priv->last_dispatch = (int)hw_status[5]; - sarea_priv->last_enqueue = dev_priv->counter-1; - sarea_priv->last_dispatch = (int) hw_status[5]; - return 0; } int i830_clear_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_i830_clear_t clear; - if (copy_from_user(&clear, (drm_i830_clear_t __user *)arg, sizeof(clear))) + if (copy_from_user + (&clear, (drm_i830_clear_t __user *) arg, sizeof(clear))) return -EFAULT; - - if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_clear_bufs called without lock held\n"); return -EINVAL; } @@ -1371,35 +1356,32 @@ int i830_clear_bufs(struct inode *inode, struct file *filp, return -EINVAL; } - i830_dma_dispatch_clear( dev, clear.flags, - clear.clear_color, - clear.clear_depth, - clear.clear_depthmask); - return 0; + i830_dma_dispatch_clear(dev, clear.flags, + clear.clear_color, + clear.clear_depth, clear.clear_depthmask); + return 0; } int i830_swap_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; - + DRM_DEBUG("i830_swap_bufs\n"); - if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_swap_buf called without lock held\n"); return -EINVAL; } - i830_dma_dispatch_swap( dev ); - return 0; + i830_dma_dispatch_swap(dev); + return 0; } - - /* Not sure why this isn't set all the time: - */ -static void i830_do_init_pageflip( drm_device_t *dev ) + */ +static void i830_do_init_pageflip(drm_device_t * dev) { drm_i830_private_t *dev_priv = dev->dev_private; @@ -1409,13 +1391,13 @@ static void i830_do_init_pageflip( drm_device_t *dev ) dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; } -int i830_do_cleanup_pageflip( drm_device_t *dev ) +int i830_do_cleanup_pageflip(drm_device_t * dev) { drm_i830_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); if (dev_priv->current_page != 0) - i830_dma_dispatch_flip( dev ); + i830_dma_dispatch_flip(dev); dev_priv->page_flipping = 0; return 0; @@ -1430,53 +1412,53 @@ int i830_flip_bufs(struct inode *inode, struct file *filp, DRM_DEBUG("%s\n", __FUNCTION__); - if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_flip_buf called without lock held\n"); return -EINVAL; } - if (!dev_priv->page_flipping) - i830_do_init_pageflip( dev ); + if (!dev_priv->page_flipping) + i830_do_init_pageflip(dev); - i830_dma_dispatch_flip( dev ); - return 0; + i830_dma_dispatch_flip(dev); + return 0; } int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) - dev_priv->sarea_priv; - - sarea_priv->last_dispatch = (int) hw_status[5]; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) + dev_priv->sarea_priv; + + sarea_priv->last_dispatch = (int)hw_status[5]; return 0; } int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - int retcode = 0; - drm_i830_dma_t d; - drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) - dev_priv->sarea_priv; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode = 0; + drm_i830_dma_t d; + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) + dev_priv->sarea_priv; DRM_DEBUG("getbuf\n"); - if (copy_from_user(&d, (drm_i830_dma_t __user *)arg, sizeof(d))) + if (copy_from_user(&d, (drm_i830_dma_t __user *) arg, sizeof(d))) return -EFAULT; - - if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_dma called without lock held\n"); return -EINVAL; } - + d.granted = 0; retcode = i830_dma_get_buffer(dev, &d, filp); @@ -1484,17 +1466,15 @@ int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n", current->pid, retcode, d.granted); - if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d))) + if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d))) return -EFAULT; - sarea_priv->last_dispatch = (int) hw_status[5]; + sarea_priv->last_dispatch = (int)hw_status[5]; return retcode; } int i830_copybuf(struct inode *inode, - struct file *filp, - unsigned int cmd, - unsigned long arg) + struct file *filp, unsigned int cmd, unsigned long arg) { /* Never copy - 2.4.x doesn't need it */ return 0; @@ -1506,26 +1486,25 @@ int i830_docopy(struct inode *inode, struct file *filp, unsigned int cmd, return 0; } - - -int i830_getparam( struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg ) +int i830_getparam(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_getparam_t param; int value; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - if (copy_from_user(¶m, (drm_i830_getparam_t __user *)arg, sizeof(param) )) + if (copy_from_user + (¶m, (drm_i830_getparam_t __user *) arg, sizeof(param))) return -EFAULT; - switch( param.param ) { + switch (param.param) { case I830_PARAM_IRQ_ACTIVE: value = dev->irq_enabled; break; @@ -1533,32 +1512,32 @@ int i830_getparam( struct inode *inode, struct file *filp, unsigned int cmd, return -EINVAL; } - if ( copy_to_user( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (copy_to_user(param.value, &value, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return -EFAULT; } - + return 0; } - -int i830_setparam( struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg ) +int i830_setparam(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_setparam_t param; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - if (copy_from_user(¶m, (drm_i830_setparam_t __user *)arg, sizeof(param) )) + if (copy_from_user + (¶m, (drm_i830_setparam_t __user *) arg, sizeof(param))) return -EFAULT; - switch( param.param ) { + switch (param.param) { case I830_SETPARAM_USE_MI_BATCHBUFFER_START: dev_priv->use_mi_batchbuffer_start = param.value; break; @@ -1569,20 +1548,18 @@ int i830_setparam( struct inode *inode, struct file *filp, unsigned int cmd, return 0; } - -void i830_driver_pretakedown(drm_device_t *dev) +void i830_driver_pretakedown(drm_device_t * dev) { - i830_dma_cleanup( dev ); + i830_dma_cleanup(dev); } -void i830_driver_release(drm_device_t *dev, struct file *filp) +void i830_driver_release(drm_device_t * dev, struct file *filp) { i830_reclaim_buffers(filp); } -int i830_driver_dma_quiescent(drm_device_t *dev) +int i830_driver_dma_quiescent(drm_device_t * dev) { - i830_dma_quiescent( dev ); + i830_dma_quiescent(dev); return 0; } - diff --git a/linux-core/i830_drm.h b/linux-core/i830_drm.h index 03382c0b..7283f794 100644 --- a/linux-core/i830_drm.h +++ b/linux-core/i830_drm.h @@ -33,21 +33,21 @@ #define I830_UPLOAD_CTX 0x1 #define I830_UPLOAD_BUFFERS 0x2 #define I830_UPLOAD_CLIPRECTS 0x4 -#define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */ -#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */ -#define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */ -#define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */ -#define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */ -#define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */ -#define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */ -#define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */ +#define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */ +#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */ +#define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */ +#define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */ +#define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */ +#define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */ +#define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */ +#define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */ #define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2)) #define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2)) #define I830_UPLOAD_TEXIMAGE_MASK 0xff00 -#define I830_UPLOAD_TEX0 0x10000 -#define I830_UPLOAD_TEX1 0x20000 -#define I830_UPLOAD_TEX2 0x40000 -#define I830_UPLOAD_TEX3 0x80000 +#define I830_UPLOAD_TEX0 0x10000 +#define I830_UPLOAD_TEX1 0x20000 +#define I830_UPLOAD_TEX2 0x40000 +#define I830_UPLOAD_TEX3 0x80000 #define I830_UPLOAD_TEX_N(n) (0x10000 << (n)) #define I830_UPLOAD_TEX_MASK 0xf0000 #define I830_UPLOAD_TEXBLEND0 0x100000 @@ -65,7 +65,7 @@ * or in a piecewise fashion as required. */ -/* Destbuffer state +/* Destbuffer state * - backbuffer linear offset and pitch -- invarient in the current dri * - zbuffer linear offset and pitch -- also invarient * - drawing origin in back and depth buffers. @@ -103,7 +103,7 @@ #define I830_CTXREG_AA 9 #define I830_CTXREG_FOGCOLOR 10 #define I830_CTXREG_BLENDCOLR0 11 -#define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */ +#define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */ #define I830_CTXREG_VF 13 #define I830_CTXREG_VF2 14 #define I830_CTXREG_MCSB0 15 @@ -111,12 +111,11 @@ #define I830_CTX_SETUP_SIZE 17 /* 1.3: Stipple state - */ + */ #define I830_STPREG_ST0 0 #define I830_STPREG_ST1 1 #define I830_STP_SETUP_SIZE 2 - /* Texture state (per tex unit) */ @@ -132,23 +131,23 @@ #define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */ #define I830_TEX_SETUP_SIZE 10 -#define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */ +#define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */ #define I830_TEXREG_TM0S0 1 #define I830_TEXREG_TM0S1 2 #define I830_TEXREG_TM0S2 3 #define I830_TEXREG_TM0S3 4 #define I830_TEXREG_TM0S4 5 -#define I830_TEXREG_NOP0 6 /* noop */ -#define I830_TEXREG_NOP1 7 /* noop */ -#define I830_TEXREG_NOP2 8 /* noop */ -#define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */ +#define I830_TEXREG_NOP0 6 /* noop */ +#define I830_TEXREG_NOP1 7 /* noop */ +#define I830_TEXREG_NOP2 8 /* noop */ +#define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */ #define __I830_TEX_SETUP_SIZE 10 #define I830_FRONT 0x1 #define I830_BACK 0x2 #define I830_DEPTH 0x4 -#endif /* _I830_DEFINES_ */ +#endif /* _I830_DEFINES_ */ typedef struct _drm_i830_init { enum { @@ -177,19 +176,19 @@ typedef struct _drm_i830_init { * structure as well */ typedef struct _drm_i830_tex_region { - unsigned char next, prev; /* indices to form a circular LRU */ + unsigned char next, prev; /* indices to form a circular LRU */ unsigned char in_use; /* owned by a client, or free? */ int age; /* tracked by clients to update local LRU's */ } drm_i830_tex_region_t; typedef struct _drm_i830_sarea { unsigned int ContextState[I830_CTX_SETUP_SIZE]; - unsigned int BufferState[I830_DEST_SETUP_SIZE]; + unsigned int BufferState[I830_DEST_SETUP_SIZE]; unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE]; unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE]; unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT]; unsigned int Palette[2][256]; - unsigned int dirty; + unsigned int dirty; unsigned int nbox; drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS]; @@ -207,26 +206,26 @@ typedef struct _drm_i830_sarea { * texture space, and can make informed decisions as to which * areas to kick out. There is no need to choose whether to * kick out your own texture or someone else's - simply eject - * them all in LRU order. + * them all in LRU order. */ - drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS+1]; - /* Last elt is sentinal */ - int texAge; /* last time texture was uploaded */ - int last_enqueue; /* last time a buffer was enqueued */ + drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS + 1]; + /* Last elt is sentinal */ + int texAge; /* last time texture was uploaded */ + int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ - int last_quiescent; /* */ + int last_quiescent; /* */ int ctxOwner; /* last context to upload state */ int vertex_prim; - int pf_enabled; /* is pageflipping allowed? */ - int pf_active; - int pf_current_page; /* which buffer is being displayed? */ + int pf_enabled; /* is pageflipping allowed? */ + int pf_active; + int pf_current_page; /* which buffer is being displayed? */ + + int perf_boxes; /* performance boxes to be displayed */ - int perf_boxes; /* performance boxes to be displayed */ - - /* Here's the state for texunits 2,3: + /* Here's the state for texunits 2,3: */ unsigned int TexState2[I830_TEX_SETUP_SIZE]; unsigned int TexBlendState2[I830_TEXBLEND_SIZE]; @@ -241,26 +240,25 @@ typedef struct _drm_i830_sarea { /* Flags for perf_boxes */ -#define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */ -#define I830_BOX_FLIP 0x2 /* populated by kernel */ -#define I830_BOX_WAIT 0x4 /* populated by kernel & client */ -#define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */ -#define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */ - +#define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */ +#define I830_BOX_FLIP 0x2 /* populated by kernel */ +#define I830_BOX_WAIT 0x4 /* populated by kernel & client */ +#define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */ +#define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */ /* I830 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ -#define DRM_I830_INIT 0x00 -#define DRM_I830_VERTEX 0x01 -#define DRM_I830_CLEAR 0x02 -#define DRM_I830_FLUSH 0x03 -#define DRM_I830_GETAGE 0x04 -#define DRM_I830_GETBUF 0x05 -#define DRM_I830_SWAP 0x06 -#define DRM_I830_COPY 0x07 -#define DRM_I830_DOCOPY 0x08 -#define DRM_I830_FLIP 0x09 +#define DRM_I830_INIT 0x00 +#define DRM_I830_VERTEX 0x01 +#define DRM_I830_CLEAR 0x02 +#define DRM_I830_FLUSH 0x03 +#define DRM_I830_GETAGE 0x04 +#define DRM_I830_GETBUF 0x05 +#define DRM_I830_SWAP 0x06 +#define DRM_I830_COPY 0x07 +#define DRM_I830_DOCOPY 0x08 +#define DRM_I830_FLIP 0x09 #define DRM_I830_IRQ_EMIT 0x0a #define DRM_I830_IRQ_WAIT 0x0b #define DRM_I830_GETPARAM 0x0c @@ -289,23 +287,21 @@ typedef struct _drm_i830_clear { unsigned int clear_depthmask; } drm_i830_clear_t; - - /* These may be placeholders if we have more cliprects than * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to * false, indicating that the buffer will be dispatched again with a * new set of cliprects. */ typedef struct _drm_i830_vertex { - int idx; /* buffer index */ + int idx; /* buffer index */ int used; /* nr bytes in use */ int discard; /* client is finished with the buffer? */ } drm_i830_vertex_t; typedef struct _drm_i830_copy_t { - int idx; /* buffer index */ + int idx; /* buffer index */ int used; /* nr bytes in use */ - void __user *address; /* Address to copy from */ + void __user *address; /* Address to copy from */ } drm_i830_copy_t; typedef struct drm_i830_dma { @@ -315,7 +311,6 @@ typedef struct drm_i830_dma { int granted; } drm_i830_dma_t; - /* 1.3: Userspace can request & wait on irq's: */ typedef struct drm_i830_irq_emit { @@ -326,7 +321,6 @@ typedef struct drm_i830_irq_wait { int irq_seq; } drm_i830_irq_wait_t; - /* 1.3: New ioctl to query kernel params: */ #define I830_PARAM_IRQ_ACTIVE 1 @@ -336,7 +330,6 @@ typedef struct drm_i830_getparam { int __user *value; } drm_i830_getparam_t; - /* 1.3: New ioctl to set kernel params: */ #define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1 @@ -346,5 +339,4 @@ typedef struct drm_i830_setparam { int value; } drm_i830_setparam_t; - -#endif /* _I830_DRM_H_ */ +#endif /* _I830_DRM_H_ */ diff --git a/linux-core/i830_drv.c b/linux-core/i830_drv.c index 55d38c1b..9f0a5d3c 100644 --- a/linux-core/i830_drv.c +++ b/linux-core/i830_drv.c @@ -33,6 +33,7 @@ */ #include + #include "drmP.h" #include "drm.h" #include "i830_drm.h" @@ -40,36 +41,34 @@ #include "drm_pciids.h" -int postinit( struct drm_device *dev, unsigned long flags ) +int postinit(struct drm_device *dev, unsigned long flags) { dev->counters += 4; dev->types[6] = _DRM_STAT_IRQ; dev->types[7] = _DRM_STAT_PRIMARY; dev->types[8] = _DRM_STAT_SECONDARY; dev->types[9] = _DRM_STAT_DMA; - - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->minor, - pci_pretty_name(dev->pdev) - ); + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -78,24 +77,26 @@ static struct pci_device_id pciidlist[] = { }; static drm_ioctl_desc_t ioctls[] = { - [DRM_IOCTL_NR(DRM_I830_INIT)] = { i830_dma_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_I830_VERTEX)] = { i830_dma_vertex, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_CLEAR)] = { i830_clear_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_FLUSH)] = { i830_flush_ioctl, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_GETAGE)] = { i830_getage, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_GETBUF)] = { i830_getbuf, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_SWAP)] = { i830_swap_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_COPY)] = { i830_copybuf, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_DOCOPY)] = { i830_docopy, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_FLIP)] = { i830_flip_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT)] = { i830_irq_emit, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT)] = { i830_irq_wait, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_GETPARAM)] = { i830_getparam, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_SETPARAM)] = { i830_setparam, 1, 0 } + [DRM_IOCTL_NR(DRM_I830_INIT)] = {i830_dma_init, 1, 1}, + [DRM_IOCTL_NR(DRM_I830_VERTEX)] = {i830_dma_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_CLEAR)] = {i830_clear_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_FLUSH)] = {i830_flush_ioctl, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_GETAGE)] = {i830_getage, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_GETBUF)] = {i830_getbuf, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_SWAP)] = {i830_swap_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_COPY)] = {i830_copybuf, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_DOCOPY)] = {i830_docopy, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_FLIP)] = {i830_flip_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT)] = {i830_irq_emit, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT)] = {i830_irq_wait, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_GETPARAM)] = {i830_getparam, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_SETPARAM)] = {i830_setparam, 1, 0} }; static struct drm_driver_fn driver_fn = { - .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, + .driver_features = + DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | + DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, #if USE_IRQS .driver_features |= DRIVER_HAVE_IRQ | DRIVER_SHARED_IRQ, #endif @@ -117,13 +118,14 @@ static struct drm_driver_fn driver_fn = { .ioctls = ioctls, .num_ioctls = DRM_ARRAY_SIZE(ioctls), .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = i830_mmap_buffers, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = i830_mmap_buffers, + .fasync = drm_fasync, + } + , }; static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -132,10 +134,10 @@ static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) } static struct pci_driver driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - .probe = probe, - .remove = __devexit_p(drm_cleanup_pci), + .name = DRIVER_NAME, + .id_table = pciidlist, + .probe = probe, + .remove = __devexit_p(drm_cleanup_pci), }; static int __init i830_init(void) @@ -151,6 +153,6 @@ static void __exit i830_exit(void) module_init(i830_init); module_exit(i830_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/linux-core/i830_drv.h b/linux-core/i830_drv.h index c2832cf8..91f11a72 100644 --- a/linux-core/i830_drv.h +++ b/linux-core/i830_drv.h @@ -11,11 +11,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -63,14 +63,14 @@ #define USE_IRQS 0 typedef struct drm_i830_buf_priv { - u32 *in_use; - int my_use_idx; + u32 *in_use; + int my_use_idx; int currently_mapped; void __user *virtual; void *kernel_virtual; } drm_i830_buf_priv_t; -typedef struct _drm_i830_ring_buffer{ +typedef struct _drm_i830_ring_buffer { int tail_mask; unsigned long Start; unsigned long End; @@ -86,17 +86,17 @@ typedef struct drm_i830_private { drm_map_t *mmio_map; drm_i830_sarea_t *sarea_priv; - drm_i830_ring_buffer_t ring; + drm_i830_ring_buffer_t ring; - void * hw_status_page; - unsigned long counter; + void *hw_status_page; + unsigned long counter; dma_addr_t dma_status_page; drm_buf_t *mmap_buffer; - + u32 front_di1, back_di1, zi1; - + int back_offset; int depth_offset; int front_offset; @@ -113,66 +113,66 @@ typedef struct drm_i830_private { int page_flipping; wait_queue_head_t irq_queue; - atomic_t irq_received; - atomic_t irq_emitted; + atomic_t irq_received; + atomic_t irq_emitted; int use_mi_batchbuffer_start; } drm_i830_private_t; /* i830_dma.c */ -extern int i830_dma_schedule(drm_device_t *dev, int locked); -extern int i830_getbuf(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int i830_dma_init(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int i830_dma_cleanup(drm_device_t *dev); -extern int i830_flush_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); +extern int i830_dma_schedule(drm_device_t * dev, int locked); +extern int i830_getbuf(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i830_dma_init(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i830_dma_cleanup(drm_device_t * dev); +extern int i830_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); extern void i830_reclaim_buffers(struct file *filp); -extern int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg); +extern int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg); extern int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma); -extern int i830_copybuf(struct inode *inode, struct file *filp, +extern int i830_copybuf(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); -extern int i830_docopy(struct inode *inode, struct file *filp, +extern int i830_docopy(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); -extern void i830_dma_quiescent(drm_device_t *dev); +extern void i830_dma_quiescent(drm_device_t * dev); extern int i830_dma_vertex(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); + unsigned int cmd, unsigned long arg); extern int i830_swap_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); + unsigned int cmd, unsigned long arg); extern int i830_clear_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); + unsigned int cmd, unsigned long arg); extern int i830_flip_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); + unsigned int cmd, unsigned long arg); -extern int i830_getparam( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); +extern int i830_getparam(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); -extern int i830_setparam( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); +extern int i830_setparam(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); /* i830_irq.c */ -extern int i830_irq_emit( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int i830_irq_wait( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int i830_wait_irq(drm_device_t *dev, int irq_nr); -extern int i830_emit_irq(drm_device_t *dev); - -extern irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS ); -extern void i830_driver_irq_preinstall( drm_device_t *dev ); -extern void i830_driver_irq_postinstall( drm_device_t *dev ); -extern void i830_driver_irq_uninstall( drm_device_t *dev ); -extern void i830_driver_pretakedown(drm_device_t *dev); -extern void i830_driver_release(drm_device_t *dev, struct file *filp); -extern int i830_driver_dma_quiescent(drm_device_t *dev); +extern int i830_irq_emit(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i830_irq_wait(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i830_wait_irq(drm_device_t * dev, int irq_nr); +extern int i830_emit_irq(drm_device_t * dev); + +extern irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS); +extern void i830_driver_irq_preinstall(drm_device_t * dev); +extern void i830_driver_irq_postinstall(drm_device_t * dev); +extern void i830_driver_irq_uninstall(drm_device_t * dev); +extern void i830_driver_pretakedown(drm_device_t * dev); +extern void i830_driver_release(drm_device_t * dev, struct file *filp); +extern int i830_driver_dma_quiescent(drm_device_t * dev); #define I830_BASE(reg) ((unsigned long) \ dev_priv->mmio_map->handle) @@ -184,8 +184,6 @@ extern int i830_driver_dma_quiescent(drm_device_t *dev); #define I830_READ16(reg) I830_DEREF16(reg) #define I830_WRITE16(reg,val) do { I830_DEREF16(reg) = val; } while (0) - - #define I830_VERBOSE 0 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ @@ -203,7 +201,6 @@ extern int i830_driver_dma_quiescent(drm_device_t *dev); virt = dev_priv->ring.virtual_start; \ } while (0) - #define OUT_RING(n) do { \ if (I830_VERBOSE) printk(" OUT_RING %x\n", (int)(n)); \ *(volatile unsigned int *)(virt + outring) = n; \ @@ -219,8 +216,7 @@ extern int i830_driver_dma_quiescent(drm_device_t *dev); I830_WRITE(LP_RING + RING_TAIL, outring); \ } while(0) -extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); - +extern int i830_wait_ring(drm_device_t * dev, int n, const char *caller); #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) @@ -235,7 +231,6 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); #define INST_OP_FLUSH 0x02000000 #define INST_FLUSH_MAP_CACHE 0x00000001 - #define BB1_START_ADDR_MASK (~0x7) #define BB1_PROTECTED (1<<0) #define BB1_UNPROTECTED (0<<0) @@ -248,7 +243,6 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); #define I830_IRQ_RESERVED ((1<<13)|(3<<2)) - #define LP_RING 0x2030 #define HP_RING 0x2040 #define RING_TAIL 0x00 @@ -260,7 +254,7 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); #define RING_START 0x08 #define START_ADDR 0x0xFFFFF000 #define RING_LEN 0x0C -#define RING_NR_PAGES 0x001FF000 +#define RING_NR_PAGES 0x001FF000 #define RING_REPORT_MASK 0x00000006 #define RING_REPORT_64K 0x00000002 #define RING_REPORT_128K 0x00000004 @@ -326,10 +320,9 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); #define MI_BATCH_NON_SECURE (1) #define MI_WAIT_FOR_EVENT ((0x3<<23)) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) +#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) #endif - diff --git a/linux-core/i830_irq.c b/linux-core/i830_irq.c index 19f4fd51..7c709738 100644 --- a/linux-core/i830_irq.c +++ b/linux-core/i830_irq.c @@ -9,11 +9,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -26,36 +26,35 @@ * */ +#include /* For task queue support */ +#include + #include "drmP.h" #include "drm.h" #include "i830_drm.h" #include "i830_drv.h" -#include /* For task queue support */ -#include - -irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS ) +irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS) { - drm_device_t *dev = (drm_device_t *)arg; - drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; - u16 temp; + drm_device_t *dev = (drm_device_t *) arg; + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; + u16 temp; - temp = I830_READ16(I830REG_INT_IDENTITY_R); + temp = I830_READ16(I830REG_INT_IDENTITY_R); DRM_DEBUG("%x\n", temp); - if ( !( temp & 2 ) ) + if (!(temp & 2)) return IRQ_NONE; - I830_WRITE16(I830REG_INT_IDENTITY_R, temp); + I830_WRITE16(I830REG_INT_IDENTITY_R, temp); atomic_inc(&dev_priv->irq_received); - wake_up_interruptible(&dev_priv->irq_queue); + wake_up_interruptible(&dev_priv->irq_queue); return IRQ_HANDLED; } - -int i830_emit_irq(drm_device_t *dev) +int i830_emit_irq(drm_device_t * dev) { drm_i830_private_t *dev_priv = dev->dev_private; RING_LOCALS; @@ -64,27 +63,25 @@ int i830_emit_irq(drm_device_t *dev) atomic_inc(&dev_priv->irq_emitted); - BEGIN_LP_RING(2); - OUT_RING( 0 ); - OUT_RING( GFX_OP_USER_INTERRUPT ); - ADVANCE_LP_RING(); + BEGIN_LP_RING(2); + OUT_RING(0); + OUT_RING(GFX_OP_USER_INTERRUPT); + ADVANCE_LP_RING(); return atomic_read(&dev_priv->irq_emitted); } - -int i830_wait_irq(drm_device_t *dev, int irq_nr) +int i830_wait_irq(drm_device_t * dev, int irq_nr) { - drm_i830_private_t *dev_priv = - (drm_i830_private_t *)dev->dev_private; + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; DECLARE_WAITQUEUE(entry, current); - unsigned long end = jiffies + HZ*3; + unsigned long end = jiffies + HZ * 3; int ret = 0; DRM_DEBUG("%s\n", __FUNCTION__); - if (atomic_read(&dev_priv->irq_received) >= irq_nr) - return 0; + if (atomic_read(&dev_priv->irq_received) >= irq_nr) + return 0; dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT; @@ -92,21 +89,21 @@ int i830_wait_irq(drm_device_t *dev, int irq_nr) for (;;) { current->state = TASK_INTERRUPTIBLE; - if (atomic_read(&dev_priv->irq_received) >= irq_nr) - break; - if((signed)(end - jiffies) <= 0) { + if (atomic_read(&dev_priv->irq_received) >= irq_nr) + break; + if ((signed)(end - jiffies) <= 0) { DRM_ERROR("timeout iir %x imr %x ier %x hwstam %x\n", - I830_READ16( I830REG_INT_IDENTITY_R ), - I830_READ16( I830REG_INT_MASK_R ), - I830_READ16( I830REG_INT_ENABLE_R ), - I830_READ16( I830REG_HWSTAM )); + I830_READ16(I830REG_INT_IDENTITY_R), + I830_READ16(I830REG_INT_MASK_R), + I830_READ16(I830REG_INT_ENABLE_R), + I830_READ16(I830REG_HWSTAM)); - ret = -EBUSY; /* Lockup? Missed irq? */ + ret = -EBUSY; /* Lockup? Missed irq? */ break; } - schedule_timeout(HZ*3); - if (signal_pending(current)) { - ret = -EINTR; + schedule_timeout(HZ * 3); + if (signal_pending(current)) { + ret = -EINTR; break; } } @@ -116,92 +113,90 @@ int i830_wait_irq(drm_device_t *dev, int irq_nr) return ret; } - /* Needs the lock as it touches the ring. */ -int i830_irq_emit( struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg ) +int i830_irq_emit(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_irq_emit_t emit; int result; - if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { DRM_ERROR("i830_irq_emit called without lock held\n"); return -EINVAL; } - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - if (copy_from_user( &emit, (drm_i830_irq_emit_t __user *)arg, sizeof(emit) )) + if (copy_from_user + (&emit, (drm_i830_irq_emit_t __user *) arg, sizeof(emit))) return -EFAULT; - result = i830_emit_irq( dev ); + result = i830_emit_irq(dev); - if ( copy_to_user( emit.irq_seq, &result, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (copy_to_user(emit.irq_seq, &result, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return -EFAULT; } return 0; } - /* Doesn't need the hardware lock. */ -int i830_irq_wait( struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg ) +int i830_irq_wait(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_irq_wait_t irqwait; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - if (copy_from_user( &irqwait, (drm_i830_irq_wait_t __user *)arg, - sizeof(irqwait) )) + if (copy_from_user(&irqwait, (drm_i830_irq_wait_t __user *) arg, + sizeof(irqwait))) return -EFAULT; - return i830_wait_irq( dev, irqwait.irq_seq ); + return i830_wait_irq(dev, irqwait.irq_seq); } - /* drm_dma.h hooks */ -void i830_driver_irq_preinstall( drm_device_t *dev ) { - drm_i830_private_t *dev_priv = - (drm_i830_private_t *)dev->dev_private; +void i830_driver_irq_preinstall(drm_device_t * dev) +{ + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; - I830_WRITE16( I830REG_HWSTAM, 0xffff ); - I830_WRITE16( I830REG_INT_MASK_R, 0x0 ); - I830_WRITE16( I830REG_INT_ENABLE_R, 0x0 ); + I830_WRITE16(I830REG_HWSTAM, 0xffff); + I830_WRITE16(I830REG_INT_MASK_R, 0x0); + I830_WRITE16(I830REG_INT_ENABLE_R, 0x0); atomic_set(&dev_priv->irq_received, 0); atomic_set(&dev_priv->irq_emitted, 0); init_waitqueue_head(&dev_priv->irq_queue); } -void i830_driver_irq_postinstall( drm_device_t *dev ) { - drm_i830_private_t *dev_priv = - (drm_i830_private_t *)dev->dev_private; +void i830_driver_irq_postinstall(drm_device_t * dev) +{ + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; - I830_WRITE16( I830REG_INT_ENABLE_R, 0x2 ); + I830_WRITE16(I830REG_INT_ENABLE_R, 0x2); } -void i830_driver_irq_uninstall( drm_device_t *dev ) { - drm_i830_private_t *dev_priv = - (drm_i830_private_t *)dev->dev_private; +void i830_driver_irq_uninstall(drm_device_t * dev) +{ + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; if (!dev_priv) return; - I830_WRITE16( I830REG_INT_MASK_R, 0xffff ); - I830_WRITE16( I830REG_INT_ENABLE_R, 0x0 ); + I830_WRITE16(I830REG_INT_MASK_R, 0xffff); + I830_WRITE16(I830REG_INT_ENABLE_R, 0x0); } diff --git a/linux-core/i915_drv.c b/linux-core/i915_drv.c index 6daeb738..77b48045 100644 --- a/linux-core/i915_drv.c +++ b/linux-core/i915_drv.c @@ -15,36 +15,34 @@ #include "drm_pciids.h" -int postinit( struct drm_device *dev, unsigned long flags ) +int postinit(struct drm_device *dev, unsigned long flags) { dev->counters += 4; dev->types[6] = _DRM_STAT_IRQ; dev->types[7] = _DRM_STAT_PRIMARY; dev->types[8] = _DRM_STAT_SECONDARY; dev->types[9] = _DRM_STAT_DMA; - - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->minor, - pci_pretty_name(dev->pdev) - ); + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -53,23 +51,24 @@ static struct pci_device_id pciidlist[] = { }; static drm_ioctl_desc_t ioctls[] = { - [DRM_IOCTL_NR(DRM_I915_INIT)] = { i915_dma_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_I915_FLUSH)] = { i915_flush_ioctl, 1, 0 }, - [DRM_IOCTL_NR(DRM_I915_FLIP)] = { i915_flip_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = { i915_batchbuffer, 1, 0 }, - [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = { i915_irq_emit, 1, 0 }, - [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = { i915_irq_wait, 1, 0 }, - [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = { i915_getparam, 1, 0 }, - [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = { i915_setparam, 1, 1 }, - [DRM_IOCTL_NR(DRM_I915_ALLOC)] = { i915_mem_alloc, 1, 0 }, - [DRM_IOCTL_NR(DRM_I915_FREE)] = { i915_mem_free, 1, 0 }, - [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = { i915_mem_init_heap, 1, 1 }, - [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = { i915_cmdbuffer, 1, 0 } + [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, 1, 1}, + [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, 1, 1}, + [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, 1, 1}, + [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, 1, 0} }; static struct drm_driver_fn driver_fn = { - .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | - DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, + .driver_features = + DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | + DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, .pretakedown = i915_driver_pretakedown, .prerelease = i915_driver_prerelease, .irq_preinstall = i915_driver_irq_preinstall, @@ -84,13 +83,13 @@ static struct drm_driver_fn driver_fn = { .ioctls = ioctls, .num_ioctls = DRM_ARRAY_SIZE(ioctls), .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .fasync = drm_fasync, + }, }; static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -99,10 +98,10 @@ static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) } static struct pci_driver driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - .probe = probe, - .remove = __devexit_p(drm_cleanup_pci), + .name = DRIVER_NAME, + .id_table = pciidlist, + .probe = probe, + .remove = __devexit_p(drm_cleanup_pci), }; static int __init i915_init(void) @@ -118,6 +117,6 @@ static void __exit i915_exit(void) module_init(i915_init); module_exit(i915_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/linux-core/mach64_drv.c b/linux-core/mach64_drv.c index 3a65dc1c..ae34e70c 100644 --- a/linux-core/mach64_drv.c +++ b/linux-core/mach64_drv.c @@ -35,30 +35,28 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -72,19 +70,21 @@ static struct pci_device_id pciidlist[] = { * */ static drm_ioctl_desc_t ioctls[] = { - [DRM_IOCTL_NR(DRM_MACH64_INIT)] = { mach64_dma_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_MACH64_CLEAR)] = { mach64_dma_clear, 1, 0 }, - [DRM_IOCTL_NR(DRM_MACH64_SWAP)] = { mach64_dma_swap, 1, 0 }, - [DRM_IOCTL_NR(DRM_MACH64_IDLE)] = { mach64_dma_idle, 1, 0 }, - [DRM_IOCTL_NR(DRM_MACH64_RESET)] = { mach64_engine_reset, 1, 0 }, - [DRM_IOCTL_NR(DRM_MACH64_VERTEX)] = { mach64_dma_vertex, 1, 0 }, - [DRM_IOCTL_NR(DRM_MACH64_BLIT)] = { mach64_dma_blit, 1, 0 }, - [DRM_IOCTL_NR(DRM_MACH64_FLUSH)] = { mach64_dma_flush, 1, 0 }, - [DRM_IOCTL_NR(DRM_MACH64_GETPARAM)] = { mach64_get_param, 1, 0 }, + [DRM_IOCTL_NR(DRM_MACH64_INIT)] = {mach64_dma_init, 1, 1}, + [DRM_IOCTL_NR(DRM_MACH64_CLEAR)] = {mach64_dma_clear, 1, 0}, + [DRM_IOCTL_NR(DRM_MACH64_SWAP)] = {mach64_dma_swap, 1, 0}, + [DRM_IOCTL_NR(DRM_MACH64_IDLE)] = {mach64_dma_idle, 1, 0}, + [DRM_IOCTL_NR(DRM_MACH64_RESET)] = {mach64_engine_reset, 1, 0}, + [DRM_IOCTL_NR(DRM_MACH64_VERTEX)] = {mach64_dma_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_MACH64_BLIT)] = {mach64_dma_blit, 1, 0}, + [DRM_IOCTL_NR(DRM_MACH64_FLUSH)] = {mach64_dma_flush, 1, 0}, + [DRM_IOCTL_NR(DRM_MACH64_GETPARAM)] = {mach64_get_param, 1, 0}, }; static struct drm_driver_fn driver_fn = { - .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, + .driver_features = + DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_HAVE_DMA + | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, .pretakedown = mach64_driver_pretakedown, .vblank_wait = mach64_driver_vblank_wait, .irq_preinstall = mach64_driver_irq_preinstall, @@ -100,13 +100,13 @@ static struct drm_driver_fn driver_fn = { .num_ioctls = DRM_ARRAY_SIZE(ioctls), .dma_ioctl = mach64_dma_buffers, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .fasync = drm_fasync, + }, }; static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -115,10 +115,10 @@ static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) } static struct pci_driver driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - .probe = probe, - .remove = __devexit_p(drm_cleanup_pci), + .name = DRIVER_NAME, + .id_table = pciidlist, + .probe = probe, + .remove = __devexit_p(drm_cleanup_pci), }; static int __init mach64_init(void) @@ -134,6 +134,6 @@ static void __exit mach64_exit(void) module_init(mach64_init); module_exit(mach64_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/linux-core/mga_drv.c b/linux-core/mga_drv.c index 8787204c..08b6bcb4 100644 --- a/linux-core/mga_drv.c +++ b/linux-core/mga_drv.c @@ -37,35 +37,33 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { dev->counters += 3; dev->types[6] = _DRM_STAT_IRQ; dev->types[7] = _DRM_STAT_PRIMARY; dev->types[8] = _DRM_STAT_SECONDARY; - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -74,20 +72,23 @@ static struct pci_device_id pciidlist[] = { }; static drm_ioctl_desc_t ioctls[] = { - [DRM_IOCTL_NR(DRM_MGA_INIT)] = { mga_dma_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = { mga_dma_flush, 1, 0 }, - [DRM_IOCTL_NR(DRM_MGA_RESET)] = { mga_dma_reset, 1, 0 }, - [DRM_IOCTL_NR(DRM_MGA_SWAP)] = { mga_dma_swap, 1, 0 }, - [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = { mga_dma_clear, 1, 0 }, - [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = { mga_dma_vertex, 1, 0 }, - [DRM_IOCTL_NR(DRM_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, - [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = { mga_dma_iload, 1, 0 }, - [DRM_IOCTL_NR(DRM_MGA_BLIT)] = { mga_dma_blit, 1, 0 }, - [DRM_IOCTL_NR(DRM_MGA_GETPARAM)]= { mga_getparam, 1, 0 }, + [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1}, + [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0}, }; static struct drm_driver_fn driver_fn = { - .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, + .driver_features = + DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | + DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | + DRIVER_IRQ_VBL, .pretakedown = mga_driver_pretakedown, .dma_quiescent = mga_driver_dma_quiescent, .vblank_wait = mga_driver_vblank_wait, @@ -104,13 +105,13 @@ static struct drm_driver_fn driver_fn = { .num_ioctls = DRM_ARRAY_SIZE(ioctls), .dma_ioctl = mga_dma_buffers, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .fasync = drm_fasync, + }, }; static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -119,10 +120,10 @@ static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) } static struct pci_driver driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - .probe = probe, - .remove = __devexit_p(drm_cleanup_pci), + .name = DRIVER_NAME, + .id_table = pciidlist, + .probe = probe, + .remove = __devexit_p(drm_cleanup_pci), }; static int __init mga_init(void) @@ -138,6 +139,6 @@ static void __exit mga_exit(void) module_init(mga_init); module_exit(mga_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/linux-core/r128_drv.c b/linux-core/r128_drv.c index 9c95518f..cead11e4 100644 --- a/linux-core/r128_drv.c +++ b/linux-core/r128_drv.c @@ -38,30 +38,28 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -76,27 +74,30 @@ static struct pci_device_id pciidlist[] = { * 2.5 - Add FLIP ioctl, disable FULLSCREEN. */ static drm_ioctl_desc_t ioctls[] = { - [DRM_IOCTL_NR(DRM_R128_INIT)] = { r128_cce_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_R128_CCE_START)] = { r128_cce_start, 1, 1 }, - [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = { r128_cce_stop, 1, 1 }, - [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = { r128_cce_reset, 1, 1 }, - [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_RESET)] = { r128_engine_reset, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = { r128_fullscreen, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_SWAP)] = { r128_cce_swap, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_FLIP)] = { r128_cce_flip, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_CLEAR)] = { r128_cce_clear, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_VERTEX)] = { r128_cce_vertex, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_INDICES)] = { r128_cce_indices, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_BLIT)] = { r128_cce_blit, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_DEPTH)] = { r128_cce_depth, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = { r128_cce_stipple, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = { r128_cce_indirect, 1, 1 }, - [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = { r128_getparam, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_INIT)] = {r128_cce_init, 1, 1}, + [DRM_IOCTL_NR(DRM_R128_CCE_START)] = {r128_cce_start, 1, 1}, + [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = {r128_cce_stop, 1, 1}, + [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = {r128_cce_reset, 1, 1}, + [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = {r128_cce_idle, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_RESET)] = {r128_engine_reset, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = {r128_fullscreen, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_SWAP)] = {r128_cce_swap, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_FLIP)] = {r128_cce_flip, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_CLEAR)] = {r128_cce_clear, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_VERTEX)] = {r128_cce_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_INDICES)] = {r128_cce_indices, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_BLIT)] = {r128_cce_blit, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_DEPTH)] = {r128_cce_depth, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = {r128_cce_stipple, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = {r128_cce_indirect, 1, 1}, + [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = {r128_getparam, 1, 0}, }; static struct drm_driver_fn driver_fn = { - .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, + .driver_features = + DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | + DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | + DRIVER_IRQ_VBL, .dev_priv_size = sizeof(drm_r128_buf_priv_t), .prerelease = r128_driver_prerelease, .pretakedown = r128_driver_pretakedown, @@ -114,13 +115,14 @@ static struct drm_driver_fn driver_fn = { .num_ioctls = DRM_ARRAY_SIZE(ioctls), .dma_ioctl = r128_cce_buffers, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .fasync = drm_fasync, + } + , }; static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -129,10 +131,10 @@ static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) } static struct pci_driver driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - .probe = probe, - .remove = __devexit_p(drm_cleanup_pci), + .name = DRIVER_NAME, + .id_table = pciidlist, + .probe = probe, + .remove = __devexit_p(drm_cleanup_pci), }; static int __init r128_init(void) @@ -148,6 +150,6 @@ static void __exit r128_exit(void) module_init(r128_init); module_exit(r128_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/linux-core/radeon_drv.c b/linux-core/radeon_drv.c index 43c5c7ef..2ae1838f 100644 --- a/linux-core/radeon_drv.c +++ b/linux-core/radeon_drv.c @@ -29,7 +29,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ - #include #include "drmP.h" #include "drm.h" @@ -39,30 +38,28 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -98,41 +95,44 @@ static struct pci_device_id pciidlist[] = { * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. * Add texture rectangle support for r100. * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which - * clients use to tell the DRM where they think the framebuffer is + * clients use to tell the DRM where they think the framebuffer is * located in the card's address space * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color * and GL_EXT_blend_[func|equation]_separate on r200 */ static drm_ioctl_desc_t ioctls[] = { - [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = { radeon_cp_resume, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = { radeon_cp_texture, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = { radeon_cp_indirect, 1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = { radeon_cp_vertex2, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = { radeon_cp_cmdbuf, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = { radeon_cp_getparam, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = { radeon_cp_flip, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = { radeon_mem_alloc, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_FREE)] = { radeon_mem_free, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = { radeon_mem_init_heap,1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = { radeon_irq_emit, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = { radeon_irq_wait, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = { radeon_cp_setparam, 1, 0 }, + [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, 1, 0}, }; static struct drm_driver_fn driver_fn = { - .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, + .driver_features = + DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | + DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | + DRIVER_IRQ_VBL, .dev_priv_size = sizeof(drm_radeon_buf_priv_t), .preinit = radeon_preinit, .postinit = radeon_postinit, @@ -155,13 +155,14 @@ static struct drm_driver_fn driver_fn = { .num_ioctls = DRM_ARRAY_SIZE(ioctls), .dma_ioctl = radeon_cp_buffers, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .fasync = drm_fasync, + } + , }; static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -170,10 +171,10 @@ static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) } static struct pci_driver driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - .probe = probe, - .remove = __devexit_p(drm_cleanup_pci), + .name = DRIVER_NAME, + .id_table = pciidlist, + .probe = probe, + .remove = __devexit_p(drm_cleanup_pci), }; static int __init radeon_init(void) @@ -189,6 +190,6 @@ static void __exit radeon_exit(void) module_init(radeon_init); module_exit(radeon_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/linux-core/radeon_i2c.c b/linux-core/radeon_i2c.c index 5073884c..bd35f17f 100644 --- a/linux-core/radeon_i2c.c +++ b/linux-core/radeon_i2c.c @@ -31,7 +31,7 @@ #include "radeon_drm.h" #include "radeon_drv.h" -static void gpio_setscl(void* data, int state) +static void gpio_setscl(void *data, int state) { struct radeon_i2c_chan *chan = data; drm_radeon_private_t *dev_priv = chan->dev->dev_private; @@ -45,7 +45,7 @@ static void gpio_setscl(void* data, int state) (void)RADEON_READ(chan->ddc_reg); } -static void gpio_setsda(void* data, int state) +static void gpio_setsda(void *data, int state) { struct radeon_i2c_chan *chan = data; drm_radeon_private_t *dev_priv = chan->dev->dev_private; @@ -59,7 +59,7 @@ static void gpio_setsda(void* data, int state) (void)RADEON_READ(chan->ddc_reg); } -static int gpio_getscl(void* data) +static int gpio_getscl(void *data) { struct radeon_i2c_chan *chan = data; drm_radeon_private_t *dev_priv = chan->dev->dev_private; @@ -70,12 +70,12 @@ static int gpio_getscl(void* data) return (val & VGA_DDC_CLK_INPUT) ? 1 : 0; } -static int gpio_getsda(void* data) +static int gpio_getsda(void *data) { struct radeon_i2c_chan *chan = data; drm_radeon_private_t *dev_priv = chan->dev->dev_private; u32 val; - + val = RADEON_READ(chan->ddc_reg); return (val & VGA_DDC_DATA_INPUT) ? 1 : 0; @@ -86,17 +86,17 @@ static int setup_i2c_bus(struct radeon_i2c_chan *chan, const char *name) int rc; strcpy(chan->adapter.name, name); - chan->adapter.owner = THIS_MODULE; - chan->adapter.id = I2C_ALGO_ATI; - chan->adapter.algo_data = &chan->algo; - chan->adapter.dev.parent = &chan->dev->pdev->dev; - chan->algo.setsda = gpio_setsda; - chan->algo.setscl = gpio_setscl; - chan->algo.getsda = gpio_getsda; - chan->algo.getscl = gpio_getscl; - chan->algo.udelay = 40; - chan->algo.timeout = 20; - chan->algo.data = chan; + chan->adapter.owner = THIS_MODULE; + chan->adapter.id = I2C_ALGO_ATI; + chan->adapter.algo_data = &chan->algo; + chan->adapter.dev.parent = &chan->dev->pdev->dev; + chan->algo.setsda = gpio_setsda; + chan->algo.setscl = gpio_setscl; + chan->algo.getsda = gpio_getsda; + chan->algo.getscl = gpio_getscl; + chan->algo.udelay = 40; + chan->algo.timeout = 20; + chan->algo.data = chan; i2c_set_adapdata(&chan->adapter, chan); @@ -113,7 +113,7 @@ static int setup_i2c_bus(struct radeon_i2c_chan *chan, const char *name) return rc; } -int radeon_create_i2c_busses(drm_device_t *dev) +int radeon_create_i2c_busses(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; int ret; @@ -140,11 +140,11 @@ int radeon_create_i2c_busses(drm_device_t *dev) return 0; } -void radeon_delete_i2c_busses(drm_device_t *dev) +void radeon_delete_i2c_busses(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; int i, ret; - + for (i = 0; i < 4; i++) { if (dev_priv->i2c[i].dev) { ret = i2c_bit_del_bus(&dev_priv->i2c[i].adapter); diff --git a/linux-core/radeon_i2c.h b/linux-core/radeon_i2c.h index 2adc6723..6fc1519d 100644 --- a/linux-core/radeon_i2c.h +++ b/linux-core/radeon_i2c.h @@ -17,13 +17,11 @@ #include struct radeon_i2c_chan { - drm_device_t *dev; - u32 ddc_reg; - struct i2c_adapter adapter; - struct i2c_algo_bit_data algo; + drm_device_t *dev; + u32 ddc_reg; + struct i2c_adapter adapter; + struct i2c_algo_bit_data algo; }; -extern int radeon_create_i2c_busses(drm_device_t *dev); -extern void radeon_delete_i2c_busses(drm_device_t *dev); - - +extern int radeon_create_i2c_busses(drm_device_t * dev); +extern void radeon_delete_i2c_busses(drm_device_t * dev); diff --git a/linux-core/savage_dma.c b/linux-core/savage_dma.c index 401fd942..eb21b09a 100644 --- a/linux-core/savage_dma.c +++ b/linux-core/savage_dma.c @@ -22,59 +22,58 @@ * DEALINGS IN THE SOFTWARE. */ - /*=========================================================*/ +#include /* For task queue support */ +#include + #include "drmP.h" #include "savage_drm.h" #include "savage_drv.h" -#include /* For task queue support */ -#include - #define SAVAGE_DEFAULT_USEC_TIMEOUT 10000 #define SAVAGE_FREELIST_DEBUG 0 -int savage_preinit( drm_device_t *dev, unsigned long chipset ) +int savage_preinit(drm_device_t * dev, unsigned long chipset) { drm_savage_private_t *dev_priv; unsigned mmioBase, fbBase, fbSize, apertureBase; int ret = 0; - dev_priv = drm_alloc( sizeof(drm_savage_private_t), DRM_MEM_DRIVER ); - if ( dev_priv == NULL ) + dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER); + if (dev_priv == NULL) return DRM_ERR(ENOMEM); - memset( dev_priv, 0, sizeof(drm_savage_private_t) ); + memset(dev_priv, 0, sizeof(drm_savage_private_t)); dev->dev_private = (void *)dev_priv; dev_priv->chipset = (enum savage_family)chipset; - if( S3_SAVAGE3D_SERIES(dev_priv->chipset) ) { - fbBase = pci_resource_start( dev->pdev, 0 ); + if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { + fbBase = pci_resource_start(dev->pdev, 0); fbSize = SAVAGE_FB_SIZE_S3; mmioBase = fbBase + fbSize; apertureBase = fbBase + SAVAGE_APERTURE_OFFSET; - } else if( chipset != S3_SUPERSAVAGE ) { - mmioBase = pci_resource_start( dev->pdev, 0 ); - fbBase = pci_resource_start( dev->pdev, 1 ); + } else if (chipset != S3_SUPERSAVAGE) { + mmioBase = pci_resource_start(dev->pdev, 0); + fbBase = pci_resource_start(dev->pdev, 1); fbSize = SAVAGE_FB_SIZE_S4; apertureBase = fbBase + SAVAGE_APERTURE_OFFSET; } else { - mmioBase = pci_resource_start( dev->pdev, 0 ); - fbBase = pci_resource_start( dev->pdev, 1 ); - fbSize = pci_resource_len( dev->pdev, 1 ); - apertureBase = pci_resource_start( dev->pdev, 2 ); + mmioBase = pci_resource_start(dev->pdev, 0); + fbBase = pci_resource_start(dev->pdev, 1); + fbSize = pci_resource_len(dev->pdev, 1); + apertureBase = pci_resource_start(dev->pdev, 2); } - if( (ret = drm_initmap( dev, mmioBase, SAVAGE_MMIO_SIZE, - _DRM_REGISTERS, 0 ))) + if ((ret = drm_initmap(dev, mmioBase, SAVAGE_MMIO_SIZE, + _DRM_REGISTERS, 0))) return ret; - if( (ret = drm_initmap( dev, fbBase, fbSize, - _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING ))) + if ((ret = drm_initmap(dev, fbBase, fbSize, + _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING))) return ret; - if( (ret = drm_initmap( dev, apertureBase, SAVAGE_APERTURE_SIZE, - _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING ))) + if ((ret = drm_initmap(dev, apertureBase, SAVAGE_APERTURE_SIZE, + _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING))) return ret; return ret; diff --git a/linux-core/savage_drm.h b/linux-core/savage_drm.h index f7d4f404..ee06d68a 100644 --- a/linux-core/savage_drm.h +++ b/linux-core/savage_drm.h @@ -34,22 +34,20 @@ #define DRM_SAVAGE_MEM_LOCATION_AGP 2 #define DRM_SAVAGE_DMA_AGP_SIZE (16*1024*1024) -typedef struct drm_savage_alloc_cont_mem -{ - size_t size; /*size of buffer*/ - unsigned long type; /*4k page or word*/ - unsigned long alignment; - unsigned long location; /*agp or pci*/ - - unsigned long phyaddress; - unsigned long linear; +typedef struct drm_savage_alloc_cont_mem { + size_t size; /*size of buffer */ + unsigned long type; /*4k page or word */ + unsigned long alignment; + unsigned long location; /*agp or pci */ + + unsigned long phyaddress; + unsigned long linear; } drm_savage_alloc_cont_mem_t; -typedef struct drm_savage_get_physcis_address -{ - unsigned long v_address; - unsigned long p_address; -}drm_savage_get_physcis_address_t; +typedef struct drm_savage_get_physcis_address { + unsigned long v_address; + unsigned long p_address; +} drm_savage_get_physcis_address_t; /*ioctl number*/ #define DRM_IOCTL_SAVAGE_ALLOC_CONTINUOUS_MEM \ @@ -69,12 +67,12 @@ typedef struct drm_savage_get_physcis_address #define SAVAGE_UPLOAD_CTX 0x1 #define SAVAGE_UPLOAD_TEX0 0x2 #define SAVAGE_UPLOAD_TEX1 0x4 -#define SAVAGE_UPLOAD_PIPE 0x8 /* <- seems should be removed, Jiayo Hsu */ -#define SAVAGE_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ -#define SAVAGE_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ +#define SAVAGE_UPLOAD_PIPE 0x8 /* <- seems should be removed, Jiayo Hsu */ +#define SAVAGE_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ +#define SAVAGE_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ #define SAVAGE_UPLOAD_2D 0x40 -#define SAVAGE_WAIT_AGE 0x80 /* handled client-side */ -#define SAVAGE_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ +#define SAVAGE_WAIT_AGE 0x80 /* handled client-side */ +#define SAVAGE_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ /*frank:add Buffer state 2001/11/15*/ #define SAVAGE_UPLOAD_BUFFERS 0x200 /* original marked off in MGA drivers , Jiayo Hsu Oct.23,2001 */ @@ -93,10 +91,10 @@ typedef struct drm_savage_get_physcis_address #define SAVAGE_CARD_HEAP 0 #define SAVAGE_AGP_HEAP 1 #define SAVAGE_NR_TEX_HEAPS 2 -#define SAVAGE_NR_TEX_REGIONS 16 /* num. of global texture manage list element*/ -#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 /* each region 64K, Jiayo Hsu */ +#define SAVAGE_NR_TEX_REGIONS 16 /* num. of global texture manage list element */ +#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 /* each region 64K, Jiayo Hsu */ -#endif /* __SAVAGE_SAREA_DEFINES__ */ +#endif /* __SAVAGE_SAREA_DEFINES__ */ /* drm_tex_region_t define in drm.h */ @@ -108,22 +106,21 @@ typedef struct { unsigned int pitch; } drm_savage_server_regs_t; - typedef struct _drm_savage_sarea { /* The channel for communication of state information to the kernel * on firing a vertex dma buffer. */ - unsigned int setup[28]; /* 3D context registers */ - drm_savage_server_regs_t server_state; - - unsigned int dirty; - - unsigned int vertsize; /* vertext size */ + unsigned int setup[28]; /* 3D context registers */ + drm_savage_server_regs_t server_state; + + unsigned int dirty; + + unsigned int vertsize; /* vertext size */ /* The current cliprects, or a subset thereof. */ - drm_clip_rect_t boxes[SAVAGE_NR_SAREA_CLIPRECTS]; - unsigned int nbox; + drm_clip_rect_t boxes[SAVAGE_NR_SAREA_CLIPRECTS]; + unsigned int nbox; /* Information about the most recently used 3d drawable. The * client fills in the req_* fields, the server fills in the @@ -132,58 +129,56 @@ typedef struct _drm_savage_sarea { * The client clears the exported_drawable field before * clobbering the boxes data. */ - unsigned int req_drawable; /* the X drawable id */ - unsigned int req_draw_buffer; /* SAVAGE_FRONT or SAVAGE_BACK */ + unsigned int req_drawable; /* the X drawable id */ + unsigned int req_draw_buffer; /* SAVAGE_FRONT or SAVAGE_BACK */ - unsigned int exported_drawable; + unsigned int exported_drawable; unsigned int exported_index; - unsigned int exported_stamp; - unsigned int exported_buffers; - unsigned int exported_nfront; - unsigned int exported_nback; + unsigned int exported_stamp; + unsigned int exported_buffers; + unsigned int exported_nfront; + unsigned int exported_nback; int exported_back_x, exported_front_x, exported_w; int exported_back_y, exported_front_y, exported_h; - drm_clip_rect_t exported_boxes[SAVAGE_NR_SAREA_CLIPRECTS]; + drm_clip_rect_t exported_boxes[SAVAGE_NR_SAREA_CLIPRECTS]; /* Counters for aging textures and for client-side throttling. */ unsigned int status[4]; - /* LRU lists for texture memory in agp space and on the card. */ - drm_tex_region_t texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS+1]; + drm_tex_region_t texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + + 1]; unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; /* Mechanism to validate card state. */ - int ctxOwner; - unsigned long shadow_status[64];/*too big?*/ + int ctxOwner; + unsigned long shadow_status[64]; /*too big? */ - /*agp offset*/ + /*agp offset */ unsigned long agp_offset; -} drm_savage_sarea_t,*drm_savage_sarea_ptr; - - +} drm_savage_sarea_t, *drm_savage_sarea_ptr; typedef struct drm_savage_init { - unsigned long sarea_priv_offset; + unsigned long sarea_priv_offset; int chipset; - int sgram; + int sgram; unsigned int maccess; - unsigned int fb_cpp; + unsigned int fb_cpp; unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; + unsigned int back_offset, back_pitch; - unsigned int depth_cpp; - unsigned int depth_offset, depth_pitch; + unsigned int depth_cpp; + unsigned int depth_offset, depth_pitch; - unsigned int texture_offset[SAVAGE_NR_TEX_HEAPS]; - unsigned int texture_size[SAVAGE_NR_TEX_HEAPS]; + unsigned int texture_offset[SAVAGE_NR_TEX_HEAPS]; + unsigned int texture_size[SAVAGE_NR_TEX_HEAPS]; unsigned long fb_offset; unsigned long mmio_offset; @@ -192,7 +187,7 @@ typedef struct drm_savage_init { typedef struct drm_savage_fullscreen { enum { - SAVAGE_INIT_FULLSCREEN = 0x01, + SAVAGE_INIT_FULLSCREEN = 0x01, SAVAGE_CLEANUP_FULLSCREEN = 0x02 } func; } drm_savage_fullscreen_t; @@ -206,16 +201,16 @@ typedef struct drm_savage_clear { } drm_savage_clear_t; typedef struct drm_savage_vertex { - int idx; /* buffer to queue */ - int used; /* bytes in use */ - int discard; /* client finished with buffer? */ + int idx; /* buffer to queue */ + int used; /* bytes in use */ + int discard; /* client finished with buffer? */ } drm_savage_vertex_t; typedef struct drm_savage_indices { - int idx; /* buffer to queue */ + int idx; /* buffer to queue */ unsigned int start; unsigned int end; - int discard; /* client finished with buffer? */ + int discard; /* client finished with buffer? */ } drm_savage_indices_t; typedef struct drm_savage_iload { @@ -231,7 +226,7 @@ typedef struct _drm_savage_blit { int src_pitch, dst_pitch; int delta_sx, delta_sy; int delta_dx, delta_dy; - int height, ydir; /* flip image vertically */ + int height, ydir; /* flip image vertically */ int source_pitch, dest_pitch; } drm_savage_blit_t; diff --git a/linux-core/savage_drv.c b/linux-core/savage_drv.c index 9f02f81f..db7dbe0d 100644 --- a/linux-core/savage_drv.c +++ b/linux-core/savage_drv.c @@ -46,14 +46,14 @@ int savage_alloc_continuous_mem(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - drm_savage_alloc_cont_mem_t cont_mem; + drm_savage_alloc_cont_mem_t cont_mem; unsigned long size,addr; void * ret; int i; mem_map_t *p; pgprot_t flags; - /* add to list */ + /* add to list */ drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_map_t *map; @@ -61,33 +61,33 @@ int savage_alloc_continuous_mem(struct inode *inode, struct file *filp, if (copy_from_user(&cont_mem,(drm_savage_alloc_cont_mem_t *)arg,sizeof(cont_mem))) return -EFAULT; - + map = savage_alloc)( sizeof(*map), DRM_MEM_MAPS ); if ( !map ) return -ENOMEM; - + /*check the parameters*/ if (cont_mem.size <= 0 ) return -EINVAL; - + size = cont_mem.type * cont_mem.size; printk("[drm]JTLIsize = %lu\n",size); - + ret = (void *)__get_free_pages(GFP_KERNEL, get_order(size)); if (ret == NULL) { printk("Kalloc error\n"); return 0; } - + /*set the reserverd flag so that the remap_page_range can map these page*/ for(i=0,p=virt_to_page(ret);i< size /PAGE_SIZE; i++,p++) SetPageReserved(p); - + cont_mem.phyaddress = virt_to_bus(ret); cont_mem.location = DRM_SAVAGE_MEM_LOCATION_PCI; /* pci only at present*/ - - + + /*Map the memory to user space*/ down_write(¤t->mm->mmap_sem); addr=do_mmap(NULL,0,size,PROT_READ|PROT_WRITE,MAP_PRIVATE,cont_mem.phyaddress); @@ -97,19 +97,19 @@ int savage_alloc_continuous_mem(struct inode *inode, struct file *filp, if (remap_page_range(addr,cont_mem.phyaddress,size,flags)) return -EFAULT; up_write(¤t->mm->mmap_sem); - + for(i=0,p=virt_to_page(ret);i< size /PAGE_SIZE; i++,p++) ClearPageReserved(p); - + cont_mem.linear = addr; - + /*map list*/ map->handle = ret; /* to distinguish with other*/ map->offset = cont_mem.phyaddress; map->size = size; map->mtrr=-1; /*map-flags,type??*/ - + list = savage_alloc)(sizeof(*list), DRM_MEM_MAPS); if(!list) { savage_free)(map, sizeof(*map), DRM_MEM_MAPS); @@ -117,54 +117,54 @@ int savage_alloc_continuous_mem(struct inode *inode, struct file *filp, } memset(list, 0, sizeof(*list)); list->map = map; - + down(&dev->struct_sem); list_add(&list->head, &dev->maplist->head); up(&dev->struct_sem); - + if (copy_to_user((drm_savage_alloc_cont_mem_t *)arg,&cont_mem,sizeof(cont_mem))) return -EFAULT; for(i=0,p=virt_to_page(ret);i< size /PAGE_SIZE; i++,p++) atomic_set(&p->count,1); - return 1;/*success*/ + return 1;/*success*/ } int savage_get_physics_address(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - + drm_savage_get_physcis_address_t req; unsigned long buf; pgd_t *pgd; pmd_t *pmd; pte_t *pte; struct mm_struct *mm; - + if (copy_from_user(&req,(drm_savage_get_physcis_address_t *)arg,sizeof(req))) return -EFAULT; buf = req.v_address; - + /*What kind of virtual address ?*/ if (buf >= (unsigned long)high_memory) mm = &init_mm; else mm = current->mm; - + #ifdef LINUX_24 spin_lock(&mm->page_table_lock); #endif - + pgd=pgd_offset(mm,buf); pmd=pmd_offset(pgd,buf); pte=pte_offset_map(pmd,buf); - + if (!pte_present(*pte)) return -EFAULT; - + req.p_address = ((pte_val(*pte) &PAGE_MASK) |( buf&(PAGE_SIZE-1))); - + if (copy_to_user((drm_savage_get_physcis_address_t *)arg,&req,sizeof(req))) return -EFAULT; return 1; @@ -174,10 +174,10 @@ int savage_get_physics_address(struct inode *inode, struct file *filp, int savage_free_cont_mem(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - drm_savage_alloc_cont_mem_t cont_mem; + drm_savage_alloc_cont_mem_t cont_mem; unsigned long size; - /*map list */ + /*map list */ drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_map_t *map; @@ -194,10 +194,10 @@ int savage_free_cont_mem(struct inode *inode, struct file *filp, list_for_each(list,&dev->maplist->head) { r_list = (drm_map_list_t *) list; - + if(r_list->map && r_list->map->offset == cont_mem.phyaddress ) - break; + break; } /*find none*/ if(list == (&dev->maplist->head)) { @@ -279,7 +279,7 @@ static drm_ioctl_desc_t ioctls[] = { [DRM_IOCTL_NR(DRM_SAVAGE_ALLOC_CONTINUOUS_MEM)] = {savage_alloc_continuous_mem, 1, 0}, [DRM_IOCTL_NR(DRM_SAVAGE_GET_PHYSICS_ADDRESS)] = {savage_get_physics_address, 1, 0}, [DRM_IOCTL_NR(DRM_SAVAGE_FREE_CONTINUOUS_MEM)] = {savage_free_cont_mem, 1, 0}, -#endif +#endif }; static struct drm_driver_fn driver_fn = { diff --git a/linux-core/savage_drv.h b/linux-core/savage_drv.h index 4931d74a..69ae8692 100644 --- a/linux-core/savage_drv.h +++ b/linux-core/savage_drv.h @@ -26,19 +26,19 @@ /* these chip tags should match the ones in the 2D driver in savage_regs.h. */ enum savage_family { - S3_UNKNOWN = 0, - S3_SAVAGE3D, - S3_SAVAGE_MX, - S3_SAVAGE4, - S3_PROSAVAGE, - S3_TWISTER, - S3_PROSAVAGEDDR, - S3_SUPERSAVAGE, - S3_SAVAGE2000, - S3_LAST + S3_UNKNOWN = 0, + S3_SAVAGE3D, + S3_SAVAGE_MX, + S3_SAVAGE4, + S3_PROSAVAGE, + S3_TWISTER, + S3_PROSAVAGEDDR, + S3_SUPERSAVAGE, + S3_SAVAGE2000, + S3_LAST }; -extern int savage_preinit( drm_device_t *dev, unsigned long chipset ); +extern int savage_preinit(drm_device_t * dev, unsigned long chipset); #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) @@ -62,13 +62,13 @@ typedef struct drm_savage_private { enum savage_family chipset; unsigned flags; - + } drm_savage_private_t; -#define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ -#define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ -#define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */ -#define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ -#define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ +#define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ +#define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ +#define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */ +#define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ +#define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ -#endif /* end #ifndef __SAVAGE_DRV_ */ +#endif /* end #ifndef __SAVAGE_DRV_ */ diff --git a/linux-core/sis_drv.c b/linux-core/sis_drv.c index d455dbc5..4db7b5c7 100644 --- a/linux-core/sis_drv.c +++ b/linux-core/sis_drv.c @@ -10,11 +10,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -32,30 +32,28 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -64,12 +62,12 @@ static struct pci_device_id pciidlist[] = { }; static drm_ioctl_desc_t ioctls[] = { - [DRM_IOCTL_NR(DRM_SIS_FB_ALLOC)] = { sis_fb_alloc, 1, 0 }, - [DRM_IOCTL_NR(DRM_SIS_FB_FREE)] = { sis_fb_free, 1, 0 }, - [DRM_IOCTL_NR(DRM_SIS_AGP_INIT)] = { sis_ioctl_agp_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_SIS_AGP_ALLOC)] = { sis_ioctl_agp_alloc, 1, 0 }, - [DRM_IOCTL_NR(DRM_SIS_AGP_FREE)] = { sis_ioctl_agp_free, 1, 0 }, - [DRM_IOCTL_NR(DRM_SIS_FB_INIT)] = { sis_fb_init, 1, 1 } + [DRM_IOCTL_NR(DRM_SIS_FB_ALLOC)] = {sis_fb_alloc, 1, 0}, + [DRM_IOCTL_NR(DRM_SIS_FB_FREE)] = {sis_fb_free, 1, 0}, + [DRM_IOCTL_NR(DRM_SIS_AGP_INIT)] = {sis_ioctl_agp_init, 1, 1}, + [DRM_IOCTL_NR(DRM_SIS_AGP_ALLOC)] = {sis_ioctl_agp_alloc, 1, 0}, + [DRM_IOCTL_NR(DRM_SIS_AGP_FREE)] = {sis_ioctl_agp_free, 1, 0}, + [DRM_IOCTL_NR(DRM_SIS_FB_INIT)] = {sis_fb_init, 1, 1} }; static struct drm_driver_fn driver_fn = { @@ -84,13 +82,13 @@ static struct drm_driver_fn driver_fn = { .ioctls = ioctls, .num_ioctls = DRM_ARRAY_SIZE(ioctls), .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .fasync = drm_fasync, + }, }; static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -99,10 +97,10 @@ static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) } static struct pci_driver driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - .probe = probe, - .remove = __devexit_p(drm_cleanup_pci), + .name = DRIVER_NAME, + .id_table = pciidlist, + .probe = probe, + .remove = __devexit_p(drm_cleanup_pci), }; static int __init sis_init(void) @@ -118,6 +116,6 @@ static void __exit sis_exit(void) module_init(sis_init); module_exit(sis_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/linux-core/tdfx_drv.c b/linux-core/tdfx_drv.c index db00fa5a..78aad6fc 100644 --- a/linux-core/tdfx_drv.c +++ b/linux-core/tdfx_drv.c @@ -36,30 +36,28 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -75,13 +73,13 @@ static struct drm_driver_fn driver_fn = { .postinit = postinit, .version = version, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .fasync = drm_fasync, + }, }; static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -90,10 +88,10 @@ static int probe(struct pci_dev *pdev, const struct pci_device_id *ent) } static struct pci_driver driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - .probe = probe, - .remove = __devexit_p(drm_cleanup_pci), + .name = DRIVER_NAME, + .id_table = pciidlist, + .probe = probe, + .remove = __devexit_p(drm_cleanup_pci), }; static int __init tdfx_init(void) @@ -109,6 +107,6 @@ static void __exit tdfx_exit(void) module_init(tdfx_init); module_exit(tdfx_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/shared-core/drm.h b/shared-core/drm.h index f9469129..0d907629 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -1,7 +1,7 @@ /** - * \file drm.h + * \file drm.h * Header for the Direct Rendering Manager - * + * * \author Rickard E. (Rik) Faith * * \par Acknowledgments: @@ -39,7 +39,7 @@ * The Direct Rendering Manager (DRM) is a device-independent kernel-level * device driver that provides support for the XFree86 Direct Rendering * Infrastructure (DRI). - * + * * The DRM supports the Direct Rendering Infrastructure (DRI) in four major * ways: * -# The DRM provides synchronized access to the graphics hardware via @@ -52,8 +52,8 @@ * switch. * -# The DRM is extensible via the use of small device-specific modules * that rely extensively on the API exported by the DRM module. - * - */ + * + */ #ifndef _DRM_H_ #define _DRM_H_ @@ -79,7 +79,7 @@ #define ioctl(a,b,c) xf86ioctl(a,b,c) #else #include -#endif /* __FreeBSD__ && xf86ioctl */ +#endif /* __FreeBSD__ && xf86ioctl */ #define DRM_IOCTL_NR(n) ((n) & 0xff) #define DRM_IOC_VOID IOC_VOID #define DRM_IOC_READ IOC_OUT @@ -125,16 +125,14 @@ #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) - -typedef unsigned long drm_handle_t; /**< To mapped regions */ -typedef unsigned int drm_context_t; /**< GLXContext handle */ -typedef unsigned int drm_drawable_t; -typedef unsigned int drm_magic_t; /**< Magic for authentication */ - +typedef unsigned long drm_handle_t; /**< To mapped regions */ +typedef unsigned int drm_context_t; /**< GLXContext handle */ +typedef unsigned int drm_drawable_t; +typedef unsigned int drm_magic_t; /**< Magic for authentication */ /** * Cliprect. - * + * * \warning If you change this structure, make sure you change * XF86DRIClipRectRec in the server as well * @@ -142,22 +140,21 @@ typedef unsigned int drm_magic_t; /**< Magic for authentication */ * backwards-compatibility reasons. */ typedef struct drm_clip_rect { - unsigned short x1; - unsigned short y1; - unsigned short x2; - unsigned short y2; + unsigned short x1; + unsigned short y1; + unsigned short x2; + unsigned short y2; } drm_clip_rect_t; - /** * Texture region, */ typedef struct drm_tex_region { - unsigned char next; - unsigned char prev; - unsigned char in_use; - unsigned char padding; - unsigned int age; + unsigned char next; + unsigned char prev; + unsigned char in_use; + unsigned char padding; + unsigned int age; } drm_tex_region_t; /** @@ -169,14 +166,13 @@ typedef struct drm_tex_region { */ typedef struct drm_hw_lock { __volatile__ unsigned int lock; /**< lock variable */ - char padding[60]; /**< Pad to cache line */ + char padding[60]; /**< Pad to cache line */ } drm_hw_lock_t; - /* This is beyond ugly, and only works on GCC. However, it allows me to use * drm.h in places (i.e., in the X-server) where I can't use size_t. The real * fix is to use uint32_t instead of size_t, but that fix will break existing - * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will* + * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will* * eventually happen, though. I chose 'unsigned long' to be the fallback type * because that works on all the platforms I know about. Hopefully, the * real fix will happen before that bites us. @@ -191,22 +187,21 @@ typedef struct drm_hw_lock { /** * DRM_IOCTL_VERSION ioctl argument type. - * + * * \sa drmGetVersion(). */ typedef struct drm_version { - int version_major; /**< Major version */ - int version_minor; /**< Minor version */ - int version_patchlevel;/**< Patch level */ + int version_major; /**< Major version */ + int version_minor; /**< Minor version */ + int version_patchlevel; /**< Patch level */ DRM_SIZE_T name_len; /**< Length of name buffer */ - char __user *name; /**< Name of driver */ + char __user *name; /**< Name of driver */ DRM_SIZE_T date_len; /**< Length of date buffer */ - char __user *date; /**< User-space buffer to hold date */ + char __user *date; /**< User-space buffer to hold date */ DRM_SIZE_T desc_len; /**< Length of desc buffer */ - char __user *desc; /**< User-space buffer to hold desc */ + char __user *desc; /**< User-space buffer to hold desc */ } drm_version_t; - /** * DRM_IOCTL_GET_UNIQUE ioctl argument type. * @@ -214,22 +209,20 @@ typedef struct drm_version { */ typedef struct drm_unique { DRM_SIZE_T unique_len; /**< Length of unique */ - char __user *unique; /**< Unique name for driver instantiation */ + char __user *unique; /**< Unique name for driver instantiation */ } drm_unique_t; #undef DRM_SIZE_T typedef struct drm_list { - int count; /**< Length of user-space structures */ - drm_version_t __user *version; + int count; /**< Length of user-space structures */ + drm_version_t __user *version; } drm_list_t; - typedef struct drm_block { - int unused; + int unused; } drm_block_t; - /** * DRM_IOCTL_CONTROL ioctl argument type. * @@ -241,43 +234,39 @@ typedef struct drm_control { DRM_RM_COMMAND, DRM_INST_HANDLER, DRM_UNINST_HANDLER - } func; - int irq; + } func; + int irq; } drm_control_t; - /** * Type of memory to map. */ typedef enum drm_map_type { - _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ - _DRM_REGISTERS = 1, /**< no caching, no core dump */ - _DRM_SHM = 2, /**< shared, cached */ - _DRM_AGP = 3, /**< AGP/GART */ + _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ + _DRM_REGISTERS = 1, /**< no caching, no core dump */ + _DRM_SHM = 2, /**< shared, cached */ + _DRM_AGP = 3, /**< AGP/GART */ _DRM_SCATTER_GATHER = 4 /**< Scatter/gather memory for PCI DMA */ } drm_map_type_t; - /** * Memory mapping flags. */ typedef enum drm_map_flags { - _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ - _DRM_READ_ONLY = 0x02, - _DRM_LOCKED = 0x04, /**< shared, cached, locked */ - _DRM_KERNEL = 0x08, /**< kernel requires access */ + _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ + _DRM_READ_ONLY = 0x02, + _DRM_LOCKED = 0x04, /**< shared, cached, locked */ + _DRM_KERNEL = 0x08, /**< kernel requires access */ _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ - _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ - _DRM_REMOVABLE = 0x40 /**< Removable mapping */ + _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ + _DRM_REMOVABLE = 0x40 /**< Removable mapping */ } drm_map_flags_t; - typedef struct drm_ctx_priv_map { - unsigned int ctx_id; /**< Context requesting private mapping */ - void *handle; /**< Handle of map */ + unsigned int ctx_id; /**< Context requesting private mapping */ + void *handle; /**< Handle of map */ } drm_ctx_priv_map_t; - /** * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls * argument type. @@ -285,30 +274,28 @@ typedef struct drm_ctx_priv_map { * \sa drmAddMap(). */ typedef struct drm_map { - unsigned long offset; /**< Requested physical address (0 for SAREA)*/ - unsigned long size; /**< Requested physical size (bytes) */ - drm_map_type_t type; /**< Type of memory to map */ + unsigned long offset; /**< Requested physical address (0 for SAREA)*/ + unsigned long size; /**< Requested physical size (bytes) */ + drm_map_type_t type; /**< Type of memory to map */ drm_map_flags_t flags; /**< Flags */ - void *handle; /**< User-space: "Handle" to pass to mmap() */ + void *handle; /**< User-space: "Handle" to pass to mmap() */ /**< Kernel-space: kernel-virtual address */ - int mtrr; /**< MTRR slot used */ - /* Private data */ + int mtrr; /**< MTRR slot used */ + /* Private data */ } drm_map_t; - /** * DRM_IOCTL_GET_CLIENT ioctl argument type. */ typedef struct drm_client { - int idx; /**< Which client desired? */ - int auth; /**< Is client authenticated? */ - unsigned long pid; /**< Process ID */ - unsigned long uid; /**< User ID */ - unsigned long magic; /**< Magic */ - unsigned long iocs; /**< Ioctl count */ + int idx; /**< Which client desired? */ + int auth; /**< Is client authenticated? */ + unsigned long pid; /**< Process ID */ + unsigned long uid; /**< User ID */ + unsigned long magic; /**< Magic */ + unsigned long iocs; /**< Ioctl count */ } drm_client_t; - typedef enum { _DRM_STAT_LOCK, _DRM_STAT_OPENS, @@ -326,63 +313,58 @@ typedef enum { _DRM_STAT_DMA, /**< DMA */ _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ _DRM_STAT_MISSED /**< Missed DMA opportunity */ - - /* Add to the *END* of the list */ + /* Add to the *END* of the list */ } drm_stat_type_t; - /** * DRM_IOCTL_GET_STATS ioctl argument type. */ typedef struct drm_stats { unsigned long count; struct { - unsigned long value; + unsigned long value; drm_stat_type_t type; } data[15]; } drm_stats_t; - /** * Hardware locking flags. */ typedef enum drm_lock_flags { - _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ - _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ - _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ - _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ - /* These *HALT* flags aren't supported yet - -- they will be used to support the - full-screen DGA-like mode. */ + _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ + _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ + _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ + _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ + /* These *HALT* flags aren't supported yet + -- they will be used to support the + full-screen DGA-like mode. */ _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ } drm_lock_flags_t; - /** * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. - * + * * \sa drmGetLock() and drmUnlock(). */ typedef struct drm_lock { - int context; + int context; drm_lock_flags_t flags; } drm_lock_t; - /** * DMA flags * - * \warning + * \warning * These values \e must match xf86drm.h. * * \sa drm_dma. */ -typedef enum drm_dma_flags { - /* Flags for DMA buffer dispatch */ - _DRM_DMA_BLOCK = 0x01, /**< +typedef enum drm_dma_flags { + /* Flags for DMA buffer dispatch */ + _DRM_DMA_BLOCK = 0x01, /**< * Block until buffer dispatched. - * + * * \note The buffer may not yet have * been processed by the hardware -- * getting a hardware lock with the @@ -391,78 +373,72 @@ typedef enum drm_dma_flags { * processed. */ _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ - _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ + _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ - /* Flags for DMA buffer request */ - _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ - _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ - _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ + /* Flags for DMA buffer request */ + _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ + _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ + _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ } drm_dma_flags_t; - /** * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. * * \sa drmAddBufs(). */ typedef struct drm_buf_desc { - int count; /**< Number of buffers of this size */ - int size; /**< Size in bytes */ - int low_mark; /**< Low water mark */ - int high_mark; /**< High water mark */ + int count; /**< Number of buffers of this size */ + int size; /**< Size in bytes */ + int low_mark; /**< Low water mark */ + int high_mark; /**< High water mark */ enum { - _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ - _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ - _DRM_SG_BUFFER = 0x04 /**< Scatter/gather memory buffer */ - } flags; - unsigned long agp_start; /**< + _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ + _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ + _DRM_SG_BUFFER = 0x04 /**< Scatter/gather memory buffer */ + } flags; + unsigned long agp_start; /**< * Start address of where the AGP buffers are * in the AGP aperture */ } drm_buf_desc_t; - /** * DRM_IOCTL_INFO_BUFS ioctl argument type. */ typedef struct drm_buf_info { - int count; /**< Number of buffers described in list */ + int count; /**< Number of buffers described in list */ drm_buf_desc_t __user *list; /**< List of buffer descriptions */ } drm_buf_info_t; - /** * DRM_IOCTL_FREE_BUFS ioctl argument type. */ typedef struct drm_buf_free { - int count; - int __user *list; + int count; + int __user *list; } drm_buf_free_t; - /** * Buffer information * * \sa drm_buf_map. */ typedef struct drm_buf_pub { - int idx; /**< Index into the master buffer list */ - int total; /**< Buffer size */ - int used; /**< Amount of buffer in use (for DMA) */ - void __user *address; /**< Address of buffer */ + int idx; /**< Index into the master buffer list */ + int total; /**< Buffer size */ + int used; /**< Amount of buffer in use (for DMA) */ + void __user *address; /**< Address of buffer */ } drm_buf_pub_t; - /** * DRM_IOCTL_MAP_BUFS ioctl argument type. */ typedef struct drm_buf_map { - int count; /**< Length of the buffer list */ - void __user *virtual; /**< Mmap'd area in user-virtual */ + int count; /**< Length of the buffer list */ + void __user *virtual; /**< Mmap'd area in user-virtual */ drm_buf_pub_t __user *list; /**< Buffer information */ } drm_buf_map_t; - /** * DRM_IOCTL_DMA ioctl argument type. * @@ -471,61 +447,55 @@ typedef struct drm_buf_map { * \sa drmDMA(). */ typedef struct drm_dma { - int context; /**< Context handle */ - int send_count; /**< Number of buffers to send */ - int __user *send_indices; /**< List of handles to buffers */ - int __user *send_sizes; /**< Lengths of data to send */ + int context; /**< Context handle */ + int send_count; /**< Number of buffers to send */ + int __user *send_indices; /**< List of handles to buffers */ + int __user *send_sizes; /**< Lengths of data to send */ drm_dma_flags_t flags; /**< Flags */ - int request_count; /**< Number of buffers requested */ - int request_size; /**< Desired size for buffers */ - int __user *request_indices; /**< Buffer information */ - int __user *request_sizes; - int granted_count; /**< Number of buffers granted */ + int request_count; /**< Number of buffers requested */ + int request_size; /**< Desired size for buffers */ + int __user *request_indices; /**< Buffer information */ + int __user *request_sizes; + int granted_count; /**< Number of buffers granted */ } drm_dma_t; - typedef enum { _DRM_CONTEXT_PRESERVED = 0x01, - _DRM_CONTEXT_2DONLY = 0x02 + _DRM_CONTEXT_2DONLY = 0x02 } drm_ctx_flags_t; - /** * DRM_IOCTL_ADD_CTX ioctl argument type. * * \sa drmCreateContext() and drmDestroyContext(). */ typedef struct drm_ctx { - drm_context_t handle; + drm_context_t handle; drm_ctx_flags_t flags; } drm_ctx_t; - /** * DRM_IOCTL_RES_CTX ioctl argument type. */ typedef struct drm_ctx_res { - int count; - drm_ctx_t __user *contexts; + int count; + drm_ctx_t __user *contexts; } drm_ctx_res_t; - /** * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. */ typedef struct drm_draw { - drm_drawable_t handle; + drm_drawable_t handle; } drm_draw_t; - /** * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. */ typedef struct drm_auth { - drm_magic_t magic; + drm_magic_t magic; } drm_auth_t; - /** * DRM_IOCTL_IRQ_BUSID ioctl argument type. * @@ -538,24 +508,20 @@ typedef struct drm_irq_busid { int funcnum; /**< function number */ } drm_irq_busid_t; - typedef enum { - _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ - _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ - _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ + _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ + _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ + _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ } drm_vblank_seq_type_t; - #define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL - struct drm_wait_vblank_request { drm_vblank_seq_type_t type; unsigned int sequence; unsigned long signal; }; - struct drm_wait_vblank_reply { drm_vblank_seq_type_t type; unsigned int sequence; @@ -563,7 +529,6 @@ struct drm_wait_vblank_reply { long tval_usec; }; - /** * DRM_IOCTL_WAIT_VBLANK ioctl argument type. * @@ -574,7 +539,6 @@ typedef union drm_wait_vblank { struct drm_wait_vblank_reply reply; } drm_wait_vblank_t; - /** * DRM_IOCTL_AGP_ENABLE ioctl argument type. * @@ -584,7 +548,6 @@ typedef struct drm_agp_mode { unsigned long mode; /**< AGP mode */ } drm_agp_mode_t; - /** * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. * @@ -593,22 +556,20 @@ typedef struct drm_agp_mode { typedef struct drm_agp_buffer { unsigned long size; /**< In bytes -- will round to page boundary */ unsigned long handle; /**< Used for binding / unbinding */ - unsigned long type; /**< Type of memory to allocate */ - unsigned long physical; /**< Physical used by i810 */ + unsigned long type; /**< Type of memory to allocate */ + unsigned long physical; /**< Physical used by i810 */ } drm_agp_buffer_t; - /** * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. * * \sa drmAgpBind() and drmAgpUnbind(). */ typedef struct drm_agp_binding { - unsigned long handle; /**< From drm_agp_buffer */ + unsigned long handle; /**< From drm_agp_buffer */ unsigned long offset; /**< In bytes -- will round to page boundary */ } drm_agp_binding_t; - /** * DRM_IOCTL_AGP_INFO ioctl argument type. * @@ -617,22 +578,21 @@ typedef struct drm_agp_binding { * drmAgpVendorId() and drmAgpDeviceId(). */ typedef struct drm_agp_info { - int agp_version_major; - int agp_version_minor; - unsigned long mode; - unsigned long aperture_base; /**< physical address */ - unsigned long aperture_size; /**< bytes */ - unsigned long memory_allowed; /**< bytes */ - unsigned long memory_used; + int agp_version_major; + int agp_version_minor; + unsigned long mode; + unsigned long aperture_base; /**< physical address */ + unsigned long aperture_size; /**< bytes */ + unsigned long memory_allowed; /**< bytes */ + unsigned long memory_used; /** \name PCI information */ - /*@{*/ + /*@{ */ unsigned short id_vendor; unsigned short id_device; - /*@}*/ + /*@} */ } drm_agp_info_t; - /** * DRM_IOCTL_SG_ALLOC ioctl argument type. */ @@ -651,7 +611,6 @@ typedef struct drm_set_version { int drm_dd_minor; } drm_set_version_t; - /** * \name Ioctls Definitions */ @@ -719,7 +678,6 @@ typedef struct drm_set_version { /*@}*/ - /** * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x79. diff --git a/shared-core/drm_sarea.h b/shared-core/drm_sarea.h index 40f7d5f1..0d5baf69 100644 --- a/shared-core/drm_sarea.h +++ b/shared-core/drm_sarea.h @@ -1,5 +1,5 @@ /** - * \file drm_sarea.h + * \file drm_sarea.h * \brief SAREA definitions * * \author Michel D�zer @@ -38,7 +38,7 @@ #if defined(__alpha__) #define SAREA_MAX 0x2000 #elif defined(__ia64__) -#define SAREA_MAX 0x10000 /* 64kB */ +#define SAREA_MAX 0x10000 /* 64kB */ #else /* Intel 830M driver needs at least 8k SAREA */ #define SAREA_MAX 0x2000 @@ -51,28 +51,28 @@ /** SAREA drawable */ typedef struct drm_sarea_drawable { - unsigned int stamp; - unsigned int flags; + unsigned int stamp; + unsigned int flags; } drm_sarea_drawable_t; /** SAREA frame */ typedef struct drm_sarea_frame { - unsigned int x; - unsigned int y; - unsigned int width; - unsigned int height; - unsigned int fullscreen; + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; + unsigned int fullscreen; } drm_sarea_frame_t; /** SAREA */ typedef struct drm_sarea { /** first thing is always the DRM locking structure */ - drm_hw_lock_t lock; + drm_hw_lock_t lock; /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ - drm_hw_lock_t drawable_lock; - drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ - drm_sarea_frame_t frame; /**< frame */ - drm_context_t dummy_context; + drm_hw_lock_t drawable_lock; + drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ + drm_sarea_frame_t frame; /**< frame */ + drm_context_t dummy_context; } drm_sarea_t; -#endif /* _DRM_SAREA_H_ */ +#endif /* _DRM_SAREA_H_ */ diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 1b91c60a..9007bd2c 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -1,10 +1,10 @@ /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- */ /************************************************************************** - * + * * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. - * + * **************************************************************************/ #include "drmP.h" @@ -83,7 +83,7 @@ int i915_dma_cleanup(drm_device_t * dev) * is freed, it's too late. */ if (dev->irq) - drm_irq_uninstall (dev); + drm_irq_uninstall(dev); if (dev->dev_private) { drm_i915_private_t *dev_priv = @@ -108,8 +108,8 @@ int i915_dma_cleanup(drm_device_t * dev) I915_WRITE(0x02080, 0x1ffff000); } - drm_free (dev->dev_private, sizeof(drm_i915_private_t), - DRM_MEM_DRIVER); + drm_free(dev->dev_private, sizeof(drm_i915_private_t), + DRM_MEM_DRIVER); dev->dev_private = NULL; } @@ -254,8 +254,8 @@ int i915_dma_init(DRM_IOCTL_ARGS) switch (init.func) { case I915_INIT_DMA: - dev_priv = drm_alloc (sizeof(drm_i915_private_t), - DRM_MEM_DRIVER); + dev_priv = drm_alloc(sizeof(drm_i915_private_t), + DRM_MEM_DRIVER); if (dev_priv == NULL) return DRM_ERR(ENOMEM); retcode = i915_initialize(dev, dev_priv, &init); @@ -732,7 +732,7 @@ int i915_setparam(DRM_IOCTL_ARGS) return 0; } -void i915_driver_pretakedown(drm_device_t *dev) +void i915_driver_pretakedown(drm_device_t * dev) { if (dev->dev_private) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -741,7 +741,7 @@ void i915_driver_pretakedown(drm_device_t *dev) i915_dma_cleanup(dev); } -void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp) +void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp) { if (dev->dev_private) { drm_i915_private_t *dev_priv = dev->dev_private; diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index f6ca92a5..19f8c0ad 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -1,10 +1,10 @@ /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- */ /************************************************************************** - * + * * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. - * + * **************************************************************************/ #ifndef _I915_DRV_H_ @@ -88,8 +88,8 @@ extern int i915_getparam(DRM_IOCTL_ARGS); extern int i915_setparam(DRM_IOCTL_ARGS); extern int i915_cmdbuffer(DRM_IOCTL_ARGS); extern void i915_kernel_lost_context(drm_device_t * dev); -extern void i915_driver_pretakedown(drm_device_t *dev); -extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp); +extern void i915_driver_pretakedown(drm_device_t * dev); +extern void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp); /* i915_irq.c */ extern int i915_irq_emit(DRM_IOCTL_ARGS); @@ -98,9 +98,9 @@ extern int i915_wait_irq(drm_device_t * dev, int irq_nr); extern int i915_emit_irq(drm_device_t * dev); extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); -extern void i915_driver_irq_preinstall(drm_device_t *dev); -extern void i915_driver_irq_postinstall(drm_device_t *dev); -extern void i915_driver_irq_uninstall(drm_device_t *dev); +extern void i915_driver_irq_preinstall(drm_device_t * dev); +extern void i915_driver_irq_postinstall(drm_device_t * dev); +extern void i915_driver_irq_uninstall(drm_device_t * dev); /* i915_mem.c */ extern int i915_mem_alloc(DRM_IOCTL_ARGS); diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c index 581d3f22..04c627b9 100644 --- a/shared-core/i915_irq.c +++ b/shared-core/i915_irq.c @@ -1,10 +1,10 @@ /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- */ /************************************************************************** - * + * * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. - * + * **************************************************************************/ #include "drmP.h" diff --git a/shared-core/i915_mem.c b/shared-core/i915_mem.c index d54a3005..0023d19c 100644 --- a/shared-core/i915_mem.c +++ b/shared-core/i915_mem.c @@ -1,10 +1,10 @@ /* i915_mem.c -- Simple agp/fb memory manager for i915 -*- linux-c -*- */ /************************************************************************** - * + * * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. - * + * **************************************************************************/ #include "drmP.h" @@ -66,7 +66,7 @@ static void mark_block(drm_device_t * dev, struct mem_block *p, int in_use) } /* Very simple allocator for agp memory, working on a static range - * already mapped into each client's address space. + * already mapped into each client's address space. */ static struct mem_block *split_block(struct mem_block *p, int start, int size, @@ -74,7 +74,8 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, { /* Maybe cut off the start of an existing block */ if (start > p->start) { - struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); + struct mem_block *newblock = + drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); if (!newblock) goto out; newblock->start = start; @@ -90,7 +91,8 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, /* Maybe cut off the end of an existing block */ if (size < p->size) { - struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); + struct mem_block *newblock = + drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); if (!newblock) goto out; newblock->start = start + size; diff --git a/shared-core/mach64_dma.c b/shared-core/mach64_dma.c index c463b6cf..f06873e7 100644 --- a/shared-core/mach64_dma.c +++ b/shared-core/mach64_dma.c @@ -36,70 +36,71 @@ #include "mach64_drm.h" #include "mach64_drv.h" - /* ================================================================ * Engine, FIFO control */ -int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv, int entries ) +int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv, int entries) { int slots = 0, i; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - slots = (MACH64_READ( MACH64_FIFO_STAT ) & - MACH64_FIFO_SLOT_MASK); - if ( slots <= (0x8000 >> entries) ) return 0; - DRM_UDELAY( 1 ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + slots = (MACH64_READ(MACH64_FIFO_STAT) & MACH64_FIFO_SLOT_MASK); + if (slots <= (0x8000 >> entries)) + return 0; + DRM_UDELAY(1); } - DRM_INFO( "%s failed! slots=%d entries=%d\n", __FUNCTION__, slots, entries ); + DRM_INFO("%s failed! slots=%d entries=%d\n", __FUNCTION__, slots, + entries); return DRM_ERR(EBUSY); } -int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv ) +int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv) { int i, ret; - ret = mach64_do_wait_for_fifo( dev_priv, 16 ); - if ( ret < 0 ) return ret; + ret = mach64_do_wait_for_fifo(dev_priv, 16); + if (ret < 0) + return ret; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(MACH64_READ( MACH64_GUI_STAT ) & MACH64_GUI_ACTIVE) ) { + for (i = 0; i < dev_priv->usec_timeout; i++) { + if (!(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE)) { return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } - DRM_INFO( "%s failed! GUI_STAT=0x%08x\n", __FUNCTION__, - MACH64_READ( MACH64_GUI_STAT ) ); - mach64_dump_ring_info( dev_priv ); + DRM_INFO("%s failed! GUI_STAT=0x%08x\n", __FUNCTION__, + MACH64_READ(MACH64_GUI_STAT)); + mach64_dump_ring_info(dev_priv); return DRM_ERR(EBUSY); } -int mach64_wait_ring( drm_mach64_private_t *dev_priv, int n ) +int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; int i; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - mach64_update_ring_snapshot( dev_priv ); - if ( ring->space >= n ) { + for (i = 0; i < dev_priv->usec_timeout; i++) { + mach64_update_ring_snapshot(dev_priv); + if (ring->space >= n) { if (i > 0) { - DRM_DEBUG( "%s: %d usecs\n", __FUNCTION__, i ); + DRM_DEBUG("%s: %d usecs\n", __FUNCTION__, i); } return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } /* FIXME: This is being ignored... */ - DRM_ERROR( "failed!\n" ); - mach64_dump_ring_info( dev_priv ); + DRM_ERROR("failed!\n"); + mach64_dump_ring_info(dev_priv); return DRM_ERR(EBUSY); } /* Wait until all DMA requests have been processed... */ -static int mach64_ring_idle( drm_mach64_private_t *dev_priv ) +static int mach64_ring_idle(drm_mach64_private_t * dev_priv) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; u32 head; @@ -107,108 +108,106 @@ static int mach64_ring_idle( drm_mach64_private_t *dev_priv ) head = ring->head; i = 0; - while ( i < dev_priv->usec_timeout ) { - mach64_update_ring_snapshot( dev_priv ); - if ( ring->head == ring->tail && - !(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE) ) { + while (i < dev_priv->usec_timeout) { + mach64_update_ring_snapshot(dev_priv); + if (ring->head == ring->tail && + !(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE)) { if (i > 0) { - DRM_DEBUG( "%s: %d usecs\n", __FUNCTION__, i ); + DRM_DEBUG("%s: %d usecs\n", __FUNCTION__, i); } return 0; - } - if ( ring->head == head ) { + } + if (ring->head == head) { ++i; } else { head = ring->head; i = 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } - DRM_INFO( "%s failed! GUI_STAT=0x%08x\n", __FUNCTION__, - MACH64_READ( MACH64_GUI_STAT ) ); - mach64_dump_ring_info( dev_priv ); + DRM_INFO("%s failed! GUI_STAT=0x%08x\n", __FUNCTION__, + MACH64_READ(MACH64_GUI_STAT)); + mach64_dump_ring_info(dev_priv); return DRM_ERR(EBUSY); } -static void mach64_ring_reset( drm_mach64_private_t *dev_priv ) +static void mach64_ring_reset(drm_mach64_private_t * dev_priv) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - mach64_do_release_used_buffers( dev_priv ); + mach64_do_release_used_buffers(dev_priv); ring->head_addr = ring->start_addr; ring->head = ring->tail = 0; ring->space = ring->size; - - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); + + MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, + ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB); dev_priv->ring_running = 0; } -int mach64_do_dma_flush( drm_mach64_private_t *dev_priv ) +int mach64_do_dma_flush(drm_mach64_private_t * dev_priv) { - /* FIXME: It's not necessary to wait for idle when flushing + /* FIXME: It's not necessary to wait for idle when flushing * we just need to ensure the ring will be completely processed * in finite time without another ioctl */ - return mach64_ring_idle( dev_priv ); + return mach64_ring_idle(dev_priv); } -int mach64_do_dma_idle( drm_mach64_private_t *dev_priv ) +int mach64_do_dma_idle(drm_mach64_private_t * dev_priv) { int ret; /* wait for completion */ - if ( (ret = mach64_ring_idle( dev_priv )) < 0 ) { - DRM_ERROR( "%s failed BM_GUI_TABLE=0x%08x tail: %u\n", __FUNCTION__, - MACH64_READ(MACH64_BM_GUI_TABLE), dev_priv->ring.tail ); + if ((ret = mach64_ring_idle(dev_priv)) < 0) { + DRM_ERROR("%s failed BM_GUI_TABLE=0x%08x tail: %u\n", + __FUNCTION__, MACH64_READ(MACH64_BM_GUI_TABLE), + dev_priv->ring.tail); return ret; } - mach64_ring_stop( dev_priv ); + mach64_ring_stop(dev_priv); /* clean up after pass */ - mach64_do_release_used_buffers( dev_priv ); + mach64_do_release_used_buffers(dev_priv); return 0; } /* Reset the engine. This will stop the DMA if it is running. */ -int mach64_do_engine_reset( drm_mach64_private_t *dev_priv ) +int mach64_do_engine_reset(drm_mach64_private_t * dev_priv) { u32 tmp; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); /* Kill off any outstanding DMA transfers. */ - tmp = MACH64_READ( MACH64_BUS_CNTL ); - MACH64_WRITE( MACH64_BUS_CNTL, - tmp | MACH64_BUS_MASTER_DIS ); - + tmp = MACH64_READ(MACH64_BUS_CNTL); + MACH64_WRITE(MACH64_BUS_CNTL, tmp | MACH64_BUS_MASTER_DIS); + /* Reset the GUI engine (high to low transition). */ - tmp = MACH64_READ( MACH64_GEN_TEST_CNTL ); - MACH64_WRITE( MACH64_GEN_TEST_CNTL, - tmp & ~MACH64_GUI_ENGINE_ENABLE ); + tmp = MACH64_READ(MACH64_GEN_TEST_CNTL); + MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp & ~MACH64_GUI_ENGINE_ENABLE); /* Enable the GUI engine */ - tmp = MACH64_READ( MACH64_GEN_TEST_CNTL ); - MACH64_WRITE( MACH64_GEN_TEST_CNTL, - tmp | MACH64_GUI_ENGINE_ENABLE ); + tmp = MACH64_READ(MACH64_GEN_TEST_CNTL); + MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp | MACH64_GUI_ENGINE_ENABLE); /* ensure engine is not locked up by clearing any FIFO or HOST errors - */ - tmp = MACH64_READ( MACH64_BUS_CNTL ); - MACH64_WRITE( MACH64_BUS_CNTL, tmp | 0x00a00000 ); + */ + tmp = MACH64_READ(MACH64_BUS_CNTL); + MACH64_WRITE(MACH64_BUS_CNTL, tmp | 0x00a00000); /* Once GUI engine is restored, disable bus mastering */ - MACH64_WRITE( MACH64_SRC_CNTL, 0 ); + MACH64_WRITE(MACH64_SRC_CNTL, 0); /* Reset descriptor ring */ - mach64_ring_reset( dev_priv ); - + mach64_ring_reset(dev_priv); + return 0; } @@ -216,220 +215,282 @@ int mach64_do_engine_reset( drm_mach64_private_t *dev_priv ) * Debugging output */ -void mach64_dump_engine_info( drm_mach64_private_t *dev_priv ) +void mach64_dump_engine_info(drm_mach64_private_t * dev_priv) { - DRM_INFO( "\n" ); - if ( !dev_priv->is_pci ) - { - DRM_INFO( " AGP_BASE = 0x%08x\n", MACH64_READ( MACH64_AGP_BASE ) ); - DRM_INFO( " AGP_CNTL = 0x%08x\n", MACH64_READ( MACH64_AGP_CNTL ) ); + DRM_INFO("\n"); + if (!dev_priv->is_pci) { + DRM_INFO(" AGP_BASE = 0x%08x\n", + MACH64_READ(MACH64_AGP_BASE)); + DRM_INFO(" AGP_CNTL = 0x%08x\n", + MACH64_READ(MACH64_AGP_CNTL)); } - DRM_INFO( " ALPHA_TST_CNTL = 0x%08x\n", MACH64_READ( MACH64_ALPHA_TST_CNTL ) ); - DRM_INFO( "\n" ); - DRM_INFO( " BM_COMMAND = 0x%08x\n", MACH64_READ( MACH64_BM_COMMAND ) ); - DRM_INFO( "BM_FRAME_BUF_OFFSET = 0x%08x\n", MACH64_READ( MACH64_BM_FRAME_BUF_OFFSET ) ); - DRM_INFO( " BM_GUI_TABLE = 0x%08x\n", MACH64_READ( MACH64_BM_GUI_TABLE ) ); - DRM_INFO( " BM_STATUS = 0x%08x\n", MACH64_READ( MACH64_BM_STATUS ) ); - DRM_INFO( " BM_SYSTEM_MEM_ADDR = 0x%08x\n", MACH64_READ( MACH64_BM_SYSTEM_MEM_ADDR ) ); - DRM_INFO( " BM_SYSTEM_TABLE = 0x%08x\n", MACH64_READ( MACH64_BM_SYSTEM_TABLE ) ); - DRM_INFO( " BUS_CNTL = 0x%08x\n", MACH64_READ( MACH64_BUS_CNTL ) ); - DRM_INFO( "\n" ); + DRM_INFO(" ALPHA_TST_CNTL = 0x%08x\n", + MACH64_READ(MACH64_ALPHA_TST_CNTL)); + DRM_INFO("\n"); + DRM_INFO(" BM_COMMAND = 0x%08x\n", + MACH64_READ(MACH64_BM_COMMAND)); + DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n", + MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET)); + DRM_INFO(" BM_GUI_TABLE = 0x%08x\n", + MACH64_READ(MACH64_BM_GUI_TABLE)); + DRM_INFO(" BM_STATUS = 0x%08x\n", + MACH64_READ(MACH64_BM_STATUS)); + DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n", + MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR)); + DRM_INFO(" BM_SYSTEM_TABLE = 0x%08x\n", + MACH64_READ(MACH64_BM_SYSTEM_TABLE)); + DRM_INFO(" BUS_CNTL = 0x%08x\n", + MACH64_READ(MACH64_BUS_CNTL)); + DRM_INFO("\n"); /* DRM_INFO( " CLOCK_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLOCK_CNTL ) ); */ - DRM_INFO( " CLR_CMP_CLR = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_CLR ) ); - DRM_INFO( " CLR_CMP_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_CNTL ) ); + DRM_INFO(" CLR_CMP_CLR = 0x%08x\n", + MACH64_READ(MACH64_CLR_CMP_CLR)); + DRM_INFO(" CLR_CMP_CNTL = 0x%08x\n", + MACH64_READ(MACH64_CLR_CMP_CNTL)); /* DRM_INFO( " CLR_CMP_MSK = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_MSK ) ); */ - DRM_INFO( " CONFIG_CHIP_ID = 0x%08x\n", MACH64_READ( MACH64_CONFIG_CHIP_ID ) ); - DRM_INFO( " CONFIG_CNTL = 0x%08x\n", MACH64_READ( MACH64_CONFIG_CNTL ) ); - DRM_INFO( " CONFIG_STAT0 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT0 ) ); - DRM_INFO( " CONFIG_STAT1 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT1 ) ); - DRM_INFO( " CONFIG_STAT2 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT2 ) ); - DRM_INFO( " CRC_SIG = 0x%08x\n", MACH64_READ( MACH64_CRC_SIG ) ); - DRM_INFO( " CUSTOM_MACRO_CNTL = 0x%08x\n", MACH64_READ( MACH64_CUSTOM_MACRO_CNTL ) ); - DRM_INFO( "\n" ); + DRM_INFO(" CONFIG_CHIP_ID = 0x%08x\n", + MACH64_READ(MACH64_CONFIG_CHIP_ID)); + DRM_INFO(" CONFIG_CNTL = 0x%08x\n", + MACH64_READ(MACH64_CONFIG_CNTL)); + DRM_INFO(" CONFIG_STAT0 = 0x%08x\n", + MACH64_READ(MACH64_CONFIG_STAT0)); + DRM_INFO(" CONFIG_STAT1 = 0x%08x\n", + MACH64_READ(MACH64_CONFIG_STAT1)); + DRM_INFO(" CONFIG_STAT2 = 0x%08x\n", + MACH64_READ(MACH64_CONFIG_STAT2)); + DRM_INFO(" CRC_SIG = 0x%08x\n", MACH64_READ(MACH64_CRC_SIG)); + DRM_INFO(" CUSTOM_MACRO_CNTL = 0x%08x\n", + MACH64_READ(MACH64_CUSTOM_MACRO_CNTL)); + DRM_INFO("\n"); /* DRM_INFO( " DAC_CNTL = 0x%08x\n", MACH64_READ( MACH64_DAC_CNTL ) ); */ /* DRM_INFO( " DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_DAC_REGS ) ); */ - DRM_INFO( " DP_BKGD_CLR = 0x%08x\n", MACH64_READ( MACH64_DP_BKGD_CLR ) ); - DRM_INFO( " DP_FRGD_CLR = 0x%08x\n", MACH64_READ( MACH64_DP_FRGD_CLR ) ); - DRM_INFO( " DP_MIX = 0x%08x\n", MACH64_READ( MACH64_DP_MIX ) ); - DRM_INFO( " DP_PIX_WIDTH = 0x%08x\n", MACH64_READ( MACH64_DP_PIX_WIDTH ) ); - DRM_INFO( " DP_SRC = 0x%08x\n", MACH64_READ( MACH64_DP_SRC ) ); - DRM_INFO( " DP_WRITE_MASK = 0x%08x\n", MACH64_READ( MACH64_DP_WRITE_MASK ) ); - DRM_INFO( " DSP_CONFIG = 0x%08x\n", MACH64_READ( MACH64_DSP_CONFIG ) ); - DRM_INFO( " DSP_ON_OFF = 0x%08x\n", MACH64_READ( MACH64_DSP_ON_OFF ) ); - DRM_INFO( " DST_CNTL = 0x%08x\n", MACH64_READ( MACH64_DST_CNTL ) ); - DRM_INFO( " DST_OFF_PITCH = 0x%08x\n", MACH64_READ( MACH64_DST_OFF_PITCH ) ); - DRM_INFO( "\n" ); + DRM_INFO(" DP_BKGD_CLR = 0x%08x\n", + MACH64_READ(MACH64_DP_BKGD_CLR)); + DRM_INFO(" DP_FRGD_CLR = 0x%08x\n", + MACH64_READ(MACH64_DP_FRGD_CLR)); + DRM_INFO(" DP_MIX = 0x%08x\n", MACH64_READ(MACH64_DP_MIX)); + DRM_INFO(" DP_PIX_WIDTH = 0x%08x\n", + MACH64_READ(MACH64_DP_PIX_WIDTH)); + DRM_INFO(" DP_SRC = 0x%08x\n", MACH64_READ(MACH64_DP_SRC)); + DRM_INFO(" DP_WRITE_MASK = 0x%08x\n", + MACH64_READ(MACH64_DP_WRITE_MASK)); + DRM_INFO(" DSP_CONFIG = 0x%08x\n", + MACH64_READ(MACH64_DSP_CONFIG)); + DRM_INFO(" DSP_ON_OFF = 0x%08x\n", + MACH64_READ(MACH64_DSP_ON_OFF)); + DRM_INFO(" DST_CNTL = 0x%08x\n", + MACH64_READ(MACH64_DST_CNTL)); + DRM_INFO(" DST_OFF_PITCH = 0x%08x\n", + MACH64_READ(MACH64_DST_OFF_PITCH)); + DRM_INFO("\n"); /* DRM_INFO( " EXT_DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_EXT_DAC_REGS ) ); */ - DRM_INFO( " EXT_MEM_CNTL = 0x%08x\n", MACH64_READ( MACH64_EXT_MEM_CNTL ) ); - DRM_INFO( "\n" ); - DRM_INFO( " FIFO_STAT = 0x%08x\n", MACH64_READ( MACH64_FIFO_STAT ) ); - DRM_INFO( "\n" ); - DRM_INFO( " GEN_TEST_CNTL = 0x%08x\n", MACH64_READ( MACH64_GEN_TEST_CNTL ) ); + DRM_INFO(" EXT_MEM_CNTL = 0x%08x\n", + MACH64_READ(MACH64_EXT_MEM_CNTL)); + DRM_INFO("\n"); + DRM_INFO(" FIFO_STAT = 0x%08x\n", + MACH64_READ(MACH64_FIFO_STAT)); + DRM_INFO("\n"); + DRM_INFO(" GEN_TEST_CNTL = 0x%08x\n", + MACH64_READ(MACH64_GEN_TEST_CNTL)); /* DRM_INFO( " GP_IO = 0x%08x\n", MACH64_READ( MACH64_GP_IO ) ); */ - DRM_INFO( " GUI_CMDFIFO_DATA = 0x%08x\n", MACH64_READ( MACH64_GUI_CMDFIFO_DATA ) ); - DRM_INFO( " GUI_CMDFIFO_DEBUG = 0x%08x\n", MACH64_READ( MACH64_GUI_CMDFIFO_DEBUG ) ); - DRM_INFO( " GUI_CNTL = 0x%08x\n", MACH64_READ( MACH64_GUI_CNTL ) ); - DRM_INFO( " GUI_STAT = 0x%08x\n", MACH64_READ( MACH64_GUI_STAT ) ); - DRM_INFO( " GUI_TRAJ_CNTL = 0x%08x\n", MACH64_READ( MACH64_GUI_TRAJ_CNTL ) ); - DRM_INFO( "\n" ); - DRM_INFO( " HOST_CNTL = 0x%08x\n", MACH64_READ( MACH64_HOST_CNTL ) ); - DRM_INFO( " HW_DEBUG = 0x%08x\n", MACH64_READ( MACH64_HW_DEBUG ) ); - DRM_INFO( "\n" ); - DRM_INFO( " MEM_ADDR_CONFIG = 0x%08x\n", MACH64_READ( MACH64_MEM_ADDR_CONFIG ) ); - DRM_INFO( " MEM_BUF_CNTL = 0x%08x\n", MACH64_READ( MACH64_MEM_BUF_CNTL ) ); - DRM_INFO( "\n" ); - DRM_INFO( " PAT_REG0 = 0x%08x\n", MACH64_READ( MACH64_PAT_REG0 ) ); - DRM_INFO( " PAT_REG1 = 0x%08x\n", MACH64_READ( MACH64_PAT_REG1 ) ); - DRM_INFO( "\n" ); - DRM_INFO( " SC_LEFT = 0x%08x\n", MACH64_READ( MACH64_SC_LEFT ) ); - DRM_INFO( " SC_RIGHT = 0x%08x\n", MACH64_READ( MACH64_SC_RIGHT ) ); - DRM_INFO( " SC_TOP = 0x%08x\n", MACH64_READ( MACH64_SC_TOP ) ); - DRM_INFO( " SC_BOTTOM = 0x%08x\n", MACH64_READ( MACH64_SC_BOTTOM ) ); - DRM_INFO( "\n" ); - DRM_INFO( " SCALE_3D_CNTL = 0x%08x\n", MACH64_READ( MACH64_SCALE_3D_CNTL ) ); - DRM_INFO( " SCRATCH_REG0 = 0x%08x\n", MACH64_READ( MACH64_SCRATCH_REG0 ) ); - DRM_INFO( " SCRATCH_REG1 = 0x%08x\n", MACH64_READ( MACH64_SCRATCH_REG1 ) ); - DRM_INFO( " SETUP_CNTL = 0x%08x\n", MACH64_READ( MACH64_SETUP_CNTL ) ); - DRM_INFO( " SRC_CNTL = 0x%08x\n", MACH64_READ( MACH64_SRC_CNTL ) ); - DRM_INFO( "\n" ); - DRM_INFO( " TEX_CNTL = 0x%08x\n", MACH64_READ( MACH64_TEX_CNTL ) ); - DRM_INFO( " TEX_SIZE_PITCH = 0x%08x\n", MACH64_READ( MACH64_TEX_SIZE_PITCH ) ); - DRM_INFO( " TIMER_CONFIG = 0x%08x\n", MACH64_READ( MACH64_TIMER_CONFIG ) ); - DRM_INFO( "\n" ); - DRM_INFO( " Z_CNTL = 0x%08x\n", MACH64_READ( MACH64_Z_CNTL ) ); - DRM_INFO( " Z_OFF_PITCH = 0x%08x\n", MACH64_READ( MACH64_Z_OFF_PITCH ) ); - DRM_INFO( "\n" ); + DRM_INFO(" GUI_CMDFIFO_DATA = 0x%08x\n", + MACH64_READ(MACH64_GUI_CMDFIFO_DATA)); + DRM_INFO(" GUI_CMDFIFO_DEBUG = 0x%08x\n", + MACH64_READ(MACH64_GUI_CMDFIFO_DEBUG)); + DRM_INFO(" GUI_CNTL = 0x%08x\n", + MACH64_READ(MACH64_GUI_CNTL)); + DRM_INFO(" GUI_STAT = 0x%08x\n", + MACH64_READ(MACH64_GUI_STAT)); + DRM_INFO(" GUI_TRAJ_CNTL = 0x%08x\n", + MACH64_READ(MACH64_GUI_TRAJ_CNTL)); + DRM_INFO("\n"); + DRM_INFO(" HOST_CNTL = 0x%08x\n", + MACH64_READ(MACH64_HOST_CNTL)); + DRM_INFO(" HW_DEBUG = 0x%08x\n", + MACH64_READ(MACH64_HW_DEBUG)); + DRM_INFO("\n"); + DRM_INFO(" MEM_ADDR_CONFIG = 0x%08x\n", + MACH64_READ(MACH64_MEM_ADDR_CONFIG)); + DRM_INFO(" MEM_BUF_CNTL = 0x%08x\n", + MACH64_READ(MACH64_MEM_BUF_CNTL)); + DRM_INFO("\n"); + DRM_INFO(" PAT_REG0 = 0x%08x\n", + MACH64_READ(MACH64_PAT_REG0)); + DRM_INFO(" PAT_REG1 = 0x%08x\n", + MACH64_READ(MACH64_PAT_REG1)); + DRM_INFO("\n"); + DRM_INFO(" SC_LEFT = 0x%08x\n", MACH64_READ(MACH64_SC_LEFT)); + DRM_INFO(" SC_RIGHT = 0x%08x\n", + MACH64_READ(MACH64_SC_RIGHT)); + DRM_INFO(" SC_TOP = 0x%08x\n", MACH64_READ(MACH64_SC_TOP)); + DRM_INFO(" SC_BOTTOM = 0x%08x\n", + MACH64_READ(MACH64_SC_BOTTOM)); + DRM_INFO("\n"); + DRM_INFO(" SCALE_3D_CNTL = 0x%08x\n", + MACH64_READ(MACH64_SCALE_3D_CNTL)); + DRM_INFO(" SCRATCH_REG0 = 0x%08x\n", + MACH64_READ(MACH64_SCRATCH_REG0)); + DRM_INFO(" SCRATCH_REG1 = 0x%08x\n", + MACH64_READ(MACH64_SCRATCH_REG1)); + DRM_INFO(" SETUP_CNTL = 0x%08x\n", + MACH64_READ(MACH64_SETUP_CNTL)); + DRM_INFO(" SRC_CNTL = 0x%08x\n", + MACH64_READ(MACH64_SRC_CNTL)); + DRM_INFO("\n"); + DRM_INFO(" TEX_CNTL = 0x%08x\n", + MACH64_READ(MACH64_TEX_CNTL)); + DRM_INFO(" TEX_SIZE_PITCH = 0x%08x\n", + MACH64_READ(MACH64_TEX_SIZE_PITCH)); + DRM_INFO(" TIMER_CONFIG = 0x%08x\n", + MACH64_READ(MACH64_TIMER_CONFIG)); + DRM_INFO("\n"); + DRM_INFO(" Z_CNTL = 0x%08x\n", MACH64_READ(MACH64_Z_CNTL)); + DRM_INFO(" Z_OFF_PITCH = 0x%08x\n", + MACH64_READ(MACH64_Z_OFF_PITCH)); + DRM_INFO("\n"); } #define MACH64_DUMP_CONTEXT 3 -static void mach64_dump_buf_info( drm_mach64_private_t *dev_priv, drm_buf_t *buf) +static void mach64_dump_buf_info(drm_mach64_private_t * dev_priv, + drm_buf_t * buf) { - u32 addr = GETBUFADDR( buf ); + u32 addr = GETBUFADDR(buf); u32 used = buf->used >> 2; - u32 sys_addr = MACH64_READ( MACH64_BM_SYSTEM_MEM_ADDR ); - u32 *p = GETBUFPTR( buf ); + u32 sys_addr = MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR); + u32 *p = GETBUFPTR(buf); int skipped = 0; - DRM_INFO( "buffer contents:\n" ); - - while ( used ) { + DRM_INFO("buffer contents:\n"); + + while (used) { u32 reg, count; reg = le32_to_cpu(*p++); - if( addr <= GETBUFADDR( buf ) + MACH64_DUMP_CONTEXT * 4 || + if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 || (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 && - addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) || - addr >= GETBUFADDR( buf ) + buf->used - MACH64_DUMP_CONTEXT * 4) { + addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) || + addr >= + GETBUFADDR(buf) + buf->used - MACH64_DUMP_CONTEXT * 4) { DRM_INFO("%08x: 0x%08x\n", addr, reg); } addr += 4; used--; - + count = (reg >> 16) + 1; reg = reg & 0xffff; - reg = MMSELECT( reg ); - while ( count && used ) { - if( addr <= GETBUFADDR( buf ) + MACH64_DUMP_CONTEXT * 4 || + reg = MMSELECT(reg); + while (count && used) { + if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 || (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 && - addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) || - addr >= GETBUFADDR( buf ) + buf->used - MACH64_DUMP_CONTEXT * 4) { - DRM_INFO("%08x: 0x%04x = 0x%08x\n", addr, reg, le32_to_cpu(*p)); + addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) || + addr >= + GETBUFADDR(buf) + buf->used - + MACH64_DUMP_CONTEXT * 4) { + DRM_INFO("%08x: 0x%04x = 0x%08x\n", addr, + reg, le32_to_cpu(*p)); skipped = 0; } else { - if( !skipped ) { - DRM_INFO( " ...\n" ); + if (!skipped) { + DRM_INFO(" ...\n"); skipped = 1; } } p++; addr += 4; used--; - + reg += 4; count--; } } - - DRM_INFO( "\n" ); + + DRM_INFO("\n"); } -void mach64_dump_ring_info( drm_mach64_private_t *dev_priv ) +void mach64_dump_ring_info(drm_mach64_private_t * dev_priv) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; int i, skipped; - - DRM_INFO( "\n" ); - + + DRM_INFO("\n"); + DRM_INFO("ring contents:\n"); - DRM_INFO(" head_addr: 0x%08x head: %u tail: %u\n\n", - ring->head_addr, ring->head, ring->tail ); - + DRM_INFO(" head_addr: 0x%08x head: %u tail: %u\n\n", + ring->head_addr, ring->head, ring->tail); + skipped = 0; - for ( i = 0; i < ring->size / sizeof(u32); i += 4) { - if( i <= MACH64_DUMP_CONTEXT * 4 || + for (i = 0; i < ring->size / sizeof(u32); i += 4) { + if (i <= MACH64_DUMP_CONTEXT * 4 || i >= ring->size / sizeof(u32) - MACH64_DUMP_CONTEXT * 4 || (i >= ring->tail - MACH64_DUMP_CONTEXT * 4 && - i <= ring->tail + MACH64_DUMP_CONTEXT * 4) || + i <= ring->tail + MACH64_DUMP_CONTEXT * 4) || (i >= ring->head - MACH64_DUMP_CONTEXT * 4 && - i <= ring->head + MACH64_DUMP_CONTEXT * 4)) { - DRM_INFO( " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x%s%s\n", - ring->start_addr + i * sizeof(u32), - le32_to_cpu(((u32*) ring->start)[i + 0]), - le32_to_cpu(((u32*) ring->start)[i + 1]), - le32_to_cpu(((u32*) ring->start)[i + 2]), - le32_to_cpu(((u32*) ring->start)[i + 3]), - i == ring->head ? " (head)" : "", - i == ring->tail ? " (tail)" : "" - ); + i <= ring->head + MACH64_DUMP_CONTEXT * 4)) { + DRM_INFO(" 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x%s%s\n", + ring->start_addr + i * sizeof(u32), + le32_to_cpu(((u32 *) ring->start)[i + 0]), + le32_to_cpu(((u32 *) ring->start)[i + 1]), + le32_to_cpu(((u32 *) ring->start)[i + 2]), + le32_to_cpu(((u32 *) ring->start)[i + 3]), + i == ring->head ? " (head)" : "", + i == ring->tail ? " (tail)" : ""); skipped = 0; } else { - if( !skipped ) { - DRM_INFO( " ...\n" ); + if (!skipped) { + DRM_INFO(" ...\n"); skipped = 1; } } } - DRM_INFO( "\n" ); - - if( ring->head >= 0 && ring->head < ring->size / sizeof(u32) ) { + DRM_INFO("\n"); + + if (ring->head >= 0 && ring->head < ring->size / sizeof(u32)) { struct list_head *ptr; - u32 addr = le32_to_cpu(((u32 *)ring->start)[ring->head + 1]); + u32 addr = le32_to_cpu(((u32 *) ring->start)[ring->head + 1]); list_for_each(ptr, &dev_priv->pending) { - drm_mach64_freelist_t *entry = - list_entry(ptr, drm_mach64_freelist_t, list); + drm_mach64_freelist_t *entry = + list_entry(ptr, drm_mach64_freelist_t, list); drm_buf_t *buf = entry->buf; - u32 buf_addr = GETBUFADDR( buf ); - - if ( buf_addr <= addr && addr < buf_addr + buf->used ) { - mach64_dump_buf_info ( dev_priv, buf ); + u32 buf_addr = GETBUFADDR(buf); + + if (buf_addr <= addr && addr < buf_addr + buf->used) { + mach64_dump_buf_info(dev_priv, buf); } } } - DRM_INFO( "\n" ); - DRM_INFO( " BM_GUI_TABLE = 0x%08x\n", MACH64_READ( MACH64_BM_GUI_TABLE ) ); - DRM_INFO( "\n" ); - DRM_INFO( "BM_FRAME_BUF_OFFSET = 0x%08x\n", MACH64_READ( MACH64_BM_FRAME_BUF_OFFSET ) ); - DRM_INFO( " BM_SYSTEM_MEM_ADDR = 0x%08x\n", MACH64_READ( MACH64_BM_SYSTEM_MEM_ADDR ) ); - DRM_INFO( " BM_COMMAND = 0x%08x\n", MACH64_READ( MACH64_BM_COMMAND ) ); - DRM_INFO( "\n" ); - DRM_INFO( " BM_STATUS = 0x%08x\n", MACH64_READ( MACH64_BM_STATUS ) ); - DRM_INFO( " BUS_CNTL = 0x%08x\n", MACH64_READ( MACH64_BUS_CNTL ) ); - DRM_INFO( " FIFO_STAT = 0x%08x\n", MACH64_READ( MACH64_FIFO_STAT ) ); - DRM_INFO( " GUI_STAT = 0x%08x\n", MACH64_READ( MACH64_GUI_STAT ) ); - DRM_INFO( " SRC_CNTL = 0x%08x\n", MACH64_READ( MACH64_SRC_CNTL ) ); + DRM_INFO("\n"); + DRM_INFO(" BM_GUI_TABLE = 0x%08x\n", + MACH64_READ(MACH64_BM_GUI_TABLE)); + DRM_INFO("\n"); + DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n", + MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET)); + DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n", + MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR)); + DRM_INFO(" BM_COMMAND = 0x%08x\n", + MACH64_READ(MACH64_BM_COMMAND)); + DRM_INFO("\n"); + DRM_INFO(" BM_STATUS = 0x%08x\n", + MACH64_READ(MACH64_BM_STATUS)); + DRM_INFO(" BUS_CNTL = 0x%08x\n", + MACH64_READ(MACH64_BUS_CNTL)); + DRM_INFO(" FIFO_STAT = 0x%08x\n", + MACH64_READ(MACH64_FIFO_STAT)); + DRM_INFO(" GUI_STAT = 0x%08x\n", + MACH64_READ(MACH64_GUI_STAT)); + DRM_INFO(" SRC_CNTL = 0x%08x\n", + MACH64_READ(MACH64_SRC_CNTL)); } - /* ================================================================ * DMA test and initialization */ -static int mach64_bm_dma_test( drm_device_t *dev ) +static int mach64_bm_dma_test(drm_device_t * dev) { drm_mach64_private_t *dev_priv = dev->dev_private; dma_addr_t data_handle; @@ -440,15 +501,16 @@ static int mach64_bm_dma_test( drm_device_t *dev ) u32 src_cntl, pat_reg0, pat_reg1; int i, count, failed; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); table = (u32 *) dev_priv->ring.start; /* FIXME: get a dma buffer from the freelist here */ - DRM_DEBUG( "Allocating data memory ...\n" ); - cpu_addr_data = drm_pci_alloc( dev, 0x1000, 0x1000, 0xfffffffful, &data_handle ); + DRM_DEBUG("Allocating data memory ...\n"); + cpu_addr_data = + drm_pci_alloc(dev, 0x1000, 0x1000, 0xfffffffful, &data_handle); if (!cpu_addr_data || !data_handle) { - DRM_INFO( "data-memory allocation failed!\n" ); + DRM_INFO("data-memory allocation failed!\n"); return DRM_ERR(ENOMEM); } else { data = (u32 *) cpu_addr_data; @@ -459,28 +521,28 @@ static int mach64_bm_dma_test( drm_device_t *dev ) * in case our test fails. This prevents the X server * from disabling it's cache for this register */ - src_cntl = MACH64_READ( MACH64_SRC_CNTL ); - pat_reg0 = MACH64_READ( MACH64_PAT_REG0 ); - pat_reg1 = MACH64_READ( MACH64_PAT_REG1 ); + src_cntl = MACH64_READ(MACH64_SRC_CNTL); + pat_reg0 = MACH64_READ(MACH64_PAT_REG0); + pat_reg1 = MACH64_READ(MACH64_PAT_REG1); - mach64_do_wait_for_fifo( dev_priv, 3 ); + mach64_do_wait_for_fifo(dev_priv, 3); - MACH64_WRITE( MACH64_SRC_CNTL, 0 ); - MACH64_WRITE( MACH64_PAT_REG0, 0x11111111 ); - MACH64_WRITE( MACH64_PAT_REG1, 0x11111111 ); + MACH64_WRITE(MACH64_SRC_CNTL, 0); + MACH64_WRITE(MACH64_PAT_REG0, 0x11111111); + MACH64_WRITE(MACH64_PAT_REG1, 0x11111111); - mach64_do_wait_for_idle( dev_priv ); + mach64_do_wait_for_idle(dev_priv); - for (i=0; i < 2; i++) { + for (i = 0; i < 2; i++) { u32 reg; - reg = MACH64_READ( (MACH64_PAT_REG0 + i*4) ); - DRM_DEBUG( "(Before DMA Transfer) reg %d = 0x%08x\n", i, reg ); - if ( reg != 0x11111111 ) { - DRM_INFO( "Error initializing test registers\n" ); - DRM_INFO( "resetting engine ...\n"); - mach64_do_engine_reset( dev_priv ); - DRM_INFO( "freeing data buffer memory.\n" ); - drm_pci_free( dev, 0x1000, cpu_addr_data, data_handle ); + reg = MACH64_READ((MACH64_PAT_REG0 + i * 4)); + DRM_DEBUG("(Before DMA Transfer) reg %d = 0x%08x\n", i, reg); + if (reg != 0x11111111) { + DRM_INFO("Error initializing test registers\n"); + DRM_INFO("resetting engine ...\n"); + mach64_do_engine_reset(dev_priv); + DRM_INFO("freeing data buffer memory.\n"); + drm_pci_free(dev, 0x1000, cpu_addr_data, data_handle); return DRM_ERR(EIO); } } @@ -493,153 +555,152 @@ static int mach64_bm_dma_test( drm_device_t *dev ) data[count++] = expected[1] = 0xaaaaaaaa; while (count < 1020) { - data[count++] = cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16)); + data[count++] = + cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16)); data[count++] = 0x22222222; data[count++] = 0xaaaaaaaa; } data[count++] = cpu_to_le32(DMAREG(MACH64_SRC_CNTL) | (0 << 16)); data[count++] = 0; - DRM_DEBUG( "Preparing table ...\n" ); - table[MACH64_DMA_FRAME_BUF_OFFSET] = cpu_to_le32(MACH64_BM_ADDR + + DRM_DEBUG("Preparing table ...\n"); + table[MACH64_DMA_FRAME_BUF_OFFSET] = cpu_to_le32(MACH64_BM_ADDR + MACH64_APERTURE_OFFSET); - table[MACH64_DMA_SYS_MEM_ADDR] = cpu_to_le32(data_addr); - table[MACH64_DMA_COMMAND] = cpu_to_le32(count * sizeof( u32 ) - | MACH64_DMA_HOLD_OFFSET - | MACH64_DMA_EOL); - table[MACH64_DMA_RESERVED] = 0; - - DRM_DEBUG( "table[0] = 0x%08x\n", table[0] ); - DRM_DEBUG( "table[1] = 0x%08x\n", table[1] ); - DRM_DEBUG( "table[2] = 0x%08x\n", table[2] ); - DRM_DEBUG( "table[3] = 0x%08x\n", table[3] ); - - for ( i = 0 ; i < 6 ; i++ ) { - DRM_DEBUG( " data[%d] = 0x%08x\n", i, data[i] ); + table[MACH64_DMA_SYS_MEM_ADDR] = cpu_to_le32(data_addr); + table[MACH64_DMA_COMMAND] = cpu_to_le32(count * sizeof(u32) + | MACH64_DMA_HOLD_OFFSET + | MACH64_DMA_EOL); + table[MACH64_DMA_RESERVED] = 0; + + DRM_DEBUG("table[0] = 0x%08x\n", table[0]); + DRM_DEBUG("table[1] = 0x%08x\n", table[1]); + DRM_DEBUG("table[2] = 0x%08x\n", table[2]); + DRM_DEBUG("table[3] = 0x%08x\n", table[3]); + + for (i = 0; i < 6; i++) { + DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]); } - DRM_DEBUG( " ...\n" ); - for ( i = count-5 ; i < count ; i++ ) { - DRM_DEBUG( " data[%d] = 0x%08x\n", i, data[i] ); + DRM_DEBUG(" ...\n"); + for (i = count - 5; i < count; i++) { + DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]); } DRM_MEMORYBARRIER(); - DRM_DEBUG( "waiting for idle...\n" ); - if ( ( i = mach64_do_wait_for_idle( dev_priv ) ) ) { - DRM_INFO( "mach64_do_wait_for_idle failed (result=%d)\n", i); - DRM_INFO( "resetting engine ...\n"); - mach64_do_engine_reset( dev_priv ); - mach64_do_wait_for_fifo( dev_priv, 3 ); - MACH64_WRITE( MACH64_SRC_CNTL, src_cntl ); - MACH64_WRITE( MACH64_PAT_REG0, pat_reg0 ); - MACH64_WRITE( MACH64_PAT_REG1, pat_reg1 ); - DRM_INFO( "freeing data buffer memory.\n" ); - drm_pci_free( dev, 0x1000, cpu_addr_data, data_handle ); + DRM_DEBUG("waiting for idle...\n"); + if ((i = mach64_do_wait_for_idle(dev_priv))) { + DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i); + DRM_INFO("resetting engine ...\n"); + mach64_do_engine_reset(dev_priv); + mach64_do_wait_for_fifo(dev_priv, 3); + MACH64_WRITE(MACH64_SRC_CNTL, src_cntl); + MACH64_WRITE(MACH64_PAT_REG0, pat_reg0); + MACH64_WRITE(MACH64_PAT_REG1, pat_reg1); + DRM_INFO("freeing data buffer memory.\n"); + drm_pci_free(dev, 0x1000, cpu_addr_data, data_handle); return i; } - DRM_DEBUG( "waiting for idle...done\n" ); + DRM_DEBUG("waiting for idle...done\n"); - DRM_DEBUG( "BUS_CNTL = 0x%08x\n", MACH64_READ( MACH64_BUS_CNTL ) ); - DRM_DEBUG( "SRC_CNTL = 0x%08x\n", MACH64_READ( MACH64_SRC_CNTL ) ); - DRM_DEBUG( "\n" ); - DRM_DEBUG( "data bus addr = 0x%08x\n", data_addr ); - DRM_DEBUG( "table bus addr = 0x%08x\n", dev_priv->ring.start_addr ); + DRM_DEBUG("BUS_CNTL = 0x%08x\n", MACH64_READ(MACH64_BUS_CNTL)); + DRM_DEBUG("SRC_CNTL = 0x%08x\n", MACH64_READ(MACH64_SRC_CNTL)); + DRM_DEBUG("\n"); + DRM_DEBUG("data bus addr = 0x%08x\n", data_addr); + DRM_DEBUG("table bus addr = 0x%08x\n", dev_priv->ring.start_addr); - DRM_DEBUG( "starting DMA transfer...\n" ); - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - dev_priv->ring.start_addr | - MACH64_CIRCULAR_BUF_SIZE_16KB ); + DRM_DEBUG("starting DMA transfer...\n"); + MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, + dev_priv->ring.start_addr | MACH64_CIRCULAR_BUF_SIZE_16KB); - MACH64_WRITE( MACH64_SRC_CNTL, - MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC | - MACH64_SRC_BM_OP_SYSTEM_TO_REG ); + MACH64_WRITE(MACH64_SRC_CNTL, + MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC | + MACH64_SRC_BM_OP_SYSTEM_TO_REG); /* Kick off the transfer */ - DRM_DEBUG( "starting DMA transfer... done.\n" ); - MACH64_WRITE( MACH64_DST_HEIGHT_WIDTH, 0 ); + DRM_DEBUG("starting DMA transfer... done.\n"); + MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0); - DRM_DEBUG( "waiting for idle...\n" ); + DRM_DEBUG("waiting for idle...\n"); - if ( ( i = mach64_do_wait_for_idle( dev_priv ) ) ) { + if ((i = mach64_do_wait_for_idle(dev_priv))) { /* engine locked up, dump register state and reset */ - DRM_INFO( "mach64_do_wait_for_idle failed (result=%d)\n", i); - mach64_dump_engine_info( dev_priv ); - DRM_INFO( "resetting engine ...\n"); - mach64_do_engine_reset( dev_priv ); - mach64_do_wait_for_fifo( dev_priv, 3 ); - MACH64_WRITE( MACH64_SRC_CNTL, src_cntl ); - MACH64_WRITE( MACH64_PAT_REG0, pat_reg0 ); - MACH64_WRITE( MACH64_PAT_REG1, pat_reg1 ); - DRM_INFO( "freeing data buffer memory.\n" ); - drm_pci_free( dev, 0x1000, cpu_addr_data, data_handle ); + DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i); + mach64_dump_engine_info(dev_priv); + DRM_INFO("resetting engine ...\n"); + mach64_do_engine_reset(dev_priv); + mach64_do_wait_for_fifo(dev_priv, 3); + MACH64_WRITE(MACH64_SRC_CNTL, src_cntl); + MACH64_WRITE(MACH64_PAT_REG0, pat_reg0); + MACH64_WRITE(MACH64_PAT_REG1, pat_reg1); + DRM_INFO("freeing data buffer memory.\n"); + drm_pci_free(dev, 0x1000, cpu_addr_data, data_handle); return i; } - DRM_DEBUG( "waiting for idle...done\n" ); + DRM_DEBUG("waiting for idle...done\n"); /* restore SRC_CNTL */ - mach64_do_wait_for_fifo( dev_priv, 1 ); - MACH64_WRITE( MACH64_SRC_CNTL, src_cntl ); + mach64_do_wait_for_fifo(dev_priv, 1); + MACH64_WRITE(MACH64_SRC_CNTL, src_cntl); failed = 0; /* Check register values to see if the GUI master operation succeeded */ - for ( i = 0; i < 2; i++ ) { + for (i = 0; i < 2; i++) { u32 reg; - reg = MACH64_READ( (MACH64_PAT_REG0 + i*4) ); - DRM_DEBUG( "(After DMA Transfer) reg %d = 0x%08x\n", i, reg ); + reg = MACH64_READ((MACH64_PAT_REG0 + i * 4)); + DRM_DEBUG("(After DMA Transfer) reg %d = 0x%08x\n", i, reg); if (reg != expected[i]) { failed = -1; } } /* restore pattern registers */ - mach64_do_wait_for_fifo( dev_priv, 2 ); - MACH64_WRITE( MACH64_PAT_REG0, pat_reg0 ); - MACH64_WRITE( MACH64_PAT_REG1, pat_reg1 ); + mach64_do_wait_for_fifo(dev_priv, 2); + MACH64_WRITE(MACH64_PAT_REG0, pat_reg0); + MACH64_WRITE(MACH64_PAT_REG1, pat_reg1); - DRM_DEBUG( "freeing data buffer memory.\n" ); - drm_pci_free( dev, 0x1000, cpu_addr_data, data_handle ); - DRM_DEBUG( "returning ...\n" ); + DRM_DEBUG("freeing data buffer memory.\n"); + drm_pci_free(dev, 0x1000, cpu_addr_data, data_handle); + DRM_DEBUG("returning ...\n"); return failed; } - -static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init ) +static int mach64_do_dma_init(drm_device_t * dev, drm_mach64_init_t * init) { drm_mach64_private_t *dev_priv; u32 tmp; int i, ret; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - dev_priv = drm_alloc( sizeof(drm_mach64_private_t), DRM_MEM_DRIVER ); - if ( dev_priv == NULL ) + dev_priv = drm_alloc(sizeof(drm_mach64_private_t), DRM_MEM_DRIVER); + if (dev_priv == NULL) return DRM_ERR(ENOMEM); - - memset( dev_priv, 0, sizeof(drm_mach64_private_t) ); - dev_priv->is_pci = init->is_pci; + memset(dev_priv, 0, sizeof(drm_mach64_private_t)); + + dev_priv->is_pci = init->is_pci; - dev_priv->fb_bpp = init->fb_bpp; - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; + dev_priv->fb_bpp = init->fb_bpp; + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; - dev_priv->depth_bpp = init->depth_bpp; - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; + dev_priv->depth_bpp = init->depth_bpp; + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; - dev_priv->front_offset_pitch = (((dev_priv->front_pitch/8) << 22) | - (dev_priv->front_offset >> 3)); - dev_priv->back_offset_pitch = (((dev_priv->back_pitch/8) << 22) | - (dev_priv->back_offset >> 3)); - dev_priv->depth_offset_pitch = (((dev_priv->depth_pitch/8) << 22) | - (dev_priv->depth_offset >> 3)); + dev_priv->front_offset_pitch = (((dev_priv->front_pitch / 8) << 22) | + (dev_priv->front_offset >> 3)); + dev_priv->back_offset_pitch = (((dev_priv->back_pitch / 8) << 22) | + (dev_priv->back_offset >> 3)); + dev_priv->depth_offset_pitch = (((dev_priv->depth_pitch / 8) << 22) | + (dev_priv->depth_offset >> 3)); - dev_priv->usec_timeout = 1000000; + dev_priv->usec_timeout = 1000000; /* Set up the freelist, placeholder list and pending list */ INIT_LIST_HEAD(&dev_priv->free_list); @@ -651,152 +712,157 @@ static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init ) if (!dev_priv->sarea) { DRM_ERROR("can not find sarea!\n"); dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); + mach64_do_cleanup_dma(dev); + return DRM_ERR(EINVAL); } dev_priv->fb = drm_core_findmap(dev, init->fb_offset); if (!dev_priv->fb) { DRM_ERROR("can not find frame buffer map!\n"); dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); + mach64_do_cleanup_dma(dev); + return DRM_ERR(EINVAL); } dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); if (!dev_priv->mmio) { DRM_ERROR("can not find mmio map!\n"); dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); + mach64_do_cleanup_dma(dev); + return DRM_ERR(EINVAL); } dev_priv->sarea_priv = (drm_mach64_sarea_t *) - ((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); + ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); - if( !dev_priv->is_pci ) { + if (!dev_priv->is_pci) { dev_priv->ring_map = drm_core_findmap(dev, init->ring_offset); - if ( !dev_priv->ring_map ) { - DRM_ERROR( "can not find ring map!\n" ); + if (!dev_priv->ring_map) { + DRM_ERROR("can not find ring map!\n"); dev->dev_private = (void *)dev_priv; mach64_do_cleanup_dma(dev); return DRM_ERR(EINVAL); } - drm_core_ioremap( dev_priv->ring_map, dev ); - if ( !dev_priv->ring_map->handle ) { - DRM_ERROR( "can not ioremap virtual address for" - " descriptor ring\n" ); - dev->dev_private = (void *) dev_priv; - mach64_do_cleanup_dma( dev ); + drm_core_ioremap(dev_priv->ring_map, dev); + if (!dev_priv->ring_map->handle) { + DRM_ERROR("can not ioremap virtual address for" + " descriptor ring\n"); + dev->dev_private = (void *)dev_priv; + mach64_do_cleanup_dma(dev); return DRM_ERR(ENOMEM); - } - dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if ( !dev->agp_buffer_map ) { - DRM_ERROR( "can not find dma buffer map!\n" ); + } + dev->agp_buffer_map = + drm_core_findmap(dev, init->buffers_offset); + if (!dev->agp_buffer_map) { + DRM_ERROR("can not find dma buffer map!\n"); dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma( dev ); + mach64_do_cleanup_dma(dev); return DRM_ERR(EINVAL); } - /* there might be a nicer way to do this - + /* there might be a nicer way to do this - dev isn't passed all the way though the mach64 - DA */ dev_priv->dev_buffers = dev->agp_buffer_map; - drm_core_ioremap( dev->agp_buffer_map, dev ); - if ( !dev->agp_buffer_map->handle ) { - DRM_ERROR( "can not ioremap virtual address for" - " dma buffer\n" ); - dev->dev_private = (void *) dev_priv; - mach64_do_cleanup_dma( dev ); + drm_core_ioremap(dev->agp_buffer_map, dev); + if (!dev->agp_buffer_map->handle) { + DRM_ERROR("can not ioremap virtual address for" + " dma buffer\n"); + dev->dev_private = (void *)dev_priv; + mach64_do_cleanup_dma(dev); return DRM_ERR(ENOMEM); } - dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset); + dev_priv->agp_textures = + drm_core_findmap(dev, init->agp_textures_offset); if (!dev_priv->agp_textures) { - DRM_ERROR( "can not find agp texture region!\n" ); + DRM_ERROR("can not find agp texture region!\n"); dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma( dev ); + mach64_do_cleanup_dma(dev); return DRM_ERR(EINVAL); } } - dev->dev_private = (void *) dev_priv; + dev->dev_private = (void *)dev_priv; dev_priv->driver_mode = init->dma_mode; /* changing the FIFO size from the default causes problems with DMA */ - tmp = MACH64_READ( MACH64_GUI_CNTL ); - if ( (tmp & MACH64_CMDFIFO_SIZE_MASK) != MACH64_CMDFIFO_SIZE_128 ) { - DRM_INFO( "Setting FIFO size to 128 entries\n"); + tmp = MACH64_READ(MACH64_GUI_CNTL); + if ((tmp & MACH64_CMDFIFO_SIZE_MASK) != MACH64_CMDFIFO_SIZE_128) { + DRM_INFO("Setting FIFO size to 128 entries\n"); /* FIFO must be empty to change the FIFO depth */ - if ((ret=mach64_do_wait_for_idle( dev_priv ))) { - DRM_ERROR("wait for idle failed before changing FIFO depth!\n"); - mach64_do_cleanup_dma( dev ); + if ((ret = mach64_do_wait_for_idle(dev_priv))) { + DRM_ERROR + ("wait for idle failed before changing FIFO depth!\n"); + mach64_do_cleanup_dma(dev); return ret; } - MACH64_WRITE( MACH64_GUI_CNTL, ( ( tmp & ~MACH64_CMDFIFO_SIZE_MASK ) \ - | MACH64_CMDFIFO_SIZE_128 ) ); + MACH64_WRITE(MACH64_GUI_CNTL, ((tmp & ~MACH64_CMDFIFO_SIZE_MASK) + | MACH64_CMDFIFO_SIZE_128)); /* need to read GUI_STAT for proper sync according to docs */ - if ((ret=mach64_do_wait_for_idle( dev_priv ))) { - DRM_ERROR("wait for idle failed when changing FIFO depth!\n"); - mach64_do_cleanup_dma( dev ); + if ((ret = mach64_do_wait_for_idle(dev_priv))) { + DRM_ERROR + ("wait for idle failed when changing FIFO depth!\n"); + mach64_do_cleanup_dma(dev); return ret; } } /* allocate descriptor memory from pci pool */ - DRM_DEBUG( "Allocating dma descriptor ring\n" ); - dev_priv->ring.size = 0x4000; /* 16KB */ + DRM_DEBUG("Allocating dma descriptor ring\n"); + dev_priv->ring.size = 0x4000; /* 16KB */ - if ( dev_priv->is_pci ) { - dev_priv->ring.start = drm_pci_alloc( dev, dev_priv->ring.size, - dev_priv->ring.size, 0xfffffffful, - &dev_priv->ring.handle ); + if (dev_priv->is_pci) { + dev_priv->ring.start = drm_pci_alloc(dev, dev_priv->ring.size, + dev_priv->ring.size, + 0xfffffffful, + &dev_priv->ring.handle); if (!dev_priv->ring.start || !dev_priv->ring.handle) { - DRM_ERROR( "Allocating dma descriptor ring failed\n"); + DRM_ERROR("Allocating dma descriptor ring failed\n"); return DRM_ERR(ENOMEM); } else { dev_priv->ring.start_addr = (u32) dev_priv->ring.handle; } - } else { + } else { dev_priv->ring.start = dev_priv->ring_map->handle; dev_priv->ring.start_addr = (u32) dev_priv->ring_map->offset; } - memset( dev_priv->ring.start, 0, dev_priv->ring.size ); - DRM_INFO( "descriptor ring: cpu addr 0x%08x, bus addr: 0x%08x\n", - (u32) dev_priv->ring.start, dev_priv->ring.start_addr ); + memset(dev_priv->ring.start, 0, dev_priv->ring.size); + DRM_INFO("descriptor ring: cpu addr 0x%08x, bus addr: 0x%08x\n", + (u32) dev_priv->ring.start, dev_priv->ring.start_addr); ret = 0; - if ( dev_priv->driver_mode != MACH64_MODE_MMIO ) { + if (dev_priv->driver_mode != MACH64_MODE_MMIO) { /* enable block 1 registers and bus mastering */ - MACH64_WRITE( MACH64_BUS_CNTL, - ( ( MACH64_READ(MACH64_BUS_CNTL) - | MACH64_BUS_EXT_REG_EN ) - & ~MACH64_BUS_MASTER_DIS ) ); + MACH64_WRITE(MACH64_BUS_CNTL, ((MACH64_READ(MACH64_BUS_CNTL) + | MACH64_BUS_EXT_REG_EN) + & ~MACH64_BUS_MASTER_DIS)); /* try a DMA GUI-mastering pass and fall back to MMIO if it fails */ - DRM_DEBUG( "Starting DMA test...\n"); - if ( (ret=mach64_bm_dma_test( dev )) ) { + DRM_DEBUG("Starting DMA test...\n"); + if ((ret = mach64_bm_dma_test(dev))) { dev_priv->driver_mode = MACH64_MODE_MMIO; } } switch (dev_priv->driver_mode) { case MACH64_MODE_MMIO: - MACH64_WRITE( MACH64_BUS_CNTL, ( MACH64_READ(MACH64_BUS_CNTL) - | MACH64_BUS_EXT_REG_EN - | MACH64_BUS_MASTER_DIS ) ); - if ( init->dma_mode == MACH64_MODE_MMIO ) - DRM_INFO( "Forcing pseudo-DMA mode\n" ); + MACH64_WRITE(MACH64_BUS_CNTL, (MACH64_READ(MACH64_BUS_CNTL) + | MACH64_BUS_EXT_REG_EN + | MACH64_BUS_MASTER_DIS)); + if (init->dma_mode == MACH64_MODE_MMIO) + DRM_INFO("Forcing pseudo-DMA mode\n"); else - DRM_INFO( "DMA test failed (ret=%d), using pseudo-DMA mode\n", ret ); + DRM_INFO + ("DMA test failed (ret=%d), using pseudo-DMA mode\n", + ret); break; case MACH64_MODE_DMA_SYNC: - DRM_INFO( "DMA test succeeded, using synchronous DMA mode\n"); + DRM_INFO("DMA test succeeded, using synchronous DMA mode\n"); break; case MACH64_MODE_DMA_ASYNC: default: - DRM_INFO( "DMA test succeeded, using asynchronous DMA mode\n"); + DRM_INFO("DMA test succeeded, using asynchronous DMA mode\n"); } dev_priv->ring_running = 0; @@ -808,20 +874,21 @@ static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init ) dev_priv->ring.space = dev_priv->ring.size; /* setup physical address and size of descriptor table */ - mach64_do_wait_for_fifo( dev_priv, 1 ); - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - ( dev_priv->ring.head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ) ); + mach64_do_wait_for_fifo(dev_priv, 1); + MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, + (dev_priv->ring. + head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB)); /* init frame counter */ dev_priv->sarea_priv->frames_queued = 0; for (i = 0; i < MACH64_MAX_QUEUED_FRAMES; i++) { - dev_priv->frame_ofs[i] = ~0; /* All ones indicates placeholder */ + dev_priv->frame_ofs[i] = ~0; /* All ones indicates placeholder */ } /* Allocate the DMA buffer freelist */ - if ( (ret=mach64_init_freelist( dev )) ) { + if ((ret = mach64_init_freelist(dev))) { DRM_ERROR("Freelist allocation failed\n"); - mach64_do_cleanup_dma( dev ); + mach64_do_cleanup_dma(dev); return ret; } @@ -832,7 +899,7 @@ static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init ) * MMIO Pseudo-DMA (intended primarily for debugging, not performance) */ -int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ) +int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; volatile u32 *ring_read; @@ -846,45 +913,47 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ) fifo = count = reg = no_idle_wait = 0; target = MACH64_BM_ADDR; - if ( (ret=mach64_do_wait_for_idle( dev_priv )) < 0) { - DRM_INFO( "%s: idle failed before pseudo-dma dispatch, resetting engine\n", - __FUNCTION__); - mach64_dump_engine_info( dev_priv ); - mach64_do_engine_reset( dev_priv ); + if ((ret = mach64_do_wait_for_idle(dev_priv)) < 0) { + DRM_INFO + ("%s: idle failed before pseudo-dma dispatch, resetting engine\n", + __FUNCTION__); + mach64_dump_engine_info(dev_priv); + mach64_do_engine_reset(dev_priv); return ret; } ring_read = (u32 *) ring->start; - while ( ring->tail != ring->head ) { - u32 buf_addr, new_target, offset; + while (ring->tail != ring->head) { + u32 buf_addr, new_target, offset; u32 bytes, remaining, head, eol; head = ring->head; - new_target = le32_to_cpu( ring_read[head++] ) - MACH64_APERTURE_OFFSET; - buf_addr = le32_to_cpu( ring_read[head++] ); - eol = le32_to_cpu( ring_read[head] ) & MACH64_DMA_EOL; - bytes = le32_to_cpu( ring_read[head++] ) - & ~(MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL); + new_target = + le32_to_cpu(ring_read[head++]) - MACH64_APERTURE_OFFSET; + buf_addr = le32_to_cpu(ring_read[head++]); + eol = le32_to_cpu(ring_read[head]) & MACH64_DMA_EOL; + bytes = le32_to_cpu(ring_read[head++]) + & ~(MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL); head++; head &= ring->tail_mask; - /* can't wait for idle between a blit setup descriptor + /* can't wait for idle between a blit setup descriptor * and a HOSTDATA descriptor or the engine will lock */ - if (new_target == MACH64_BM_HOSTDATA && target == MACH64_BM_ADDR) + if (new_target == MACH64_BM_HOSTDATA + && target == MACH64_BM_ADDR) no_idle_wait = 1; target = new_target; found = 0; offset = 0; - list_for_each(ptr, &dev_priv->pending) - { + list_for_each(ptr, &dev_priv->pending) { entry = list_entry(ptr, drm_mach64_freelist_t, list); buf = entry->buf; - offset = buf_addr - GETBUFADDR( buf ); + offset = buf_addr - GETBUFADDR(buf); if (offset >= 0 && offset < MACH64_BUFFER_SIZE) { found = 1; break; @@ -892,30 +961,34 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ) } if (!found || buf == NULL) { - DRM_ERROR("Couldn't find pending buffer: head: %u tail: %u buf_addr: 0x%08x %s\n", - head, ring->tail, buf_addr, (eol ? "eol" : "")); - mach64_dump_ring_info( dev_priv ); - mach64_do_engine_reset( dev_priv ); + DRM_ERROR + ("Couldn't find pending buffer: head: %u tail: %u buf_addr: 0x%08x %s\n", + head, ring->tail, buf_addr, (eol ? "eol" : "")); + mach64_dump_ring_info(dev_priv); + mach64_do_engine_reset(dev_priv); return DRM_ERR(EINVAL); } - /* Hand feed the buffer to the card via MMIO, waiting for the fifo - * every 16 writes + /* Hand feed the buffer to the card via MMIO, waiting for the fifo + * every 16 writes */ - DRM_DEBUG("target: (0x%08x) %s\n", target, - (target == MACH64_BM_HOSTDATA ? "BM_HOSTDATA" : "BM_ADDR")); - DRM_DEBUG("offset: %u bytes: %u used: %u\n", offset, bytes, buf->used); + DRM_DEBUG("target: (0x%08x) %s\n", target, + (target == + MACH64_BM_HOSTDATA ? "BM_HOSTDATA" : "BM_ADDR")); + DRM_DEBUG("offset: %u bytes: %u used: %u\n", offset, bytes, + buf->used); + + remaining = (buf->used - offset) >> 2; /* dwords remaining in buffer */ + used = bytes >> 2; /* dwords in buffer for this descriptor */ + buf_ptr = (u32 *) ((char *)GETBUFPTR(buf) + offset); - remaining = (buf->used - offset) >> 2; /* dwords remaining in buffer */ - used = bytes >> 2; /* dwords in buffer for this descriptor */ - buf_ptr = (u32 *)((char *)GETBUFPTR( buf ) + offset); + while (used) { - while ( used ) { - if (count == 0) { if (target == MACH64_BM_HOSTDATA) { reg = DMAREG(MACH64_HOST_DATA0); - count = (remaining > 16) ? 16 : remaining; + count = + (remaining > 16) ? 16 : remaining; fifo = 0; } else { reg = le32_to_cpu(*buf_ptr++); @@ -924,17 +997,21 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ) } reg = reg & 0xffff; - reg = MMSELECT( reg ); + reg = MMSELECT(reg); } - while ( count && used ) { - if ( !fifo ) { + while (count && used) { + if (!fifo) { if (no_idle_wait) { - if ( (ret=mach64_do_wait_for_fifo( dev_priv, 16 )) < 0 ) { + if ((ret = + mach64_do_wait_for_fifo + (dev_priv, 16)) < 0) { no_idle_wait = 0; return ret; } } else { - if ( (ret=mach64_do_wait_for_idle( dev_priv )) < 0 ) { + if ((ret = + mach64_do_wait_for_idle + (dev_priv)) < 0) { return ret; } } @@ -942,8 +1019,9 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ) } --fifo; MACH64_WRITE(reg, le32_to_cpu(*buf_ptr++)); - used--; remaining--; - + used--; + remaining--; + reg += 4; count--; } @@ -953,13 +1031,13 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ) ring->space += (4 * sizeof(u32)); } - if ( (ret=mach64_do_wait_for_idle( dev_priv )) < 0 ) { + if ((ret = mach64_do_wait_for_idle(dev_priv)) < 0) { return ret; } - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); + MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, + ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB); - DRM_DEBUG( "%s completed\n", __FUNCTION__ ); + DRM_DEBUG("%s completed\n", __FUNCTION__); return 0; } @@ -967,38 +1045,41 @@ int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ) * DMA cleanup */ -int mach64_do_cleanup_dma( drm_device_t *dev ) +int mach64_do_cleanup_dma(drm_device_t * dev) { - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private * is freed, it's too late. */ - if ( dev->irq ) drm_irq_uninstall(dev); + if (dev->irq) + drm_irq_uninstall(dev); - if ( dev->dev_private ) { + if (dev->dev_private) { drm_mach64_private_t *dev_priv = dev->dev_private; - if ( dev_priv->is_pci ) { - if ( (dev_priv->ring.start != NULL) && dev_priv->ring.handle ) { - drm_pci_free( dev, dev_priv->ring.size, - dev_priv->ring.start, dev_priv->ring.handle ); + if (dev_priv->is_pci) { + if ((dev_priv->ring.start != NULL) + && dev_priv->ring.handle) { + drm_pci_free(dev, dev_priv->ring.size, + dev_priv->ring.start, + dev_priv->ring.handle); } } else { - if ( dev_priv->ring_map ) - drm_core_ioremapfree( dev_priv->ring_map, dev ); + if (dev_priv->ring_map) + drm_core_ioremapfree(dev_priv->ring_map, dev); } - if ( dev->agp_buffer_map ) { - drm_core_ioremapfree( dev->agp_buffer_map, dev ); + if (dev->agp_buffer_map) { + drm_core_ioremapfree(dev->agp_buffer_map, dev); dev->agp_buffer_map = NULL; } - mach64_destroy_freelist( dev ); + mach64_destroy_freelist(dev); - drm_free( dev_priv, sizeof(drm_mach64_private_t), - DRM_MEM_DRIVER ); + drm_free(dev_priv, sizeof(drm_mach64_private_t), + DRM_MEM_DRIVER); dev->dev_private = NULL; } @@ -1009,70 +1090,69 @@ int mach64_do_cleanup_dma( drm_device_t *dev ) * IOCTL handlers */ -int mach64_dma_init( DRM_IOCTL_ARGS ) +int mach64_dma_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mach64_init_t init; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - LOCK_TEST_WITH_RETURN( dev, filp ); + DRM_DEBUG("%s\n", __FUNCTION__); + + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( init, (drm_mach64_init_t *)data, - sizeof(init) ); + DRM_COPY_FROM_USER_IOCTL(init, (drm_mach64_init_t *) data, + sizeof(init)); - switch ( init.func ) { + switch (init.func) { case DRM_MACH64_INIT_DMA: - return mach64_do_dma_init( dev, &init ); + return mach64_do_dma_init(dev, &init); case DRM_MACH64_CLEANUP_DMA: - return mach64_do_cleanup_dma( dev ); + return mach64_do_cleanup_dma(dev); } - + return DRM_ERR(EINVAL); } -int mach64_dma_idle( DRM_IOCTL_ARGS ) +int mach64_dma_idle(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - return mach64_do_dma_idle( dev_priv ); + return mach64_do_dma_idle(dev_priv); } -int mach64_dma_flush( DRM_IOCTL_ARGS ) +int mach64_dma_flush(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - return mach64_do_dma_flush( dev_priv ); + return mach64_do_dma_flush(dev_priv); } -int mach64_engine_reset( DRM_IOCTL_ARGS ) +int mach64_engine_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - LOCK_TEST_WITH_RETURN( dev, filp ); + DRM_DEBUG("%s\n", __FUNCTION__); - return mach64_do_engine_reset( dev_priv ); -} + LOCK_TEST_WITH_RETURN(dev, filp); + return mach64_do_engine_reset(dev_priv); +} /* ================================================================ * Freelist management */ -int mach64_init_freelist( drm_device_t *dev ) +int mach64_init_freelist(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_mach64_private_t *dev_priv = dev->dev_private; @@ -1080,14 +1160,16 @@ int mach64_init_freelist( drm_device_t *dev ) struct list_head *ptr; int i; - DRM_DEBUG("%s: adding %d buffers to freelist\n", __FUNCTION__, dma->buf_count); + DRM_DEBUG("%s: adding %d buffers to freelist\n", __FUNCTION__, + dma->buf_count); - for ( i = 0 ; i < dma->buf_count ; i++ ) { - if ((entry = - (drm_mach64_freelist_t *) drm_alloc(sizeof(drm_mach64_freelist_t), - DRM_MEM_BUFLISTS)) == NULL) + for (i = 0; i < dma->buf_count; i++) { + if ((entry = + (drm_mach64_freelist_t *) + drm_alloc(sizeof(drm_mach64_freelist_t), + DRM_MEM_BUFLISTS)) == NULL) return DRM_ERR(ENOMEM); - memset( entry, 0, sizeof(drm_mach64_freelist_t) ); + memset(entry, 0, sizeof(drm_mach64_freelist_t)); entry->buf = dma->buflist[i]; ptr = &entry->list; list_add_tail(ptr, &dev_priv->free_list); @@ -1096,7 +1178,7 @@ int mach64_init_freelist( drm_device_t *dev ) return 0; } -void mach64_destroy_freelist( drm_device_t *dev ) +void mach64_destroy_freelist(drm_device_t * dev) { drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_freelist_t *entry; @@ -1105,44 +1187,40 @@ void mach64_destroy_freelist( drm_device_t *dev ) DRM_DEBUG("%s\n", __FUNCTION__); - list_for_each_safe(ptr, tmp, &dev_priv->pending) - { + list_for_each_safe(ptr, tmp, &dev_priv->pending) { list_del(ptr); entry = list_entry(ptr, drm_mach64_freelist_t, list); drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS); } - list_for_each_safe(ptr, tmp, &dev_priv->placeholders) - { + list_for_each_safe(ptr, tmp, &dev_priv->placeholders) { list_del(ptr); entry = list_entry(ptr, drm_mach64_freelist_t, list); drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS); } - list_for_each_safe(ptr, tmp, &dev_priv->free_list) - { + list_for_each_safe(ptr, tmp, &dev_priv->free_list) { list_del(ptr); entry = list_entry(ptr, drm_mach64_freelist_t, list); drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS); } } -/* IMPORTANT: This function should only be called when the engine is idle or locked up, +/* IMPORTANT: This function should only be called when the engine is idle or locked up, * as it assumes all buffers in the pending list have been completed by the hardware. */ -int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv ) +int mach64_do_release_used_buffers(drm_mach64_private_t * dev_priv) { struct list_head *ptr; struct list_head *tmp; drm_mach64_freelist_t *entry; int i; - if ( list_empty(&dev_priv->pending) ) + if (list_empty(&dev_priv->pending)) return 0; /* Iterate the pending list and move all buffers into the freelist... */ i = 0; - list_for_each_safe(ptr, tmp, &dev_priv->pending) - { + list_for_each_safe(ptr, tmp, &dev_priv->pending) { entry = list_entry(ptr, drm_mach64_freelist_t, list); if (entry->discard) { entry->buf->pending = 0; @@ -1152,12 +1230,13 @@ int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv ) } } - DRM_DEBUG( "%s: released %d buffers from pending list\n", __FUNCTION__, i ); + DRM_DEBUG("%s: released %d buffers from pending list\n", __FUNCTION__, + i); - return 0; + return 0; } -drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv ) +drm_buf_t *mach64_freelist_get(drm_mach64_private_t * dev_priv) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; drm_mach64_freelist_t *entry; @@ -1165,62 +1244,78 @@ drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv ) struct list_head *tmp; int t; - if ( list_empty(&dev_priv->free_list) ) { + if (list_empty(&dev_priv->free_list)) { u32 head, tail, ofs; - if ( list_empty( &dev_priv->pending ) ) { - DRM_ERROR( "Couldn't get buffer - pending and free lists empty\n" ); + if (list_empty(&dev_priv->pending)) { + DRM_ERROR + ("Couldn't get buffer - pending and free lists empty\n"); t = 0; - list_for_each( ptr, &dev_priv->placeholders ) { + list_for_each(ptr, &dev_priv->placeholders) { t++; } - DRM_INFO( "Placeholders: %d\n", t ); + DRM_INFO("Placeholders: %d\n", t); return NULL; } tail = ring->tail; - for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { - mach64_ring_tick( dev_priv, ring ); + for (t = 0; t < dev_priv->usec_timeout; t++) { + mach64_ring_tick(dev_priv, ring); head = ring->head; - if ( head == tail ) { + if (head == tail) { #if MACH64_EXTRA_CHECKING - if ( MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE ) { - DRM_ERROR( "Empty ring with non-idle engine!\n" ); - mach64_dump_ring_info( dev_priv ); + if (MACH64_READ(MACH64_GUI_STAT) & + MACH64_GUI_ACTIVE) { + DRM_ERROR + ("Empty ring with non-idle engine!\n"); + mach64_dump_ring_info(dev_priv); return NULL; } #endif /* last pass is complete, so release everything */ - mach64_do_release_used_buffers( dev_priv ); - DRM_DEBUG( "%s: idle engine, freed all buffers.\n", __FUNCTION__ ); - if ( list_empty(&dev_priv->free_list) ) { - DRM_ERROR( "Freelist empty with idle engine\n" ); + mach64_do_release_used_buffers(dev_priv); + DRM_DEBUG + ("%s: idle engine, freed all buffers.\n", + __FUNCTION__); + if (list_empty(&dev_priv->free_list)) { + DRM_ERROR + ("Freelist empty with idle engine\n"); return NULL; } goto _freelist_entry_found; } - /* Look for a completed buffer and bail out of the loop + /* Look for a completed buffer and bail out of the loop * as soon as we find one -- don't waste time trying * to free extra bufs here, leave that to do_release_used_buffers */ list_for_each_safe(ptr, tmp, &dev_priv->pending) { - entry = list_entry(ptr, drm_mach64_freelist_t, list); + entry = + list_entry(ptr, drm_mach64_freelist_t, + list); ofs = entry->ring_ofs; - if ( entry->discard && - ((head < tail && (ofs < head || ofs >= tail)) || - (head > tail && (ofs < head && ofs >= tail))) ) { + if (entry->discard && + ((head < tail + && (ofs < head || ofs >= tail)) + || (head > tail + && (ofs < head && ofs >= tail)))) { #if MACH64_EXTRA_CHECKING int i; - - for ( i = head ; i != tail ; i = (i + 4) & ring->tail_mask ) { - u32 o1 = le32_to_cpu(((u32 *)ring->start)[i + 1]); - u32 o2 = GETBUFADDR( entry->buf ); - - if ( o1 == o2 ) { - DRM_ERROR ( "Attempting to free used buffer: " - "i=%d buf=0x%08x\n", i, o1 ); - mach64_dump_ring_info( dev_priv ); + + for (i = head; i != tail; + i = (i + 4) & ring->tail_mask) { + u32 o1 = + le32_to_cpu(((u32 *) ring-> + start)[i + 1]); + u32 o2 = GETBUFADDR(entry->buf); + + if (o1 == o2) { + DRM_ERROR + ("Attempting to free used buffer: " + "i=%d buf=0x%08x\n", + i, o1); + mach64_dump_ring_info + (dev_priv); return NULL; } } @@ -1229,21 +1324,25 @@ drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv ) entry->buf->pending = 0; list_del(ptr); entry->buf->used = 0; - list_add_tail(ptr, &dev_priv->placeholders); - DRM_DEBUG( "%s: freed processed buffer (head=%d tail=%d " - "buf ring ofs=%d).\n", __FUNCTION__, head, tail, ofs ); + list_add_tail(ptr, + &dev_priv->placeholders); + DRM_DEBUG + ("%s: freed processed buffer (head=%d tail=%d " + "buf ring ofs=%d).\n", + __FUNCTION__, head, tail, ofs); return entry->buf; } } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } - mach64_dump_ring_info( dev_priv ); - DRM_ERROR( "timeout waiting for buffers: ring head_addr: 0x%08x head: %d tail: %d\n", - ring->head_addr, ring->head, ring->tail ); + mach64_dump_ring_info(dev_priv); + DRM_ERROR + ("timeout waiting for buffers: ring head_addr: 0x%08x head: %d tail: %d\n", + ring->head_addr, ring->head, ring->tail); return NULL; } -_freelist_entry_found: + _freelist_entry_found: ptr = dev_priv->free_list.next; list_del(ptr); entry = list_entry(ptr, drm_mach64_freelist_t, list); @@ -1256,27 +1355,30 @@ _freelist_entry_found: * DMA buffer request and submission IOCTL handler */ -static int mach64_dma_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) +static int mach64_dma_get_buffers(DRMFILE filp, drm_device_t * dev, + drm_dma_t * d) { int i; drm_buf_t *buf; drm_mach64_private_t *dev_priv = dev->dev_private; - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = mach64_freelist_get( dev_priv ); + for (i = d->granted_count; i < d->request_count; i++) { + buf = mach64_freelist_get(dev_priv); #if MACH64_EXTRA_CHECKING - if ( !buf ) return DRM_ERR(EFAULT); + if (!buf) + return DRM_ERR(EFAULT); #else - if ( !buf ) return DRM_ERR(EAGAIN); + if (!buf) + return DRM_ERR(EAGAIN); #endif buf->filp = filp; - if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, - sizeof(buf->idx) ) ) + if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, + sizeof(buf->idx))) return DRM_ERR(EFAULT); - if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, - sizeof(buf->total) ) ) + if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, + sizeof(buf->total))) return DRM_ERR(EFAULT); d->granted_count++; @@ -1284,48 +1386,45 @@ static int mach64_dma_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d return 0; } -int mach64_dma_buffers( DRM_IOCTL_ARGS ) +int mach64_dma_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; drm_dma_t d; - int ret = 0; + int ret = 0; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) ); + DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t *) data, sizeof(d)); - /* Please don't send us buffers. + /* Please don't send us buffers. */ - if ( d.send_count != 0 ) - { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count ); + if (d.send_count != 0) { + DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", + DRM_CURRENTPID, d.send_count); return DRM_ERR(EINVAL); } /* We'll send you buffers. */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) - { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count ); + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", + DRM_CURRENTPID, d.request_count, dma->buf_count); ret = DRM_ERR(EINVAL); } d.granted_count = 0; - if ( d.request_count ) - { - ret = mach64_dma_get_buffers( filp, dev, &d ); + if (d.request_count) { + ret = mach64_dma_get_buffers(filp, dev, &d); } - DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) ); + DRM_COPY_TO_USER_IOCTL((drm_dma_t *) data, d, sizeof(d)); - return ret; + return ret; } -void mach64_driver_pretakedown(drm_device_t *dev) +void mach64_driver_pretakedown(drm_device_t * dev) { - mach64_do_cleanup_dma( dev ); + mach64_do_cleanup_dma(dev); } diff --git a/shared-core/mach64_drm.h b/shared-core/mach64_drm.h index 9d748a37..3cf8da64 100644 --- a/shared-core/mach64_drm.h +++ b/shared-core/mach64_drm.h @@ -33,7 +33,6 @@ #ifndef __MACH64_DRM_H__ #define __MACH64_DRM_H__ - /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (mach64_sarea.h) */ @@ -57,7 +56,7 @@ #define MACH64_UPLOAD_TEXTURE 0x0200 #define MACH64_UPLOAD_TEX0IMAGE 0x0400 #define MACH64_UPLOAD_TEX1IMAGE 0x0800 -#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */ +#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */ #define MACH64_UPLOAD_CONTEXT 0x00ff #define MACH64_UPLOAD_ALL 0x1fff @@ -78,7 +77,6 @@ */ #define MACH64_NR_SAREA_CLIPRECTS 8 - #define MACH64_CARD_HEAP 0 #define MACH64_AGP_HEAP 1 #define MACH64_NR_TEX_HEAPS 2 @@ -90,7 +88,7 @@ #define MACH64_NR_CONTEXT_REGS 15 #define MACH64_NR_TEXTURE_REGS 4 -#endif /* __MACH64_SAREA_DEFINES__ */ +#endif /* __MACH64_SAREA_DEFINES__ */ typedef struct { unsigned int dst_off_pitch; @@ -140,17 +138,17 @@ typedef struct drm_mach64_sarea { /* Texture memory LRU. */ - drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS+1]; + drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS + + 1]; unsigned int tex_age[MACH64_NR_TEX_HEAPS]; int ctx_owner; } drm_mach64_sarea_t; - /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (mach64_common.h) */ -/* Mach64 specific ioctls +/* Mach64 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ @@ -193,11 +191,10 @@ typedef struct drm_mach64_sarea { #define MACH64_PRIM_QUAD_STRIP 0x00000008 #define MACH64_PRIM_POLYGON 0x00000009 - typedef enum _drm_mach64_dma_mode_t { - MACH64_MODE_DMA_ASYNC, - MACH64_MODE_DMA_SYNC, - MACH64_MODE_MMIO + MACH64_MODE_DMA_ASYNC, + MACH64_MODE_DMA_SYNC, + MACH64_MODE_MMIO } drm_mach64_dma_mode_t; typedef struct drm_mach64_init { @@ -233,9 +230,9 @@ typedef struct drm_mach64_clear { typedef struct drm_mach64_vertex { int prim; - void *buf; /* Address of vertex buffer */ - unsigned long used; /* Number of bytes in buffer */ - int discard; /* Client finished with buffer? */ + void *buf; /* Address of vertex buffer */ + unsigned long used; /* Number of bytes in buffer */ + int discard; /* Client finished with buffer? */ } drm_mach64_vertex_t; typedef struct drm_mach64_blit { diff --git a/shared-core/mach64_drv.h b/shared-core/mach64_drv.h index f047b7ef..698a6a51 100644 --- a/shared-core/mach64_drv.h +++ b/shared-core/mach64_drv.h @@ -49,45 +49,45 @@ /* FIXME: remove these when not needed */ /* Development driver options */ -#define MACH64_EXTRA_CHECKING 0 /* Extra sanity checks for DMA/freelist management */ -#define MACH64_VERBOSE 0 /* Verbose debugging output */ +#define MACH64_EXTRA_CHECKING 0 /* Extra sanity checks for DMA/freelist management */ +#define MACH64_VERBOSE 0 /* Verbose debugging output */ typedef struct drm_mach64_freelist { - struct list_head list; /* List pointers for free_list, placeholders, or pending list */ - drm_buf_t *buf; /* Pointer to the buffer */ - int discard; /* This flag is set when we're done (re)using a buffer */ - u32 ring_ofs; /* dword offset in ring of last descriptor for this buffer */ + struct list_head list; /* List pointers for free_list, placeholders, or pending list */ + drm_buf_t *buf; /* Pointer to the buffer */ + int discard; /* This flag is set when we're done (re)using a buffer */ + u32 ring_ofs; /* dword offset in ring of last descriptor for this buffer */ } drm_mach64_freelist_t; typedef struct drm_mach64_descriptor_ring { - dma_addr_t handle; /* handle (bus address) of ring returned by pci_alloc_consistent() */ - void *start; /* write pointer (cpu address) to start of descriptor ring */ - u32 start_addr; /* bus address of beginning of descriptor ring */ - int size; /* size of ring in bytes */ - - u32 head_addr; /* bus address of descriptor ring head */ - u32 head; /* dword offset of descriptor ring head */ - u32 tail; /* dword offset of descriptor ring tail */ - u32 tail_mask; /* mask used to wrap ring */ - int space; /* number of free bytes in ring */ + dma_addr_t handle; /* handle (bus address) of ring returned by pci_alloc_consistent() */ + void *start; /* write pointer (cpu address) to start of descriptor ring */ + u32 start_addr; /* bus address of beginning of descriptor ring */ + int size; /* size of ring in bytes */ + + u32 head_addr; /* bus address of descriptor ring head */ + u32 head; /* dword offset of descriptor ring head */ + u32 tail; /* dword offset of descriptor ring tail */ + u32 tail_mask; /* mask used to wrap ring */ + int space; /* number of free bytes in ring */ } drm_mach64_descriptor_ring_t; typedef struct drm_mach64_private { drm_mach64_sarea_t *sarea_priv; int is_pci; - drm_mach64_dma_mode_t driver_mode; /* Async DMA, sync DMA, or MMIO */ + drm_mach64_dma_mode_t driver_mode; /* Async DMA, sync DMA, or MMIO */ - int usec_timeout; /* Timeout for the wait functions */ + int usec_timeout; /* Timeout for the wait functions */ - drm_mach64_descriptor_ring_t ring; /* DMA descriptor table (ring buffer) */ - int ring_running; /* Is bus mastering is enabled */ + drm_mach64_descriptor_ring_t ring; /* DMA descriptor table (ring buffer) */ + int ring_running; /* Is bus mastering is enabled */ - struct list_head free_list; /* Free-list head */ - struct list_head placeholders; /* Placeholder list for buffers held by clients */ - struct list_head pending; /* Buffers pending completion */ + struct list_head free_list; /* Free-list head */ + struct list_head placeholders; /* Placeholder list for buffers held by clients */ + struct list_head pending; /* Buffers pending completion */ - u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES]; /* dword ring offsets of most recent frame swaps */ + u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES]; /* dword ring offsets of most recent frame swaps */ unsigned int fb_bpp; unsigned int front_offset, front_pitch; @@ -104,48 +104,49 @@ typedef struct drm_mach64_private { drm_local_map_t *fb; drm_local_map_t *mmio; drm_local_map_t *ring_map; - drm_local_map_t *dev_buffers; /* this is a pointer to a structure in dev */ + drm_local_map_t *dev_buffers; /* this is a pointer to a structure in dev */ drm_local_map_t *agp_textures; } drm_mach64_private_t; /* mach64_dma.c */ -extern int mach64_dma_init( DRM_IOCTL_ARGS ); -extern int mach64_dma_idle( DRM_IOCTL_ARGS ); -extern int mach64_dma_flush( DRM_IOCTL_ARGS ); -extern int mach64_engine_reset( DRM_IOCTL_ARGS ); -extern int mach64_dma_buffers( DRM_IOCTL_ARGS ); -extern void mach64_driver_pretakedown(drm_device_t *dev); - -extern int mach64_init_freelist( drm_device_t *dev ); -extern void mach64_destroy_freelist( drm_device_t *dev ); -extern drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv ); - -extern int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv, - int entries ); -extern int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv ); -extern int mach64_wait_ring( drm_mach64_private_t *dev_priv, int n ); -extern int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ); -extern int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv ); -extern void mach64_dump_engine_info( drm_mach64_private_t *dev_priv ); -extern void mach64_dump_ring_info( drm_mach64_private_t *dev_priv ); -extern int mach64_do_engine_reset( drm_mach64_private_t *dev_priv ); - -extern int mach64_do_dma_idle( drm_mach64_private_t *dev_priv ); -extern int mach64_do_dma_flush( drm_mach64_private_t *dev_priv ); -extern int mach64_do_cleanup_dma( drm_device_t *dev ); +extern int mach64_dma_init(DRM_IOCTL_ARGS); +extern int mach64_dma_idle(DRM_IOCTL_ARGS); +extern int mach64_dma_flush(DRM_IOCTL_ARGS); +extern int mach64_engine_reset(DRM_IOCTL_ARGS); +extern int mach64_dma_buffers(DRM_IOCTL_ARGS); +extern void mach64_driver_pretakedown(drm_device_t * dev); + +extern int mach64_init_freelist(drm_device_t * dev); +extern void mach64_destroy_freelist(drm_device_t * dev); +extern drm_buf_t *mach64_freelist_get(drm_mach64_private_t * dev_priv); + +extern int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv, + int entries); +extern int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv); +extern int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n); +extern int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv); +extern int mach64_do_release_used_buffers(drm_mach64_private_t * dev_priv); +extern void mach64_dump_engine_info(drm_mach64_private_t * dev_priv); +extern void mach64_dump_ring_info(drm_mach64_private_t * dev_priv); +extern int mach64_do_engine_reset(drm_mach64_private_t * dev_priv); + +extern int mach64_do_dma_idle(drm_mach64_private_t * dev_priv); +extern int mach64_do_dma_flush(drm_mach64_private_t * dev_priv); +extern int mach64_do_cleanup_dma(drm_device_t * dev); /* mach64_state.c */ -extern int mach64_dma_clear( DRM_IOCTL_ARGS ); -extern int mach64_dma_swap( DRM_IOCTL_ARGS ); -extern int mach64_dma_vertex( DRM_IOCTL_ARGS ); -extern int mach64_dma_blit( DRM_IOCTL_ARGS ); -extern int mach64_get_param( DRM_IOCTL_ARGS ); -extern int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); - -extern irqreturn_t mach64_driver_irq_handler( DRM_IRQ_ARGS ); -extern void mach64_driver_irq_preinstall( drm_device_t *dev ); -extern void mach64_driver_irq_postinstall( drm_device_t *dev ); -extern void mach64_driver_irq_uninstall( drm_device_t *dev ); +extern int mach64_dma_clear(DRM_IOCTL_ARGS); +extern int mach64_dma_swap(DRM_IOCTL_ARGS); +extern int mach64_dma_vertex(DRM_IOCTL_ARGS); +extern int mach64_dma_blit(DRM_IOCTL_ARGS); +extern int mach64_get_param(DRM_IOCTL_ARGS); +extern int mach64_driver_vblank_wait(drm_device_t * dev, + unsigned int *sequence); + +extern irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS); +extern void mach64_driver_irq_preinstall(drm_device_t * dev); +extern void mach64_driver_irq_postinstall(drm_device_t * dev); +extern void mach64_driver_irq_uninstall(drm_device_t * dev); /* ================================================================ * Registers @@ -155,7 +156,6 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev ); #define MACH64_AGP_CNTL 0x014c #define MACH64_ALPHA_TST_CNTL 0x0550 - #define MACH64_DSP_CONFIG 0x0420 #define MACH64_DSP_ON_OFF 0x0424 #define MACH64_EXT_MEM_CNTL 0x04ac @@ -165,7 +165,6 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev ); #define MACH64_MEM_BUF_CNTL 0x042c #define MACH64_MEM_CNTL 0x04b0 - #define MACH64_BM_ADDR 0x0648 #define MACH64_BM_COMMAND 0x0188 #define MACH64_BM_DATA 0x0648 @@ -390,17 +389,17 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev ); # define MACH64_CRTC_VBLANK_INT (1 << 2) # define MACH64_CRTC_VLINE_INT_EN (1 << 3) # define MACH64_CRTC_VLINE_INT (1 << 4) -# define MACH64_CRTC_VLINE_SYNC (1 << 5) /* 0=even, 1=odd */ -# define MACH64_CRTC_FRAME (1 << 6) /* 0=even, 1=odd */ +# define MACH64_CRTC_VLINE_SYNC (1 << 5) /* 0=even, 1=odd */ +# define MACH64_CRTC_FRAME (1 << 6) /* 0=even, 1=odd */ # define MACH64_CRTC_SNAPSHOT_INT_EN (1 << 7) # define MACH64_CRTC_SNAPSHOT_INT (1 << 8) # define MACH64_CRTC_I2C_INT_EN (1 << 9) # define MACH64_CRTC_I2C_INT (1 << 10) -# define MACH64_CRTC2_VBLANK (1 << 11) /* LT Pro */ -# define MACH64_CRTC2_VBLANK_INT_EN (1 << 12) /* LT Pro */ -# define MACH64_CRTC2_VBLANK_INT (1 << 13) /* LT Pro */ -# define MACH64_CRTC2_VLINE_INT_EN (1 << 14) /* LT Pro */ -# define MACH64_CRTC2_VLINE_INT (1 << 15) /* LT Pro */ +# define MACH64_CRTC2_VBLANK (1 << 11) /* LT Pro */ +# define MACH64_CRTC2_VBLANK_INT_EN (1 << 12) /* LT Pro */ +# define MACH64_CRTC2_VBLANK_INT (1 << 13) /* LT Pro */ +# define MACH64_CRTC2_VLINE_INT_EN (1 << 14) /* LT Pro */ +# define MACH64_CRTC2_VLINE_INT (1 << 15) /* LT Pro */ # define MACH64_CRTC_CAPBUF0_INT_EN (1 << 16) # define MACH64_CRTC_CAPBUF0_INT (1 << 17) # define MACH64_CRTC_CAPBUF1_INT_EN (1 << 18) @@ -413,9 +412,9 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev ); # define MACH64_CRTC_BUSMASTER_EOL_INT (1 << 25) # define MACH64_CRTC_GP_INT_EN (1 << 26) # define MACH64_CRTC_GP_INT (1 << 27) -# define MACH64_CRTC2_VLINE_SYNC (1 << 28) /* LT Pro */ /* 0=even, 1=odd */ -# define MACH64_CRTC_SNAPSHOT2_INT_EN (1 << 29) /* LT Pro */ -# define MACH64_CRTC_SNAPSHOT2_INT (1 << 30) /* LT Pro */ +# define MACH64_CRTC2_VLINE_SYNC (1 << 28) /* LT Pro */ /* 0=even, 1=odd */ +# define MACH64_CRTC_SNAPSHOT2_INT_EN (1 << 29) /* LT Pro */ +# define MACH64_CRTC_SNAPSHOT2_INT (1 << 30) /* LT Pro */ # define MACH64_CRTC_VBLANK2_INT (1 << 31) # define MACH64_CRTC_INT_ENS \ ( \ @@ -468,7 +467,6 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev ); #define MACH64_READ(reg) DRM_READ32(dev_priv->mmio, (reg) ) #define MACH64_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio, (reg), (val) ) - #define DWMREG0 0x0400 #define DWMREG0_END 0x07ff #define DWMREG1 0x0000 @@ -492,254 +490,246 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev ); */ /* DMA descriptor field indices: - * The descriptor fields are loaded into the read-only + * The descriptor fields are loaded into the read-only * BM_* system bus master registers during a bus-master operation */ -#define MACH64_DMA_FRAME_BUF_OFFSET 0 /* BM_FRAME_BUF_OFFSET */ -#define MACH64_DMA_SYS_MEM_ADDR 1 /* BM_SYSTEM_MEM_ADDR */ -#define MACH64_DMA_COMMAND 2 /* BM_COMMAND */ -#define MACH64_DMA_RESERVED 3 /* BM_STATUS */ +#define MACH64_DMA_FRAME_BUF_OFFSET 0 /* BM_FRAME_BUF_OFFSET */ +#define MACH64_DMA_SYS_MEM_ADDR 1 /* BM_SYSTEM_MEM_ADDR */ +#define MACH64_DMA_COMMAND 2 /* BM_COMMAND */ +#define MACH64_DMA_RESERVED 3 /* BM_STATUS */ /* BM_COMMAND descriptor field flags */ -#define MACH64_DMA_HOLD_OFFSET (1<<30) /* Don't increment DMA_FRAME_BUF_OFFSET */ -#define MACH64_DMA_EOL (1<<31) /* End of descriptor list flag */ - -#define MACH64_DMA_CHUNKSIZE 0x1000 /* 4kB per DMA descriptor */ -#define MACH64_APERTURE_OFFSET 0x7ff800 /* frame-buffer offset for gui-masters */ +#define MACH64_DMA_HOLD_OFFSET (1<<30) /* Don't increment DMA_FRAME_BUF_OFFSET */ +#define MACH64_DMA_EOL (1<<31) /* End of descriptor list flag */ +#define MACH64_DMA_CHUNKSIZE 0x1000 /* 4kB per DMA descriptor */ +#define MACH64_APERTURE_OFFSET 0x7ff800 /* frame-buffer offset for gui-masters */ /* ================================================================ * Misc helper macros */ -static __inline__ void mach64_set_dma_eol( volatile u32 * addr ) +static __inline__ void mach64_set_dma_eol(volatile u32 * addr) { #if defined(__i386__) int nr = 31; - + /* Taken from include/asm-i386/bitops.h linux header */ - __asm__ __volatile__( "lock;" - "btsl %1,%0" - :"=m" (*addr) - :"Ir" (nr)); + __asm__ __volatile__("lock;" "btsl %1,%0":"=m"(*addr) + :"Ir"(nr)); #elif defined(__powerpc__) u32 old; - u32 mask = cpu_to_le32( MACH64_DMA_EOL ); + u32 mask = cpu_to_le32(MACH64_DMA_EOL); /* Taken from the include/asm-ppc/bitops.h linux header */ __asm__ __volatile__("\n\ 1: lwarx %0,0,%3 \n\ or %0,%0,%2 \n\ stwcx. %0,0,%3 \n\ - bne- 1b" - : "=&r" (old), "=m" (*addr) - : "r" (mask), "r" (addr), "m" (*addr) - : "cc"); + bne- 1b":"=&r"(old), "=m"(*addr) + :"r"(mask), "r"(addr), "m"(*addr) + :"cc"); #elif defined(__alpha__) u32 temp; u32 mask = MACH64_DMA_EOL; /* Taken from the include/asm-alpha/bitops.h linux header */ - __asm__ __volatile__( - "1: ldl_l %0,%3\n" - " bis %0,%2,%0\n" - " stl_c %0,%1\n" - " beq %0,2f\n" - ".subsection 2\n" - "2: br 1b\n" - ".previous" - :"=&r" (temp), "=m" (*addr) - :"Ir" (mask), "m" (*addr)); + __asm__ __volatile__("1: ldl_l %0,%3\n" + " bis %0,%2,%0\n" + " stl_c %0,%1\n" + " beq %0,2f\n" + ".subsection 2\n" + "2: br 1b\n" + ".previous":"=&r"(temp), "=m"(*addr) + :"Ir"(mask), "m"(*addr)); #else - u32 mask = cpu_to_le32( MACH64_DMA_EOL ); + u32 mask = cpu_to_le32(MACH64_DMA_EOL); *addr |= mask; #endif } -static __inline__ void mach64_clear_dma_eol( volatile u32 * addr ) +static __inline__ void mach64_clear_dma_eol(volatile u32 * addr) { #if defined(__i386__) int nr = 31; - + /* Taken from include/asm-i386/bitops.h linux header */ - __asm__ __volatile__( "lock;" - "btrl %1,%0" - :"=m" (*addr) - :"Ir" (nr)); + __asm__ __volatile__("lock;" "btrl %1,%0":"=m"(*addr) + :"Ir"(nr)); #elif defined(__powerpc__) u32 old; - u32 mask = cpu_to_le32( MACH64_DMA_EOL ); + u32 mask = cpu_to_le32(MACH64_DMA_EOL); /* Taken from the include/asm-ppc/bitops.h linux header */ __asm__ __volatile__("\n\ 1: lwarx %0,0,%3 \n\ andc %0,%0,%2 \n\ stwcx. %0,0,%3 \n\ - bne- 1b" - : "=&r" (old), "=m" (*addr) - : "r" (mask), "r" (addr), "m" (*addr) - : "cc"); + bne- 1b":"=&r"(old), "=m"(*addr) + :"r"(mask), "r"(addr), "m"(*addr) + :"cc"); #elif defined(__alpha__) u32 temp; u32 mask = ~MACH64_DMA_EOL; /* Taken from the include/asm-alpha/bitops.h linux header */ - __asm__ __volatile__( - "1: ldl_l %0,%3\n" - " and %0,%2,%0\n" - " stl_c %0,%1\n" - " beq %0,2f\n" - ".subsection 2\n" - "2: br 1b\n" - ".previous" - :"=&r" (temp), "=m" (*addr) - :"Ir" (mask), "m" (*addr)); + __asm__ __volatile__("1: ldl_l %0,%3\n" + " and %0,%2,%0\n" + " stl_c %0,%1\n" + " beq %0,2f\n" + ".subsection 2\n" + "2: br 1b\n" + ".previous":"=&r"(temp), "=m"(*addr) + :"Ir"(mask), "m"(*addr)); #else - u32 mask = cpu_to_le32( ~MACH64_DMA_EOL ); + u32 mask = cpu_to_le32(~MACH64_DMA_EOL); *addr &= mask; #endif } -static __inline__ void mach64_ring_start( drm_mach64_private_t *dev_priv ) +static __inline__ void mach64_ring_start(drm_mach64_private_t * dev_priv) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - - DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", - __FUNCTION__, - ring->head_addr, ring->head, ring->tail, ring->space ); - if ( mach64_do_wait_for_idle( dev_priv ) < 0 ) { - mach64_do_engine_reset( dev_priv ); + DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", + __FUNCTION__, + ring->head_addr, ring->head, ring->tail, ring->space); + + if (mach64_do_wait_for_idle(dev_priv) < 0) { + mach64_do_engine_reset(dev_priv); } - if (dev_priv->driver_mode != MACH64_MODE_MMIO ) { + if (dev_priv->driver_mode != MACH64_MODE_MMIO) { /* enable bus mastering and block 1 registers */ - MACH64_WRITE( MACH64_BUS_CNTL, - ( MACH64_READ(MACH64_BUS_CNTL) & ~MACH64_BUS_MASTER_DIS ) - | MACH64_BUS_EXT_REG_EN ); - mach64_do_wait_for_idle( dev_priv ); + MACH64_WRITE(MACH64_BUS_CNTL, + (MACH64_READ(MACH64_BUS_CNTL) & + ~MACH64_BUS_MASTER_DIS) + | MACH64_BUS_EXT_REG_EN); + mach64_do_wait_for_idle(dev_priv); } - + /* reset descriptor table ring head */ - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); - + MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, + ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB); + dev_priv->ring_running = 1; } -static __inline__ void mach64_ring_resume( drm_mach64_private_t *dev_priv, - drm_mach64_descriptor_ring_t *ring ) +static __inline__ void mach64_ring_resume(drm_mach64_private_t * dev_priv, + drm_mach64_descriptor_ring_t * ring) { - DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", - __FUNCTION__, - ring->head_addr, ring->head, ring->tail, ring->space ); + DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", + __FUNCTION__, + ring->head_addr, ring->head, ring->tail, ring->space); /* reset descriptor table ring head */ - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); + MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD, + ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB); - if ( dev_priv->driver_mode == MACH64_MODE_MMIO ) { - mach64_do_dispatch_pseudo_dma( dev_priv ); + if (dev_priv->driver_mode == MACH64_MODE_MMIO) { + mach64_do_dispatch_pseudo_dma(dev_priv); } else { /* enable GUI bus mastering, and sync the bus master to the GUI */ - MACH64_WRITE( MACH64_SRC_CNTL, - MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC | - MACH64_SRC_BM_OP_SYSTEM_TO_REG ); + MACH64_WRITE(MACH64_SRC_CNTL, + MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC | + MACH64_SRC_BM_OP_SYSTEM_TO_REG); /* kick off the transfer */ - MACH64_WRITE( MACH64_DST_HEIGHT_WIDTH, 0 ); - if ( dev_priv->driver_mode == MACH64_MODE_DMA_SYNC ) { - if ( (mach64_do_wait_for_idle( dev_priv )) < 0 ) { - DRM_ERROR( "%s: idle failed, resetting engine\n", - __FUNCTION__); - mach64_dump_engine_info( dev_priv ); - mach64_do_engine_reset( dev_priv ); + MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0); + if (dev_priv->driver_mode == MACH64_MODE_DMA_SYNC) { + if ((mach64_do_wait_for_idle(dev_priv)) < 0) { + DRM_ERROR("%s: idle failed, resetting engine\n", + __FUNCTION__); + mach64_dump_engine_info(dev_priv); + mach64_do_engine_reset(dev_priv); return; } - mach64_do_release_used_buffers( dev_priv ); + mach64_do_release_used_buffers(dev_priv); } } } -static __inline__ void mach64_ring_tick( drm_mach64_private_t *dev_priv, - drm_mach64_descriptor_ring_t *ring ) +static __inline__ void mach64_ring_tick(drm_mach64_private_t * dev_priv, + drm_mach64_descriptor_ring_t * ring) { - DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", - __FUNCTION__, - ring->head_addr, ring->head, ring->tail, ring->space ); - - if ( !dev_priv->ring_running ) { - mach64_ring_start( dev_priv ); - - if ( ring->head != ring->tail ) { - mach64_ring_resume( dev_priv, ring ); + DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", + __FUNCTION__, + ring->head_addr, ring->head, ring->tail, ring->space); + + if (!dev_priv->ring_running) { + mach64_ring_start(dev_priv); + + if (ring->head != ring->tail) { + mach64_ring_resume(dev_priv, ring); } } else { - /* GUI_ACTIVE must be read before BM_GUI_TABLE to - * correctly determine the ring head + /* GUI_ACTIVE must be read before BM_GUI_TABLE to + * correctly determine the ring head */ - int gui_active = MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE; - + int gui_active = + MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE; + ring->head_addr = MACH64_READ(MACH64_BM_GUI_TABLE) & 0xfffffff0; - - if ( gui_active ) { - /* If not idle, BM_GUI_TABLE points one descriptor - * past the current head + + if (gui_active) { + /* If not idle, BM_GUI_TABLE points one descriptor + * past the current head */ - if ( ring->head_addr == ring->start_addr ) { + if (ring->head_addr == ring->start_addr) { ring->head_addr += ring->size; } ring->head_addr -= 4 * sizeof(u32); } - if( ring->head_addr < ring->start_addr || - ring->head_addr >= ring->start_addr + ring->size ) { - DRM_ERROR( "bad ring head address: 0x%08x\n", ring->head_addr ); - mach64_dump_ring_info( dev_priv ); - mach64_do_engine_reset( dev_priv ); + if (ring->head_addr < ring->start_addr || + ring->head_addr >= ring->start_addr + ring->size) { + DRM_ERROR("bad ring head address: 0x%08x\n", + ring->head_addr); + mach64_dump_ring_info(dev_priv); + mach64_do_engine_reset(dev_priv); return; } - + ring->head = (ring->head_addr - ring->start_addr) / sizeof(u32); - - if ( !gui_active && ring->head != ring->tail ) { - mach64_ring_resume( dev_priv, ring ); + + if (!gui_active && ring->head != ring->tail) { + mach64_ring_resume(dev_priv, ring); } } } -static __inline__ void mach64_ring_stop( drm_mach64_private_t *dev_priv ) +static __inline__ void mach64_ring_stop(drm_mach64_private_t * dev_priv) { - DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", - __FUNCTION__, - dev_priv->ring.head_addr, dev_priv->ring.head, - dev_priv->ring.tail, dev_priv->ring.space ); + DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", + __FUNCTION__, + dev_priv->ring.head_addr, dev_priv->ring.head, + dev_priv->ring.tail, dev_priv->ring.space); /* restore previous SRC_CNTL to disable busmastering */ - mach64_do_wait_for_fifo( dev_priv, 1 ); - MACH64_WRITE( MACH64_SRC_CNTL, 0 ); - - /* disable busmastering but keep the block 1 registers enabled */ - mach64_do_wait_for_idle( dev_priv ); - MACH64_WRITE( MACH64_BUS_CNTL, MACH64_READ( MACH64_BUS_CNTL ) - | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN ); - + mach64_do_wait_for_fifo(dev_priv, 1); + MACH64_WRITE(MACH64_SRC_CNTL, 0); + + /* disable busmastering but keep the block 1 registers enabled */ + mach64_do_wait_for_idle(dev_priv); + MACH64_WRITE(MACH64_BUS_CNTL, MACH64_READ(MACH64_BUS_CNTL) + | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN); + dev_priv->ring_running = 0; } static __inline__ void -mach64_update_ring_snapshot( drm_mach64_private_t *dev_priv ) +mach64_update_ring_snapshot(drm_mach64_private_t * dev_priv) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - mach64_ring_tick( dev_priv, ring ); + DRM_DEBUG("%s\n", __FUNCTION__); + + mach64_ring_tick(dev_priv, ring); ring->space = (ring->head - ring->tail) * sizeof(u32); - if ( ring->space <= 0 ) { + if (ring->space <= 0) { ring->space += ring->size; } } @@ -797,7 +787,6 @@ do { \ mach64_ring_tick( dev_priv, &(dev_priv)->ring ); \ } while (0) - /* ================================================================ * DMA macros */ @@ -816,9 +805,10 @@ do { \ #define GETRINGOFFSET() (_entry->ring_ofs) -static __inline__ int mach64_find_pending_buf_entry ( drm_mach64_private_t *dev_priv, - drm_mach64_freelist_t **entry, - drm_buf_t *buf ) +static __inline__ int mach64_find_pending_buf_entry(drm_mach64_private_t * + dev_priv, + drm_mach64_freelist_t ** + entry, drm_buf_t * buf) { struct list_head *ptr; #if MACH64_EXTRA_CHECKING @@ -1050,4 +1040,4 @@ do { \ ADVANCE_RING(); \ } while(0) -#endif /* __MACH64_DRV_H__ */ +#endif /* __MACH64_DRV_H__ */ diff --git a/shared-core/mach64_irq.c b/shared-core/mach64_irq.c index 966c3c10..b8853c1c 100644 --- a/shared-core/mach64_irq.c +++ b/shared-core/mach64_irq.c @@ -39,47 +39,48 @@ #include "mach64_drm.h" #include "mach64_drv.h" -irqreturn_t mach64_driver_irq_handler( DRM_IRQ_ARGS ) +irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS) { drm_device_t *dev = (drm_device_t *) arg; - drm_mach64_private_t *dev_priv = - (drm_mach64_private_t *)dev->dev_private; + drm_mach64_private_t *dev_priv = + (drm_mach64_private_t *) dev->dev_private; int status; - status = MACH64_READ( MACH64_CRTC_INT_CNTL ); + status = MACH64_READ(MACH64_CRTC_INT_CNTL); /* VBLANK interrupt */ if (status & MACH64_CRTC_VBLANK_INT) { - /* Mask off all interrupt ack bits before setting the ack bit, since - * there may be other handlers outside the DRM. - * - * NOTE: On mach64, you need to keep the enable bits set when doing - * the ack, despite what the docs say about not acking and enabling - * in a single write. - */ - MACH64_WRITE( MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_INT_ACKS) - | MACH64_CRTC_VBLANK_INT ); - - atomic_inc(&dev->vbl_received); - DRM_WAKEUP(&dev->vbl_queue); - drm_vbl_send_signals( dev ); - return IRQ_HANDLED; + /* Mask off all interrupt ack bits before setting the ack bit, since + * there may be other handlers outside the DRM. + * + * NOTE: On mach64, you need to keep the enable bits set when doing + * the ack, despite what the docs say about not acking and enabling + * in a single write. + */ + MACH64_WRITE(MACH64_CRTC_INT_CNTL, + (status & ~MACH64_CRTC_INT_ACKS) + | MACH64_CRTC_VBLANK_INT); + + atomic_inc(&dev->vbl_received); + DRM_WAKEUP(&dev->vbl_queue); + drm_vbl_send_signals(dev); + return IRQ_HANDLED; } return IRQ_NONE; } -int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +int mach64_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) { unsigned int cur_vblank; int ret = 0; /* Assume that the user has missed the current sequence number * by about a day rather than she wants to wait for years - * using vertical blanks... + * using vertical blanks... */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, - ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - - *sequence ) <= (1<<23) ) ); + DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, + (((cur_vblank = atomic_read(&dev->vbl_received)) + - *sequence) <= (1 << 23))); *sequence = cur_vblank; @@ -88,42 +89,47 @@ int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) /* drm_dma.h hooks */ -void mach64_driver_irq_preinstall( drm_device_t *dev ) { +void mach64_driver_irq_preinstall(drm_device_t * dev) +{ drm_mach64_private_t *dev_priv = - (drm_mach64_private_t *)dev->dev_private; + (drm_mach64_private_t *) dev->dev_private; - u32 status = MACH64_READ( MACH64_CRTC_INT_CNTL ); + u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL); - DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status ); + DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status); - /* Disable and clear VBLANK interrupt */ - MACH64_WRITE( MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_VBLANK_INT_EN) - | MACH64_CRTC_VBLANK_INT ); + /* Disable and clear VBLANK interrupt */ + MACH64_WRITE(MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_VBLANK_INT_EN) + | MACH64_CRTC_VBLANK_INT); } -void mach64_driver_irq_postinstall( drm_device_t *dev ) { +void mach64_driver_irq_postinstall(drm_device_t * dev) +{ drm_mach64_private_t *dev_priv = - (drm_mach64_private_t *)dev->dev_private; + (drm_mach64_private_t *) dev->dev_private; /* Turn on VBLANK interrupt */ - MACH64_WRITE( MACH64_CRTC_INT_CNTL, MACH64_READ( MACH64_CRTC_INT_CNTL ) - | MACH64_CRTC_VBLANK_INT_EN ); + MACH64_WRITE(MACH64_CRTC_INT_CNTL, MACH64_READ(MACH64_CRTC_INT_CNTL) + | MACH64_CRTC_VBLANK_INT_EN); - DRM_DEBUG("after install CRTC_INT_CTNL: 0x%08x\n", MACH64_READ( MACH64_CRTC_INT_CNTL )); + DRM_DEBUG("after install CRTC_INT_CTNL: 0x%08x\n", + MACH64_READ(MACH64_CRTC_INT_CNTL)); } -void mach64_driver_irq_uninstall( drm_device_t *dev ) { +void mach64_driver_irq_uninstall(drm_device_t * dev) +{ drm_mach64_private_t *dev_priv = - (drm_mach64_private_t *)dev->dev_private; - if ( !dev_priv ) + (drm_mach64_private_t *) dev->dev_private; + if (!dev_priv) return; /* Disable and clear VBLANK interrupt */ - MACH64_WRITE( MACH64_CRTC_INT_CNTL, - (MACH64_READ( MACH64_CRTC_INT_CNTL ) & ~MACH64_CRTC_VBLANK_INT_EN) - | MACH64_CRTC_VBLANK_INT ); + MACH64_WRITE(MACH64_CRTC_INT_CNTL, + (MACH64_READ(MACH64_CRTC_INT_CNTL) & + ~MACH64_CRTC_VBLANK_INT_EN) + | MACH64_CRTC_VBLANK_INT); - DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n", - MACH64_READ( MACH64_CRTC_INT_CNTL )); + DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n", + MACH64_READ(MACH64_CRTC_INT_CNTL)); } diff --git a/shared-core/mach64_state.c b/shared-core/mach64_state.c index 127f67d2..2d3c4f61 100644 --- a/shared-core/mach64_state.c +++ b/shared-core/mach64_state.c @@ -34,28 +34,29 @@ #include "mach64_drm.h" #include "mach64_drv.h" - /* ================================================================ * DMA hardware state programming functions */ -static void mach64_print_dirty( const char *msg, unsigned int flags ) +static void mach64_print_dirty(const char *msg, unsigned int flags) { - DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s\n", - msg, - flags, - (flags & MACH64_UPLOAD_DST_OFF_PITCH) ? "dst_off_pitch, " : "", - (flags & MACH64_UPLOAD_Z_ALPHA_CNTL) ? "z_alpha_cntl, " : "", - (flags & MACH64_UPLOAD_SCALE_3D_CNTL) ? "scale_3d_cntl, " : "", - (flags & MACH64_UPLOAD_DP_FOG_CLR) ? "dp_fog_clr, " : "", - (flags & MACH64_UPLOAD_DP_WRITE_MASK) ? "dp_write_mask, " : "", - (flags & MACH64_UPLOAD_DP_PIX_WIDTH) ? "dp_pix_width, " : "", - (flags & MACH64_UPLOAD_SETUP_CNTL) ? "setup_cntl, " : "", - (flags & MACH64_UPLOAD_MISC) ? "misc, " : "", - (flags & MACH64_UPLOAD_TEXTURE) ? "texture, " : "", - (flags & MACH64_UPLOAD_TEX0IMAGE) ? "tex0 image, " : "", - (flags & MACH64_UPLOAD_TEX1IMAGE) ? "tex1 image, " : "", - (flags & MACH64_UPLOAD_CLIPRECTS) ? "cliprects, " : "" ); + DRM_DEBUG("%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s\n", + msg, + flags, + (flags & MACH64_UPLOAD_DST_OFF_PITCH) ? "dst_off_pitch, " : + "", + (flags & MACH64_UPLOAD_Z_ALPHA_CNTL) ? "z_alpha_cntl, " : "", + (flags & MACH64_UPLOAD_SCALE_3D_CNTL) ? "scale_3d_cntl, " : + "", (flags & MACH64_UPLOAD_DP_FOG_CLR) ? "dp_fog_clr, " : "", + (flags & MACH64_UPLOAD_DP_WRITE_MASK) ? "dp_write_mask, " : + "", + (flags & MACH64_UPLOAD_DP_PIX_WIDTH) ? "dp_pix_width, " : "", + (flags & MACH64_UPLOAD_SETUP_CNTL) ? "setup_cntl, " : "", + (flags & MACH64_UPLOAD_MISC) ? "misc, " : "", + (flags & MACH64_UPLOAD_TEXTURE) ? "texture, " : "", + (flags & MACH64_UPLOAD_TEX0IMAGE) ? "tex0 image, " : "", + (flags & MACH64_UPLOAD_TEX1IMAGE) ? "tex1 image, " : "", + (flags & MACH64_UPLOAD_CLIPRECTS) ? "cliprects, " : ""); } /* Mach64 doesn't have hardware cliprects, just one hardware scissor, @@ -64,8 +65,8 @@ static void mach64_print_dirty( const char *msg, unsigned int flags ) /* This function returns 0 on success, 1 for no intersection, and * negative for an error */ -static int mach64_emit_cliprect( DRMFILE filp, drm_mach64_private_t *dev_priv, - drm_clip_rect_t *box ) +static int mach64_emit_cliprect(DRMFILE filp, drm_mach64_private_t * dev_priv, + drm_clip_rect_t * box) { u32 sc_left_right, sc_top_bottom; drm_clip_rect_t scissor; @@ -73,7 +74,7 @@ static int mach64_emit_cliprect( DRMFILE filp, drm_mach64_private_t *dev_priv, drm_mach64_context_regs_t *regs = &sarea_priv->context_state; DMALOCALS; - DRM_DEBUG( "%s: box=%p\n", __FUNCTION__, box ); + DRM_DEBUG("%s: box=%p\n", __FUNCTION__, box); /* Get GL scissor */ /* FIXME: store scissor in SAREA as a cliprect instead of in @@ -85,28 +86,35 @@ static int mach64_emit_cliprect( DRMFILE filp, drm_mach64_private_t *dev_priv, scissor.y2 = (regs->sc_top_bottom & 0xffff0000) >> 16; /* Intersect GL scissor with cliprect */ - if ( box->x1 > scissor.x1 ) scissor.x1 = box->x1; - if ( box->y1 > scissor.y1 ) scissor.y1 = box->y1; - if ( box->x2 < scissor.x2 ) scissor.x2 = box->x2; - if ( box->y2 < scissor.y2 ) scissor.y2 = box->y2; - /* positive return means skip */ - if ( scissor.x1 >= scissor.x2 ) return 1; - if ( scissor.y1 >= scissor.y2 ) return 1; - - DMAGETPTR( filp, dev_priv, 2 ); /* returns on failure to get buffer */ - - sc_left_right = ( (scissor.x1 << 0) | (scissor.x2 << 16) ); - sc_top_bottom = ( (scissor.y1 << 0) | (scissor.y2 << 16) ); - - DMAOUTREG( MACH64_SC_LEFT_RIGHT, sc_left_right ); - DMAOUTREG( MACH64_SC_TOP_BOTTOM, sc_top_bottom ); - - DMAADVANCE( dev_priv, 1 ); + if (box->x1 > scissor.x1) + scissor.x1 = box->x1; + if (box->y1 > scissor.y1) + scissor.y1 = box->y1; + if (box->x2 < scissor.x2) + scissor.x2 = box->x2; + if (box->y2 < scissor.y2) + scissor.y2 = box->y2; + /* positive return means skip */ + if (scissor.x1 >= scissor.x2) + return 1; + if (scissor.y1 >= scissor.y2) + return 1; + + DMAGETPTR(filp, dev_priv, 2); /* returns on failure to get buffer */ + + sc_left_right = ((scissor.x1 << 0) | (scissor.x2 << 16)); + sc_top_bottom = ((scissor.y1 << 0) | (scissor.y2 << 16)); + + DMAOUTREG(MACH64_SC_LEFT_RIGHT, sc_left_right); + DMAOUTREG(MACH64_SC_TOP_BOTTOM, sc_top_bottom); + + DMAADVANCE(dev_priv, 1); return 0; } -static __inline__ int mach64_emit_state( DRMFILE filp, drm_mach64_private_t *dev_priv ) +static __inline__ int mach64_emit_state(DRMFILE filp, + drm_mach64_private_t * dev_priv) { drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mach64_context_regs_t *regs = &sarea_priv->context_state; @@ -114,65 +122,65 @@ static __inline__ int mach64_emit_state( DRMFILE filp, drm_mach64_private_t *dev u32 offset = ((regs->tex_size_pitch & 0xf0) >> 2); DMALOCALS; - if ( MACH64_VERBOSE ) { - mach64_print_dirty( __FUNCTION__, dirty ); + if (MACH64_VERBOSE) { + mach64_print_dirty(__FUNCTION__, dirty); } else { - DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); + DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty); } - DMAGETPTR( filp, dev_priv, 17 ); /* returns on failure to get buffer */ + DMAGETPTR(filp, dev_priv, 17); /* returns on failure to get buffer */ - if ( dirty & MACH64_UPLOAD_MISC ) { - DMAOUTREG( MACH64_DP_MIX, regs->dp_mix ); - DMAOUTREG( MACH64_DP_SRC, regs->dp_src ); - DMAOUTREG( MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl ); - DMAOUTREG( MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl ); + if (dirty & MACH64_UPLOAD_MISC) { + DMAOUTREG(MACH64_DP_MIX, regs->dp_mix); + DMAOUTREG(MACH64_DP_SRC, regs->dp_src); + DMAOUTREG(MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl); + DMAOUTREG(MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl); sarea_priv->dirty &= ~MACH64_UPLOAD_MISC; } - if ( dirty & MACH64_UPLOAD_DST_OFF_PITCH ) { - DMAOUTREG( MACH64_DST_OFF_PITCH, regs->dst_off_pitch ); + if (dirty & MACH64_UPLOAD_DST_OFF_PITCH) { + DMAOUTREG(MACH64_DST_OFF_PITCH, regs->dst_off_pitch); sarea_priv->dirty &= ~MACH64_UPLOAD_DST_OFF_PITCH; } - if ( dirty & MACH64_UPLOAD_Z_OFF_PITCH ) { - DMAOUTREG( MACH64_Z_OFF_PITCH, regs->z_off_pitch ); + if (dirty & MACH64_UPLOAD_Z_OFF_PITCH) { + DMAOUTREG(MACH64_Z_OFF_PITCH, regs->z_off_pitch); sarea_priv->dirty &= ~MACH64_UPLOAD_Z_OFF_PITCH; } - if ( dirty & MACH64_UPLOAD_Z_ALPHA_CNTL ) { - DMAOUTREG( MACH64_Z_CNTL, regs->z_cntl ); - DMAOUTREG( MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl ); + if (dirty & MACH64_UPLOAD_Z_ALPHA_CNTL) { + DMAOUTREG(MACH64_Z_CNTL, regs->z_cntl); + DMAOUTREG(MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl); sarea_priv->dirty &= ~MACH64_UPLOAD_Z_ALPHA_CNTL; } - if ( dirty & MACH64_UPLOAD_SCALE_3D_CNTL ) { - DMAOUTREG( MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl ); + if (dirty & MACH64_UPLOAD_SCALE_3D_CNTL) { + DMAOUTREG(MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl); sarea_priv->dirty &= ~MACH64_UPLOAD_SCALE_3D_CNTL; } - if ( dirty & MACH64_UPLOAD_DP_FOG_CLR ) { - DMAOUTREG( MACH64_DP_FOG_CLR, regs->dp_fog_clr ); + if (dirty & MACH64_UPLOAD_DP_FOG_CLR) { + DMAOUTREG(MACH64_DP_FOG_CLR, regs->dp_fog_clr); sarea_priv->dirty &= ~MACH64_UPLOAD_DP_FOG_CLR; } - if ( dirty & MACH64_UPLOAD_DP_WRITE_MASK ) { - DMAOUTREG( MACH64_DP_WRITE_MASK, regs->dp_write_mask ); + if (dirty & MACH64_UPLOAD_DP_WRITE_MASK) { + DMAOUTREG(MACH64_DP_WRITE_MASK, regs->dp_write_mask); sarea_priv->dirty &= ~MACH64_UPLOAD_DP_WRITE_MASK; } - if ( dirty & MACH64_UPLOAD_DP_PIX_WIDTH ) { - DMAOUTREG( MACH64_DP_PIX_WIDTH, regs->dp_pix_width ); + if (dirty & MACH64_UPLOAD_DP_PIX_WIDTH) { + DMAOUTREG(MACH64_DP_PIX_WIDTH, regs->dp_pix_width); sarea_priv->dirty &= ~MACH64_UPLOAD_DP_PIX_WIDTH; } - if ( dirty & MACH64_UPLOAD_SETUP_CNTL ) { - DMAOUTREG( MACH64_SETUP_CNTL, regs->setup_cntl ); + if (dirty & MACH64_UPLOAD_SETUP_CNTL) { + DMAOUTREG(MACH64_SETUP_CNTL, regs->setup_cntl); sarea_priv->dirty &= ~MACH64_UPLOAD_SETUP_CNTL; } - if ( dirty & MACH64_UPLOAD_TEXTURE ) { - DMAOUTREG( MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch ); - DMAOUTREG( MACH64_TEX_CNTL, regs->tex_cntl ); - DMAOUTREG( MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off ); - DMAOUTREG( MACH64_TEX_0_OFF + offset, regs->tex_offset ); + if (dirty & MACH64_UPLOAD_TEXTURE) { + DMAOUTREG(MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch); + DMAOUTREG(MACH64_TEX_CNTL, regs->tex_cntl); + DMAOUTREG(MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off); + DMAOUTREG(MACH64_TEX_0_OFF + offset, regs->tex_offset); sarea_priv->dirty &= ~MACH64_UPLOAD_TEXTURE; } - DMAADVANCE( dev_priv, 1 ); + DMAADVANCE(dev_priv, 1); sarea_priv->dirty &= MACH64_UPLOAD_CLIPRECTS; @@ -180,16 +188,15 @@ static __inline__ int mach64_emit_state( DRMFILE filp, drm_mach64_private_t *dev } - /* ================================================================ * DMA command dispatch functions */ -static int mach64_dma_dispatch_clear( DRMFILE filp, drm_device_t *dev, - unsigned int flags, - int cx, int cy, int cw, int ch, - unsigned int clear_color, - unsigned int clear_depth ) +static int mach64_dma_dispatch_clear(DRMFILE filp, drm_device_t * dev, + unsigned int flags, + int cx, int cy, int cw, int ch, + unsigned int clear_color, + unsigned int clear_depth) { drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -200,9 +207,9 @@ static int mach64_dma_dispatch_clear( DRMFILE filp, drm_device_t *dev, int i; DMALOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - switch ( dev_priv->fb_bpp ) { + switch (dev_priv->fb_bpp) { case 16: fb_bpp = MACH64_DATATYPE_RGB565; break; @@ -212,7 +219,7 @@ static int mach64_dma_dispatch_clear( DRMFILE filp, drm_device_t *dev, default: return DRM_ERR(EINVAL); } - switch ( dev_priv->depth_bpp ) { + switch (dev_priv->depth_bpp) { case 16: depth_bpp = MACH64_DATATYPE_RGB565; break; @@ -224,118 +231,111 @@ static int mach64_dma_dispatch_clear( DRMFILE filp, drm_device_t *dev, return DRM_ERR(EINVAL); } - if ( !nbox ) + if (!nbox) return 0; - DMAGETPTR( filp, dev_priv, nbox * 31 ); /* returns on failure to get buffer */ + DMAGETPTR(filp, dev_priv, nbox * 31); /* returns on failure to get buffer */ - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; - - DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", - pbox[i].x1, pbox[i].y1, - pbox[i].x2, pbox[i].y2, flags ); - - if ( flags & (MACH64_FRONT | MACH64_BACK) ) { + + DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n", + pbox[i].x1, pbox[i].y1, + pbox[i].x2, pbox[i].y2, flags); + + if (flags & (MACH64_FRONT | MACH64_BACK)) { /* Setup for color buffer clears */ - - DMAOUTREG( MACH64_Z_CNTL, 0 ); - DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 ); - - DMAOUTREG( MACH64_SC_LEFT_RIGHT, ctx->sc_left_right ); - DMAOUTREG( MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom ); - - DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 ); - DMAOUTREG( MACH64_GUI_TRAJ_CNTL, - (MACH64_DST_X_LEFT_TO_RIGHT | - MACH64_DST_Y_TOP_TO_BOTTOM) ); - - DMAOUTREG( MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) | - (fb_bpp << 4) | - (fb_bpp << 8) | - (fb_bpp << 16) | - (fb_bpp << 28)) ); - - DMAOUTREG( MACH64_DP_FRGD_CLR, clear_color ); - DMAOUTREG( MACH64_DP_WRITE_MASK, ctx->dp_write_mask ); - DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D | - MACH64_FRGD_MIX_S) ); - DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR | - MACH64_FRGD_SRC_FRGD_CLR | - MACH64_MONO_SRC_ONE) ); - - + + DMAOUTREG(MACH64_Z_CNTL, 0); + DMAOUTREG(MACH64_SCALE_3D_CNTL, 0); + + DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right); + DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom); + + DMAOUTREG(MACH64_CLR_CMP_CNTL, 0); + DMAOUTREG(MACH64_GUI_TRAJ_CNTL, + (MACH64_DST_X_LEFT_TO_RIGHT | + MACH64_DST_Y_TOP_TO_BOTTOM)); + + DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) | + (fb_bpp << 4) | + (fb_bpp << 8) | + (fb_bpp << 16) | + (fb_bpp << 28))); + + DMAOUTREG(MACH64_DP_FRGD_CLR, clear_color); + DMAOUTREG(MACH64_DP_WRITE_MASK, ctx->dp_write_mask); + DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D | + MACH64_FRGD_MIX_S)); + DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR | + MACH64_FRGD_SRC_FRGD_CLR | + MACH64_MONO_SRC_ONE)); + } - if ( flags & MACH64_FRONT ) { - - DMAOUTREG( MACH64_DST_OFF_PITCH, - dev_priv->front_offset_pitch ); - DMAOUTREG( MACH64_DST_X_Y, - (y << 16) | x ); - DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, - (h << 16) | w ); - + if (flags & MACH64_FRONT) { + + DMAOUTREG(MACH64_DST_OFF_PITCH, + dev_priv->front_offset_pitch); + DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x); + DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w); + } - - if ( flags & MACH64_BACK ) { - - DMAOUTREG( MACH64_DST_OFF_PITCH, - dev_priv->back_offset_pitch ); - DMAOUTREG( MACH64_DST_X_Y, - (y << 16) | x ); - DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, - (h << 16) | w ); - + + if (flags & MACH64_BACK) { + + DMAOUTREG(MACH64_DST_OFF_PITCH, + dev_priv->back_offset_pitch); + DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x); + DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w); + } - - if ( flags & MACH64_DEPTH ) { + + if (flags & MACH64_DEPTH) { /* Setup for depth buffer clear */ - DMAOUTREG( MACH64_Z_CNTL, 0 ); - DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 ); - - DMAOUTREG( MACH64_SC_LEFT_RIGHT, ctx->sc_left_right ); - DMAOUTREG( MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom ); - - DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 ); - DMAOUTREG( MACH64_GUI_TRAJ_CNTL, - (MACH64_DST_X_LEFT_TO_RIGHT | - MACH64_DST_Y_TOP_TO_BOTTOM) ); - - DMAOUTREG( MACH64_DP_PIX_WIDTH, ((depth_bpp << 0) | - (depth_bpp << 4) | - (depth_bpp << 8) | - (depth_bpp << 16) | - (depth_bpp << 28)) ); - - DMAOUTREG( MACH64_DP_FRGD_CLR, clear_depth ); - DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff ); - DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D | - MACH64_FRGD_MIX_S) ); - DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR | - MACH64_FRGD_SRC_FRGD_CLR | - MACH64_MONO_SRC_ONE) ); - - DMAOUTREG( MACH64_DST_OFF_PITCH, - dev_priv->depth_offset_pitch ); - DMAOUTREG( MACH64_DST_X_Y, - (y << 16) | x ); - DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, - (h << 16) | w ); + DMAOUTREG(MACH64_Z_CNTL, 0); + DMAOUTREG(MACH64_SCALE_3D_CNTL, 0); + + DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right); + DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom); + + DMAOUTREG(MACH64_CLR_CMP_CNTL, 0); + DMAOUTREG(MACH64_GUI_TRAJ_CNTL, + (MACH64_DST_X_LEFT_TO_RIGHT | + MACH64_DST_Y_TOP_TO_BOTTOM)); + + DMAOUTREG(MACH64_DP_PIX_WIDTH, ((depth_bpp << 0) | + (depth_bpp << 4) | + (depth_bpp << 8) | + (depth_bpp << 16) | + (depth_bpp << 28))); + + DMAOUTREG(MACH64_DP_FRGD_CLR, clear_depth); + DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff); + DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D | + MACH64_FRGD_MIX_S)); + DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR | + MACH64_FRGD_SRC_FRGD_CLR | + MACH64_MONO_SRC_ONE)); + + DMAOUTREG(MACH64_DST_OFF_PITCH, + dev_priv->depth_offset_pitch); + DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x); + DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w); } } - DMAADVANCE( dev_priv, 1 ); + DMAADVANCE(dev_priv, 1); return 0; } -static int mach64_dma_dispatch_swap( DRMFILE filp, drm_device_t *dev ) +static int mach64_dma_dispatch_swap(DRMFILE filp, drm_device_t * dev) { drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -345,9 +345,9 @@ static int mach64_dma_dispatch_swap( DRMFILE filp, drm_device_t *dev ) int i; DMALOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - switch ( dev_priv->fb_bpp ) { + switch (dev_priv->fb_bpp) { case 16: fb_bpp = MACH64_DATATYPE_RGB565; break; @@ -357,59 +357,55 @@ static int mach64_dma_dispatch_swap( DRMFILE filp, drm_device_t *dev ) break; } - if ( !nbox ) + if (!nbox) return 0; - DMAGETPTR( filp, dev_priv, 13 + nbox * 4 ); /* returns on failure to get buffer */ + DMAGETPTR(filp, dev_priv, 13 + nbox * 4); /* returns on failure to get buffer */ - DMAOUTREG( MACH64_Z_CNTL, 0 ); - DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 ); + DMAOUTREG(MACH64_Z_CNTL, 0); + DMAOUTREG(MACH64_SCALE_3D_CNTL, 0); - DMAOUTREG( MACH64_SC_LEFT_RIGHT, 0 | ( 8191 << 16 ) ); /* no scissor */ - DMAOUTREG( MACH64_SC_TOP_BOTTOM, 0 | ( 16383 << 16 ) ); + DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16)); /* no scissor */ + DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16)); - DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 ); - DMAOUTREG( MACH64_GUI_TRAJ_CNTL, (MACH64_DST_X_LEFT_TO_RIGHT | - MACH64_DST_Y_TOP_TO_BOTTOM) ); + DMAOUTREG(MACH64_CLR_CMP_CNTL, 0); + DMAOUTREG(MACH64_GUI_TRAJ_CNTL, (MACH64_DST_X_LEFT_TO_RIGHT | + MACH64_DST_Y_TOP_TO_BOTTOM)); - DMAOUTREG( MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) | - (fb_bpp << 4) | - (fb_bpp << 8) | - (fb_bpp << 16) | - (fb_bpp << 28)) ); + DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) | + (fb_bpp << 4) | + (fb_bpp << 8) | + (fb_bpp << 16) | (fb_bpp << 28))); - DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff ); - DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D | - MACH64_FRGD_MIX_S) ); - DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_BKGD_CLR | - MACH64_FRGD_SRC_BLIT | - MACH64_MONO_SRC_ONE) ); + DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff); + DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S)); + DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_BKGD_CLR | + MACH64_FRGD_SRC_BLIT | MACH64_MONO_SRC_ONE)); - DMAOUTREG( MACH64_SRC_OFF_PITCH, dev_priv->back_offset_pitch ); - DMAOUTREG( MACH64_DST_OFF_PITCH, dev_priv->front_offset_pitch ); + DMAOUTREG(MACH64_SRC_OFF_PITCH, dev_priv->back_offset_pitch); + DMAOUTREG(MACH64_DST_OFF_PITCH, dev_priv->front_offset_pitch); - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; - DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n", - pbox[i].x1, pbox[i].y1, - pbox[i].x2, pbox[i].y2 ); + DRM_DEBUG("dispatch swap %d,%d-%d,%d\n", + pbox[i].x1, pbox[i].y1, pbox[i].x2, pbox[i].y2); - DMAOUTREG( MACH64_SRC_WIDTH1, w ); - DMAOUTREG( MACH64_SRC_Y_X, (x << 16) | y ); - DMAOUTREG( MACH64_DST_Y_X, (x << 16) | y ); - DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, (h << 16) | w ); + DMAOUTREG(MACH64_SRC_WIDTH1, w); + DMAOUTREG(MACH64_SRC_Y_X, (x << 16) | y); + DMAOUTREG(MACH64_DST_Y_X, (x << 16) | y); + DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w); } - DMAADVANCE( dev_priv, 1 ); + DMAADVANCE(dev_priv, 1); if (dev_priv->driver_mode == MACH64_MODE_DMA_ASYNC) { for (i = 0; i < MACH64_MAX_QUEUED_FRAMES - 1; i++) { - dev_priv->frame_ofs[i] = dev_priv->frame_ofs[i+1]; + dev_priv->frame_ofs[i] = dev_priv->frame_ofs[i + 1]; } dev_priv->frame_ofs[i] = GETRINGOFFSET(); @@ -419,26 +415,26 @@ static int mach64_dma_dispatch_swap( DRMFILE filp, drm_device_t *dev ) return 0; } -static int mach64_do_get_frames_queued( drm_mach64_private_t *dev_priv ) +static int mach64_do_get_frames_queued(drm_mach64_private_t * dev_priv) { drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; int i, start; u32 head, tail, ofs; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); if (sarea_priv->frames_queued == 0) return 0; tail = ring->tail; - mach64_ring_tick( dev_priv, ring ); + mach64_ring_tick(dev_priv, ring); head = ring->head; - start = ( MACH64_MAX_QUEUED_FRAMES - - DRM_MIN(MACH64_MAX_QUEUED_FRAMES, sarea_priv->frames_queued) ); + start = (MACH64_MAX_QUEUED_FRAMES - + DRM_MIN(MACH64_MAX_QUEUED_FRAMES, sarea_priv->frames_queued)); - if ( head == tail ) { + if (head == tail) { sarea_priv->frames_queued = 0; for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) { dev_priv->frame_ofs[i] = ~0; @@ -446,13 +442,14 @@ static int mach64_do_get_frames_queued( drm_mach64_private_t *dev_priv ) return 0; } - for ( i = start; i < MACH64_MAX_QUEUED_FRAMES; i++ ) { + for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) { ofs = dev_priv->frame_ofs[i]; - DRM_DEBUG( "frame_ofs[%d] ofs: %d\n", i, ofs ); - if ( ofs == ~0 || - ( head < tail && (ofs < head || ofs >= tail) ) || - ( head > tail && (ofs < head && ofs >= tail) ) ) { - sarea_priv->frames_queued = (MACH64_MAX_QUEUED_FRAMES - 1) - i; + DRM_DEBUG("frame_ofs[%d] ofs: %d\n", i, ofs); + if (ofs == ~0 || + (head < tail && (ofs < head || ofs >= tail)) || + (head > tail && (ofs < head && ofs >= tail))) { + sarea_priv->frames_queued = + (MACH64_MAX_QUEUED_FRAMES - 1) - i; dev_priv->frame_ofs[i] = ~0; } } @@ -463,22 +460,23 @@ static int mach64_do_get_frames_queued( drm_mach64_private_t *dev_priv ) /* Copy and verify a client submited buffer. * FIXME: Make an assembly optimized version */ -static __inline__ int copy_and_verify_from_user( u32 *to, const u32 *from, unsigned long bytes ) +static __inline__ int copy_and_verify_from_user(u32 * to, const u32 * from, + unsigned long bytes) { - unsigned long n = bytes; /* dwords remaining in buffer */ + unsigned long n = bytes; /* dwords remaining in buffer */ - if ( DRM_VERIFYAREA_READ( from, n ) ) { - DRM_ERROR( "%s: verify_area\n", __FUNCTION__ ); + if (DRM_VERIFYAREA_READ(from, n)) { + DRM_ERROR("%s: verify_area\n", __FUNCTION__); return DRM_ERR(EFAULT); } n >>= 2; - while ( n > 1 ) { + while (n > 1) { u32 data, reg, count; - if ( DRM_GET_USER_UNCHECKED( data, from++ ) ) { - DRM_ERROR( "%s: get_user\n", __FUNCTION__ ); + if (DRM_GET_USER_UNCHECKED(data, from++)) { + DRM_ERROR("%s: get_user\n", __FUNCTION__); return DRM_ERR(EFAULT); } @@ -486,30 +484,34 @@ static __inline__ int copy_and_verify_from_user( u32 *to, const u32 *from, unsig reg = le32_to_cpu(data); count = (reg >> 16) + 1; - if( count <= n ) { + if (count <= n) { n -= count; reg &= 0xffff; /* This is an exact match of Mach64's Setup Engine registers, * excluding SETUP_CNTL (1_C1). */ - if( (reg >= 0x0190 && reg < 0x01c1) || - (reg >= 0x01ca && reg <= 0x01cf) ) { + if ((reg >= 0x0190 && reg < 0x01c1) || + (reg >= 0x01ca && reg <= 0x01cf)) { *to++ = data; - if ( DRM_COPY_FROM_USER_UNCHECKED( to, from, count << 2 ) ) { - DRM_ERROR( "%s: copy_from_user\n", __FUNCTION__ ); + if (DRM_COPY_FROM_USER_UNCHECKED + (to, from, count << 2)) { + DRM_ERROR("%s: copy_from_user\n", + __FUNCTION__); return DRM_ERR(EFAULT); } to += count; } else { - DRM_ERROR( "%s: Got bad command: 0x%04x\n", __FUNCTION__, reg ); + DRM_ERROR("%s: Got bad command: 0x%04x\n", + __FUNCTION__, reg); return DRM_ERR(EACCES); } from += count; } else { - DRM_ERROR( "%s: Got bad command count(=%u) dwords remaining=%lu\n", - __FUNCTION__, count, n ); + DRM_ERROR + ("%s: Got bad command count(=%u) dwords remaining=%lu\n", + __FUNCTION__, count, n); return DRM_ERR(EINVAL); } } @@ -517,13 +519,14 @@ static __inline__ int copy_and_verify_from_user( u32 *to, const u32 *from, unsig if (n == 0) return 0; else { - DRM_ERROR( "%s: Bad buf->used(=%lu)\n", __FUNCTION__, bytes ); + DRM_ERROR("%s: Bad buf->used(=%lu)\n", __FUNCTION__, bytes); return DRM_ERR(EINVAL); } } -static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim, void *buf, - unsigned long used, int discard ) +static int mach64_dma_dispatch_vertex(DRMFILE filp, drm_device_t * dev, + int prim, void *buf, unsigned long used, + int discard) { drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -532,41 +535,45 @@ static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim int verify_ret = 0; DMALOCALS; - DRM_DEBUG( "%s: buf=%p used=%lu nbox=%d\n", - __FUNCTION__, buf, used, sarea_priv->nbox ); + DRM_DEBUG("%s: buf=%p used=%lu nbox=%d\n", + __FUNCTION__, buf, used, sarea_priv->nbox); - if ( used ) { + if (used) { int ret = 0; int i = 0; - copy_buf = mach64_freelist_get( dev_priv ); + copy_buf = mach64_freelist_get(dev_priv); if (copy_buf == NULL) { DRM_ERROR("%s: couldn't get buffer in DMAGETPTR\n", - __FUNCTION__ ); + __FUNCTION__); return DRM_ERR(EAGAIN); } - if ( (verify_ret = - copy_and_verify_from_user( GETBUFPTR( copy_buf ), buf, used )) == 0 ) { + if ((verify_ret = + copy_and_verify_from_user(GETBUFPTR(copy_buf), buf, + used)) == 0) { copy_buf->used = used; - DMASETPTR( copy_buf ); + DMASETPTR(copy_buf); - if ( sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS ) { - ret = mach64_emit_state( filp, dev_priv ); - if (ret < 0) return ret; + if (sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS) { + ret = mach64_emit_state(filp, dev_priv); + if (ret < 0) + return ret; } - + do { /* Emit the next cliprect */ - if ( i < sarea_priv->nbox ) { - ret = mach64_emit_cliprect(filp, dev_priv, - &sarea_priv->boxes[i]); - if ( ret < 0 ) { + if (i < sarea_priv->nbox) { + ret = + mach64_emit_cliprect(filp, dev_priv, + &sarea_priv-> + boxes[i]); + if (ret < 0) { /* failed to get buffer */ return ret; - } else if ( ret != 0 ) { + } else if (ret != 0) { /* null intersection with scissor */ continue; } @@ -575,9 +582,9 @@ static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim done = 1; /* Add the buffer to the DMA queue */ - DMAADVANCE( dev_priv, done ); + DMAADVANCE(dev_priv, done); - } while ( ++i < sarea_priv->nbox ); + } while (++i < sarea_priv->nbox); } if (copy_buf->pending && !done) { @@ -590,10 +597,13 @@ static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim drm_mach64_freelist_t *entry; #if MACH64_EXTRA_CHECKING list_for_each(ptr, &dev_priv->pending) { - entry = list_entry(ptr, drm_mach64_freelist_t, list); + entry = + list_entry(ptr, drm_mach64_freelist_t, + list); if (copy_buf == entry->buf) { - DRM_ERROR( "%s: Trying to release a pending buf\n", - __FUNCTION__ ); + DRM_ERROR + ("%s: Trying to release a pending buf\n", + __FUNCTION__); return DRM_ERR(EFAULT); } } @@ -615,9 +625,8 @@ static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim return verify_ret; } - -static int mach64_dma_dispatch_blit( DRMFILE filp, drm_device_t *dev, - drm_mach64_blit_t *blit ) +static int mach64_dma_dispatch_blit(DRMFILE filp, drm_device_t * dev, + drm_mach64_blit_t * blit) { drm_mach64_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; @@ -629,7 +638,7 @@ static int mach64_dma_dispatch_blit( DRMFILE filp, drm_device_t *dev, * even if the only legal values are powers of two. Thus, we'll * use a shift instead. */ - switch ( blit->format ) { + switch (blit->format) { case MACH64_DATATYPE_ARGB8888: dword_shift = 0; break; @@ -645,84 +654,80 @@ static int mach64_dma_dispatch_blit( DRMFILE filp, drm_device_t *dev, dword_shift = 2; break; default: - DRM_ERROR( "invalid blit format %d\n", blit->format ); + DRM_ERROR("invalid blit format %d\n", blit->format); return DRM_ERR(EINVAL); } /* Dispatch the blit buffer. */ buf = dma->buflist[blit->idx]; - - if ( buf->filp != filp ) { - DRM_ERROR( "process %d (filp %p) using buffer with filp %p\n", - DRM_CURRENTPID, filp, buf->filp ); + + if (buf->filp != filp) { + DRM_ERROR("process %d (filp %p) using buffer with filp %p\n", + DRM_CURRENTPID, filp, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", blit->idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", blit->idx); return DRM_ERR(EINVAL); } - /* Set buf->used to the bytes of blit data based on the blit dimensions - * and verify the size. When the setup is emitted to the buffer with - * the DMA* macros below, buf->used is incremented to include the bytes + /* Set buf->used to the bytes of blit data based on the blit dimensions + * and verify the size. When the setup is emitted to the buffer with + * the DMA* macros below, buf->used is incremented to include the bytes * used for setup as well as the blit data. */ - dwords = (blit->width * blit->height) >> dword_shift; + dwords = (blit->width * blit->height) >> dword_shift; buf->used = dwords << 2; - if ( buf->used <= 0 || - buf->used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET ) { - DRM_ERROR( "Invalid blit size: %d bytes\n", buf->used ); + if (buf->used <= 0 || + buf->used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET) { + DRM_ERROR("Invalid blit size: %d bytes\n", buf->used); return DRM_ERR(EINVAL); } /* FIXME: Use a last buffer flag and reduce the state emitted for subsequent, - * continuation buffers? + * continuation buffers? */ /* Blit via BM_HOSTDATA (gui-master) - like HOST_DATA[0-15], but doesn't require - * a register command every 16 dwords. State setup is added at the start of the + * a register command every 16 dwords. State setup is added at the start of the * buffer -- the client leaves space for this based on MACH64_HOSTDATA_BLIT_OFFSET */ - DMASETPTR( buf ); - - DMAOUTREG( MACH64_Z_CNTL, 0 ); - DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 ); - - DMAOUTREG( MACH64_SC_LEFT_RIGHT, 0 | ( 8191 << 16 ) ); /* no scissor */ - DMAOUTREG( MACH64_SC_TOP_BOTTOM, 0 | ( 16383 << 16 ) ); - - DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 ); /* disable */ - DMAOUTREG( MACH64_GUI_TRAJ_CNTL, - MACH64_DST_X_LEFT_TO_RIGHT - | MACH64_DST_Y_TOP_TO_BOTTOM ); - - DMAOUTREG( MACH64_DP_PIX_WIDTH, - ( blit->format << 0 ) /* dst pix width */ - | ( blit->format << 4 ) /* composite pix width */ - | ( blit->format << 8 ) /* src pix width */ - | ( blit->format << 16 ) /* host data pix width */ - | ( blit->format << 28 ) /* scaler/3D pix width */ - ); - - DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff ); /* enable all planes */ - DMAOUTREG( MACH64_DP_MIX, - MACH64_BKGD_MIX_D - | MACH64_FRGD_MIX_S ); - DMAOUTREG( MACH64_DP_SRC, - MACH64_BKGD_SRC_BKGD_CLR - | MACH64_FRGD_SRC_HOST - | MACH64_MONO_SRC_ONE ); - - DMAOUTREG( MACH64_DST_OFF_PITCH, (blit->pitch << 22) | (blit->offset >> 3) ); - DMAOUTREG( MACH64_DST_X_Y, (blit->y << 16) | blit->x ); - DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, (blit->height << 16) | blit->width ); - - DRM_DEBUG( "%s: %d bytes\n", __FUNCTION__, buf->used ); + DMASETPTR(buf); + + DMAOUTREG(MACH64_Z_CNTL, 0); + DMAOUTREG(MACH64_SCALE_3D_CNTL, 0); + + DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16)); /* no scissor */ + DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16)); + + DMAOUTREG(MACH64_CLR_CMP_CNTL, 0); /* disable */ + DMAOUTREG(MACH64_GUI_TRAJ_CNTL, + MACH64_DST_X_LEFT_TO_RIGHT | MACH64_DST_Y_TOP_TO_BOTTOM); + + DMAOUTREG(MACH64_DP_PIX_WIDTH, (blit->format << 0) /* dst pix width */ + |(blit->format << 4) /* composite pix width */ + |(blit->format << 8) /* src pix width */ + |(blit->format << 16) /* host data pix width */ + |(blit->format << 28) /* scaler/3D pix width */ + ); + + DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff); /* enable all planes */ + DMAOUTREG(MACH64_DP_MIX, MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S); + DMAOUTREG(MACH64_DP_SRC, + MACH64_BKGD_SRC_BKGD_CLR + | MACH64_FRGD_SRC_HOST | MACH64_MONO_SRC_ONE); + + DMAOUTREG(MACH64_DST_OFF_PITCH, + (blit->pitch << 22) | (blit->offset >> 3)); + DMAOUTREG(MACH64_DST_X_Y, (blit->y << 16) | blit->x); + DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (blit->height << 16) | blit->width); + + DRM_DEBUG("%s: %d bytes\n", __FUNCTION__, buf->used); /* Add the buffer to the queue */ - DMAADVANCEHOSTDATA( dev_priv ); + DMAADVANCEHOSTDATA(dev_priv); return 0; } @@ -731,7 +736,7 @@ static int mach64_dma_dispatch_blit( DRMFILE filp, drm_device_t *dev, * IOCTL functions */ -int mach64_dma_clear( DRM_IOCTL_ARGS ) +int mach64_dma_clear(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; @@ -739,90 +744,88 @@ int mach64_dma_clear( DRM_IOCTL_ARGS ) drm_mach64_clear_t clear; int ret; - DRM_DEBUG( "%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID ); + DRM_DEBUG("%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID); + + LOCK_TEST_WITH_RETURN(dev, filp); - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( clear, (drm_mach64_clear_t *)data, - sizeof(clear) ); - - if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS ) + DRM_COPY_FROM_USER_IOCTL(clear, (drm_mach64_clear_t *) data, + sizeof(clear)); + + if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - ret = mach64_dma_dispatch_clear( filp, dev, clear.flags, - clear.x, clear.y, clear.w, clear.h, - clear.clear_color, clear.clear_depth ); + ret = mach64_dma_dispatch_clear(filp, dev, clear.flags, + clear.x, clear.y, clear.w, clear.h, + clear.clear_color, clear.clear_depth); /* Make sure we restore the 3D state next time. */ - sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | - MACH64_UPLOAD_MISC); + sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC); return ret; } -int mach64_dma_swap( DRM_IOCTL_ARGS ) +int mach64_dma_swap(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; int ret; - DRM_DEBUG( "%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID ); + DRM_DEBUG("%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID); - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS ) + LOCK_TEST_WITH_RETURN(dev, filp); + + if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - ret = mach64_dma_dispatch_swap( filp, dev ); + ret = mach64_dma_dispatch_swap(filp, dev); /* Make sure we restore the 3D state next time. */ - sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | - MACH64_UPLOAD_MISC); + sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC); return ret; } -int mach64_dma_vertex( DRM_IOCTL_ARGS ) +int mach64_dma_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mach64_vertex_t vertex; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( vertex, (drm_mach64_vertex_t *)data, - sizeof(vertex) ); + DRM_COPY_FROM_USER_IOCTL(vertex, (drm_mach64_vertex_t *) data, + sizeof(vertex)); - DRM_DEBUG( "%s: pid=%d buf=%p used=%lu discard=%d\n", - __FUNCTION__, DRM_CURRENTPID, - vertex.buf, vertex.used, vertex.discard ); + DRM_DEBUG("%s: pid=%d buf=%p used=%lu discard=%d\n", + __FUNCTION__, DRM_CURRENTPID, + vertex.buf, vertex.used, vertex.discard); - if ( vertex.prim < 0 || - vertex.prim > MACH64_PRIM_POLYGON ) { - DRM_ERROR( "buffer prim %d\n", vertex.prim ); + if (vertex.prim < 0 || vertex.prim > MACH64_PRIM_POLYGON) { + DRM_ERROR("buffer prim %d\n", vertex.prim); return DRM_ERR(EINVAL); } - if ( vertex.used > MACH64_BUFFER_SIZE || (vertex.used & 3) != 0) { - DRM_ERROR( "Invalid vertex buffer size: %lu bytes\n", vertex.used ); + if (vertex.used > MACH64_BUFFER_SIZE || (vertex.used & 3) != 0) { + DRM_ERROR("Invalid vertex buffer size: %lu bytes\n", + vertex.used); return DRM_ERR(EINVAL); } - if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - return mach64_dma_dispatch_vertex( filp, dev, vertex.prim, vertex.buf, - vertex.used, vertex.discard ); + return mach64_dma_dispatch_vertex(filp, dev, vertex.prim, vertex.buf, + vertex.used, vertex.discard); } -int mach64_dma_blit( DRM_IOCTL_ARGS ) +int mach64_dma_blit(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; @@ -831,53 +834,52 @@ int mach64_dma_blit( DRM_IOCTL_ARGS ) drm_mach64_blit_t blit; int ret; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( blit, (drm_mach64_blit_t *)data, - sizeof(blit) ); + DRM_COPY_FROM_USER_IOCTL(blit, (drm_mach64_blit_t *) data, + sizeof(blit)); - DRM_DEBUG( "%s: pid=%d index=%d\n", - __FUNCTION__, DRM_CURRENTPID, blit.idx ); + DRM_DEBUG("%s: pid=%d index=%d\n", + __FUNCTION__, DRM_CURRENTPID, blit.idx); - if ( blit.idx < 0 || blit.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - blit.idx, dma->buf_count - 1 ); + if (blit.idx < 0 || blit.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + blit.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - ret = mach64_dma_dispatch_blit( filp, dev, &blit ); + ret = mach64_dma_dispatch_blit(filp, dev, &blit); /* Make sure we restore the 3D state next time. */ sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | - MACH64_UPLOAD_MISC | - MACH64_UPLOAD_CLIPRECTS); + MACH64_UPLOAD_MISC | MACH64_UPLOAD_CLIPRECTS); return ret; } -int mach64_get_param( DRM_IOCTL_ARGS ) +int mach64_get_param(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_getparam_t param; int value; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( param, (drm_mach64_getparam_t *)data, - sizeof(param) ); + DRM_COPY_FROM_USER_IOCTL(param, (drm_mach64_getparam_t *) data, + sizeof(param)); - switch ( param.param ) { + switch (param.param) { case MACH64_PARAM_FRAMES_QUEUED: /* Needs lock since it calls mach64_ring_tick() */ - LOCK_TEST_WITH_RETURN( dev, filp ); - value = mach64_do_get_frames_queued( dev_priv ); + LOCK_TEST_WITH_RETURN(dev, filp); + value = mach64_do_get_frames_queued(dev_priv); break; case MACH64_PARAM_IRQ_NR: value = dev->irq; @@ -886,8 +888,8 @@ int mach64_get_param( DRM_IOCTL_ARGS ) return DRM_ERR(EINVAL); } - if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } diff --git a/shared-core/mga_dma.c b/shared-core/mga_dma.c index 896787be..57f4e1c3 100644 --- a/shared-core/mga_dma.c +++ b/shared-core/mga_dma.c @@ -41,57 +41,57 @@ #define MGA_DEFAULT_USEC_TIMEOUT 10000 #define MGA_FREELIST_DEBUG 0 - /* ================================================================ * Engine control */ -int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ) +int mga_do_wait_for_idle(drm_mga_private_t * dev_priv) { u32 status = 0; int i; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; - if ( status == MGA_ENDPRDMASTS ) { - MGA_WRITE8( MGA_CRTC_INDEX, 0 ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; + if (status == MGA_ENDPRDMASTS) { + MGA_WRITE8(MGA_CRTC_INDEX, 0); return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if MGA_DMA_DEBUG - DRM_ERROR( "failed!\n" ); - DRM_INFO( " status=0x%08x\n", status ); + DRM_ERROR("failed!\n"); + DRM_INFO(" status=0x%08x\n", status); #endif return DRM_ERR(EBUSY); } -int mga_do_dma_idle( drm_mga_private_t *dev_priv ) +int mga_do_dma_idle(drm_mga_private_t * dev_priv) { u32 status = 0; int i; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - status = MGA_READ( MGA_STATUS ) & MGA_DMA_IDLE_MASK; - if ( status == MGA_ENDPRDMASTS ) return 0; - DRM_UDELAY( 1 ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + status = MGA_READ(MGA_STATUS) & MGA_DMA_IDLE_MASK; + if (status == MGA_ENDPRDMASTS) + return 0; + DRM_UDELAY(1); } #if MGA_DMA_DEBUG - DRM_ERROR( "failed! status=0x%08x\n", status ); + DRM_ERROR("failed! status=0x%08x\n", status); #endif return DRM_ERR(EBUSY); } -int mga_do_dma_reset( drm_mga_private_t *dev_priv ) +int mga_do_dma_reset(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_primary_buffer_t *primary = &dev_priv->prim; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* The primary DMA stream should look like new right about now. */ @@ -110,16 +110,16 @@ int mga_do_dma_reset( drm_mga_private_t *dev_priv ) return 0; } -int mga_do_engine_reset( drm_mga_private_t *dev_priv ) +int mga_do_engine_reset(drm_mga_private_t * dev_priv) { - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* Okay, so we've completely screwed up and locked the engine. * How about we clean up after ourselves? */ - MGA_WRITE( MGA_RST, MGA_SOFTRESET ); - DRM_UDELAY( 15 ); /* Wait at least 10 usecs */ - MGA_WRITE( MGA_RST, 0 ); + MGA_WRITE(MGA_RST, MGA_SOFTRESET); + DRM_UDELAY(15); /* Wait at least 10 usecs */ + MGA_WRITE(MGA_RST, 0); /* Initialize the registers that get clobbered by the soft * reset. Many of the core register values survive a reset, @@ -129,47 +129,46 @@ int mga_do_engine_reset( drm_mga_private_t *dev_priv ) * server should reset the engine state to known values. */ #if 0 - MGA_WRITE( MGA_PRIMPTR, - virt_to_bus((void *)dev_priv->prim.status_page) | - MGA_PRIMPTREN0 | - MGA_PRIMPTREN1 ); + MGA_WRITE(MGA_PRIMPTR, + virt_to_bus((void *)dev_priv->prim.status_page) | + MGA_PRIMPTREN0 | MGA_PRIMPTREN1); #endif - MGA_WRITE( MGA_ICLEAR, MGA_SOFTRAPICLR ); - MGA_WRITE( MGA_IEN, MGA_SOFTRAPIEN ); + MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR); + MGA_WRITE(MGA_IEN, MGA_SOFTRAPIEN); /* The primary DMA stream should look like new right about now. */ - mga_do_dma_reset( dev_priv ); + mga_do_dma_reset(dev_priv); /* This bad boy will never fail. */ return 0; } - /* ================================================================ * Primary DMA stream */ -void mga_do_dma_flush( drm_mga_private_t *dev_priv ) +void mga_do_dma_flush(drm_mga_private_t * dev_priv) { drm_mga_primary_buffer_t *primary = &dev_priv->prim; u32 head, tail; u32 status = 0; int i; - DMA_LOCALS; - DRM_DEBUG( "\n" ); - - /* We need to wait so that we can do an safe flush */ - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; - if ( status == MGA_ENDPRDMASTS ) break; - DRM_UDELAY( 1 ); + DMA_LOCALS; + DRM_DEBUG("\n"); + + /* We need to wait so that we can do an safe flush */ + for (i = 0; i < dev_priv->usec_timeout; i++) { + status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; + if (status == MGA_ENDPRDMASTS) + break; + DRM_UDELAY(1); } - if ( primary->tail == primary->last_flush ) { - DRM_DEBUG( " bailing out...\n" ); + if (primary->tail == primary->last_flush) { + DRM_DEBUG(" bailing out...\n"); return; } @@ -179,48 +178,46 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv ) * actually (partially?) reads the first of these commands. * See page 4-16 in the G400 manual, middle of the page or so. */ - BEGIN_DMA( 1 ); + BEGIN_DMA(1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); ADVANCE_DMA(); primary->last_flush = primary->tail; - head = MGA_READ( MGA_PRIMADDRESS ); + head = MGA_READ(MGA_PRIMADDRESS); - if ( head <= tail ) { + if (head <= tail) { primary->space = primary->size - primary->tail; } else { primary->space = head - tail; } - DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset ); - DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset ); - DRM_DEBUG( " space = 0x%06x\n", primary->space ); + DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); + DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset); + DRM_DEBUG(" space = 0x%06x\n", primary->space); mga_flush_write_combine(); - MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER ); + MGA_WRITE(MGA_PRIMEND, tail | MGA_PAGPXFER); - DRM_DEBUG( "done.\n" ); + DRM_DEBUG("done.\n"); } -void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ) +void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv) { drm_mga_primary_buffer_t *primary = &dev_priv->prim; u32 head, tail; DMA_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); BEGIN_DMA_WRAP(); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); ADVANCE_DMA(); @@ -230,45 +227,43 @@ void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ) primary->last_flush = 0; primary->last_wrap++; - head = MGA_READ( MGA_PRIMADDRESS ); + head = MGA_READ(MGA_PRIMADDRESS); - if ( head == dev_priv->primary->offset ) { + if (head == dev_priv->primary->offset) { primary->space = primary->size; } else { primary->space = head - dev_priv->primary->offset; } - DRM_DEBUG( " head = 0x%06lx\n", - head - dev_priv->primary->offset ); - DRM_DEBUG( " tail = 0x%06x\n", primary->tail ); - DRM_DEBUG( " wrap = %d\n", primary->last_wrap ); - DRM_DEBUG( " space = 0x%06x\n", primary->space ); + DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); + DRM_DEBUG(" tail = 0x%06x\n", primary->tail); + DRM_DEBUG(" wrap = %d\n", primary->last_wrap); + DRM_DEBUG(" space = 0x%06x\n", primary->space); mga_flush_write_combine(); - MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER ); + MGA_WRITE(MGA_PRIMEND, tail | MGA_PAGPXFER); - set_bit( 0, &primary->wrapped ); - DRM_DEBUG( "done.\n" ); + set_bit(0, &primary->wrapped); + DRM_DEBUG("done.\n"); } -void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ) +void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv) { drm_mga_primary_buffer_t *primary = &dev_priv->prim; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; u32 head = dev_priv->primary->offset; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); sarea_priv->last_wrap++; - DRM_DEBUG( " wrap = %d\n", sarea_priv->last_wrap ); + DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap); mga_flush_write_combine(); - MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL ); + MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL); - clear_bit( 0, &primary->wrapped ); - DRM_DEBUG( "done.\n" ); + clear_bit(0, &primary->wrapped); + DRM_DEBUG("done.\n"); } - /* ================================================================ * Freelist management */ @@ -277,63 +272,61 @@ void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ) #define MGA_BUFFER_FREE 0 #if MGA_FREELIST_DEBUG -static void mga_freelist_print( drm_device_t *dev ) +static void mga_freelist_print(drm_device_t * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_freelist_t *entry; - DRM_INFO( "\n" ); - DRM_INFO( "current dispatch: last=0x%x done=0x%x\n", - dev_priv->sarea_priv->last_dispatch, - (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) - - dev_priv->primary->offset) ); - DRM_INFO( "current freelist:\n" ); - - for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) { - DRM_INFO( " %p idx=%2d age=0x%x 0x%06lx\n", - entry, entry->buf->idx, entry->age.head, - entry->age.head - dev_priv->primary->offset ); + DRM_INFO("\n"); + DRM_INFO("current dispatch: last=0x%x done=0x%x\n", + dev_priv->sarea_priv->last_dispatch, + (unsigned int)(MGA_READ(MGA_PRIMADDRESS) - + dev_priv->primary->offset)); + DRM_INFO("current freelist:\n"); + + for (entry = dev_priv->head->next; entry; entry = entry->next) { + DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n", + entry, entry->buf->idx, entry->age.head, + entry->age.head - dev_priv->primary->offset); } - DRM_INFO( "\n" ); + DRM_INFO("\n"); } #endif -static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv ) +static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv) { drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_freelist_t *entry; int i; - DRM_DEBUG( "count=%d\n", dma->buf_count ); + DRM_DEBUG("count=%d\n", dma->buf_count); - dev_priv->head = drm_alloc( sizeof(drm_mga_freelist_t), - DRM_MEM_DRIVER ); - if ( dev_priv->head == NULL ) + dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); + if (dev_priv->head == NULL) return DRM_ERR(ENOMEM); - memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) ); - SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 ); + memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t)); + SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0); - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { buf = dma->buflist[i]; - buf_priv = buf->dev_private; + buf_priv = buf->dev_private; - entry = drm_alloc( sizeof(drm_mga_freelist_t), - DRM_MEM_DRIVER ); - if ( entry == NULL ) + entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); + if (entry == NULL) return DRM_ERR(ENOMEM); - memset( entry, 0, sizeof(drm_mga_freelist_t) ); + memset(entry, 0, sizeof(drm_mga_freelist_t)); entry->next = dev_priv->head->next; entry->prev = dev_priv->head; - SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); + SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); entry->buf = buf; - if ( dev_priv->head->next != NULL ) + if (dev_priv->head->next != NULL) dev_priv->head->next->prev = entry; - if ( entry->next == NULL ) + if (entry->next == NULL) dev_priv->tail = entry; buf_priv->list_entry = entry; @@ -346,17 +339,17 @@ static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv ) return 0; } -static void mga_freelist_cleanup( drm_device_t *dev ) +static void mga_freelist_cleanup(drm_device_t * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_freelist_t *entry; drm_mga_freelist_t *next; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); entry = dev_priv->head; - while ( entry ) { + while (entry) { next = entry->next; - drm_free( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER ); + drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); entry = next; } @@ -366,71 +359,69 @@ static void mga_freelist_cleanup( drm_device_t *dev ) #if 0 /* FIXME: Still needed? */ -static void mga_freelist_reset( drm_device_t *dev ) +static void mga_freelist_reset(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; int i; - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { buf = dma->buflist[i]; - buf_priv = buf->dev_private; - SET_AGE( &buf_priv->list_entry->age, - MGA_BUFFER_FREE, 0 ); + buf_priv = buf->dev_private; + SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0); } } #endif -static drm_buf_t *mga_freelist_get( drm_device_t *dev ) +static drm_buf_t *mga_freelist_get(drm_device_t * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_freelist_t *next; drm_mga_freelist_t *prev; drm_mga_freelist_t *tail = dev_priv->tail; u32 head, wrap; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - head = MGA_READ( MGA_PRIMADDRESS ); + head = MGA_READ(MGA_PRIMADDRESS); wrap = dev_priv->sarea_priv->last_wrap; - DRM_DEBUG( " tail=0x%06lx %d\n", - tail->age.head ? - tail->age.head - dev_priv->primary->offset : 0, - tail->age.wrap ); - DRM_DEBUG( " head=0x%06lx %d\n", - head - dev_priv->primary->offset, wrap ); + DRM_DEBUG(" tail=0x%06lx %d\n", + tail->age.head ? + tail->age.head - dev_priv->primary->offset : 0, + tail->age.wrap); + DRM_DEBUG(" head=0x%06lx %d\n", + head - dev_priv->primary->offset, wrap); - if ( TEST_AGE( &tail->age, head, wrap ) ) { + if (TEST_AGE(&tail->age, head, wrap)) { prev = dev_priv->tail->prev; next = dev_priv->tail; prev->next = NULL; next->prev = next->next = NULL; dev_priv->tail = prev; - SET_AGE( &next->age, MGA_BUFFER_USED, 0 ); + SET_AGE(&next->age, MGA_BUFFER_USED, 0); return next->buf; } - DRM_DEBUG( "returning NULL!\n" ); + DRM_DEBUG("returning NULL!\n"); return NULL; } -int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ) +int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; drm_mga_freelist_t *head, *entry, *prev; - DRM_DEBUG( "age=0x%06lx wrap=%d\n", - buf_priv->list_entry->age.head - - dev_priv->primary->offset, - buf_priv->list_entry->age.wrap ); + DRM_DEBUG("age=0x%06lx wrap=%d\n", + buf_priv->list_entry->age.head - + dev_priv->primary->offset, buf_priv->list_entry->age.wrap); entry = buf_priv->list_entry; head = dev_priv->head; - if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) { - SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); + if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) { + SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); prev = dev_priv->tail; prev->next = entry; entry->prev = prev; @@ -446,43 +437,42 @@ int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ) return 0; } - /* ================================================================ * DMA initialization, cleanup */ -static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) +static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init) { drm_mga_private_t *dev_priv; int ret; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - dev_priv = drm_alloc( sizeof(drm_mga_private_t), DRM_MEM_DRIVER ); - if ( !dev_priv ) + dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); + if (!dev_priv) return DRM_ERR(ENOMEM); - memset( dev_priv, 0, sizeof(drm_mga_private_t) ); + memset(dev_priv, 0, sizeof(drm_mga_private_t)); dev_priv->chipset = init->chipset; dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT; - if ( init->sgram ) { + if (init->sgram) { dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK; } else { dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; } - dev_priv->maccess = init->maccess; + dev_priv->maccess = init->maccess; - dev_priv->fb_cpp = init->fb_cpp; - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; + dev_priv->fb_cpp = init->fb_cpp; + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; - dev_priv->depth_cpp = init->depth_cpp; - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; + dev_priv->depth_cpp = init->depth_cpp; + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; /* FIXME: Need to support AGP textures... */ @@ -491,108 +481,104 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) DRM_GETSAREA(); - if(!dev_priv->sarea) { - DRM_ERROR( "failed to find sarea!\n" ); + if (!dev_priv->sarea) { + DRM_ERROR("failed to find sarea!\n"); /* Assign dev_private so we can do cleanup. */ dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); return DRM_ERR(EINVAL); } dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if(!dev_priv->mmio) { - DRM_ERROR( "failed to find mmio region!\n" ); + if (!dev_priv->mmio) { + DRM_ERROR("failed to find mmio region!\n"); /* Assign dev_private so we can do cleanup. */ dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); return DRM_ERR(EINVAL); } dev_priv->status = drm_core_findmap(dev, init->status_offset); - if(!dev_priv->status) { - DRM_ERROR( "failed to find status page!\n" ); + if (!dev_priv->status) { + DRM_ERROR("failed to find status page!\n"); /* Assign dev_private so we can do cleanup. */ dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); return DRM_ERR(EINVAL); } dev_priv->warp = drm_core_findmap(dev, init->warp_offset); - if(!dev_priv->warp) { - DRM_ERROR( "failed to find warp microcode region!\n" ); + if (!dev_priv->warp) { + DRM_ERROR("failed to find warp microcode region!\n"); /* Assign dev_private so we can do cleanup. */ dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); return DRM_ERR(EINVAL); } dev_priv->primary = drm_core_findmap(dev, init->primary_offset); - if(!dev_priv->primary) { - DRM_ERROR( "failed to find primary dma region!\n" ); + if (!dev_priv->primary) { + DRM_ERROR("failed to find primary dma region!\n"); /* Assign dev_private so we can do cleanup. */ dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); return DRM_ERR(EINVAL); } dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if(!dev->agp_buffer_map) { - DRM_ERROR( "failed to find dma buffer region!\n" ); + if (!dev->agp_buffer_map) { + DRM_ERROR("failed to find dma buffer region!\n"); /* Assign dev_private so we can do cleanup. */ dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); return DRM_ERR(EINVAL); } dev_priv->sarea_priv = - (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); + (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle + + init->sarea_priv_offset); - drm_core_ioremap( dev_priv->warp, dev ); - drm_core_ioremap( dev_priv->primary, dev ); - drm_core_ioremap( dev->agp_buffer_map, dev ); + drm_core_ioremap(dev_priv->warp, dev); + drm_core_ioremap(dev_priv->primary, dev); + drm_core_ioremap(dev->agp_buffer_map, dev); - if(!dev_priv->warp->handle || - !dev_priv->primary->handle || - !dev->agp_buffer_map->handle ) { - DRM_ERROR( "failed to ioremap agp regions!\n" ); + if (!dev_priv->warp->handle || + !dev_priv->primary->handle || !dev->agp_buffer_map->handle) { + DRM_ERROR("failed to ioremap agp regions!\n"); /* Assign dev_private so we can do cleanup. */ dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); return DRM_ERR(ENOMEM); } - ret = mga_warp_install_microcode( dev_priv ); - if ( ret < 0 ) { - DRM_ERROR( "failed to install WARP ucode!\n" ); + ret = mga_warp_install_microcode(dev_priv); + if (ret < 0) { + DRM_ERROR("failed to install WARP ucode!\n"); /* Assign dev_private so we can do cleanup. */ dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); return ret; } - ret = mga_warp_init( dev_priv ); - if ( ret < 0 ) { - DRM_ERROR( "failed to init WARP engine!\n" ); + ret = mga_warp_init(dev_priv); + if (ret < 0) { + DRM_ERROR("failed to init WARP engine!\n"); /* Assign dev_private so we can do cleanup. */ dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); return ret; } - dev_priv->prim.status = (u32 *)dev_priv->status->handle; + dev_priv->prim.status = (u32 *) dev_priv->status->handle; - mga_do_wait_for_idle( dev_priv ); + mga_do_wait_for_idle(dev_priv); /* Init the primary DMA registers. */ - MGA_WRITE( MGA_PRIMADDRESS, - dev_priv->primary->offset | MGA_DMA_GENERAL ); + MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL); #if 0 - MGA_WRITE( MGA_PRIMPTR, - virt_to_bus((void *)dev_priv->prim.status) | - MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */ - MGA_PRIMPTREN1 ); /* DWGSYNC */ + MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */ + MGA_PRIMPTREN1); /* DWGSYNC */ #endif - dev_priv->prim.start = (u8 *)dev_priv->primary->handle; - dev_priv->prim.end = ((u8 *)dev_priv->primary->handle + dev_priv->prim.start = (u8 *) dev_priv->primary->handle; + dev_priv->prim.end = ((u8 *) dev_priv->primary->handle + dev_priv->primary->size); dev_priv->prim.size = dev_priv->primary->size; @@ -612,11 +598,11 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) dev_priv->sarea_priv->last_frame.head = 0; dev_priv->sarea_priv->last_frame.wrap = 0; - if ( mga_freelist_init( dev, dev_priv ) < 0 ) { - DRM_ERROR( "could not initialize freelist\n" ); + if (mga_freelist_init(dev, dev_priv) < 0) { + DRM_ERROR("could not initialize freelist\n"); /* Assign dev_private so we can do cleanup. */ dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); return DRM_ERR(ENOMEM); } @@ -625,131 +611,132 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) return 0; } -int mga_do_cleanup_dma( drm_device_t *dev ) +int mga_do_cleanup_dma(drm_device_t * dev) { - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private * is freed, it's too late. */ - if ( dev->irq_enabled ) drm_irq_uninstall(dev); + if (dev->irq_enabled) + drm_irq_uninstall(dev); - if ( dev->dev_private ) { + if (dev->dev_private) { drm_mga_private_t *dev_priv = dev->dev_private; - if ( dev_priv->warp != NULL ) - drm_core_ioremapfree( dev_priv->warp, dev ); - if ( dev_priv->primary != NULL ) - drm_core_ioremapfree( dev_priv->primary, dev ); - if ( dev->agp_buffer_map != NULL ) { - drm_core_ioremapfree( dev->agp_buffer_map, dev ); + if (dev_priv->warp != NULL) + drm_core_ioremapfree(dev_priv->warp, dev); + if (dev_priv->primary != NULL) + drm_core_ioremapfree(dev_priv->primary, dev); + if (dev->agp_buffer_map != NULL) { + drm_core_ioremapfree(dev->agp_buffer_map, dev); dev->agp_buffer_map = NULL; } - if ( dev_priv->head != NULL ) { - mga_freelist_cleanup( dev ); + if (dev_priv->head != NULL) { + mga_freelist_cleanup(dev); } - drm_free( dev->dev_private, sizeof(drm_mga_private_t), - DRM_MEM_DRIVER ); + drm_free(dev->dev_private, sizeof(drm_mga_private_t), + DRM_MEM_DRIVER); dev->dev_private = NULL; } return 0; } -int mga_dma_init( DRM_IOCTL_ARGS ) +int mga_dma_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_init_t init; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( init, (drm_mga_init_t __user *)data, sizeof(init) ); + DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data, + sizeof(init)); - switch ( init.func ) { + switch (init.func) { case MGA_INIT_DMA: - return mga_do_init_dma( dev, &init ); + return mga_do_init_dma(dev, &init); case MGA_CLEANUP_DMA: - return mga_do_cleanup_dma( dev ); + return mga_do_cleanup_dma(dev); } return DRM_ERR(EINVAL); } - /* ================================================================ * Primary DMA stream management */ -int mga_dma_flush( DRM_IOCTL_ARGS ) +int mga_dma_flush(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; drm_lock_t lock; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( lock, (drm_lock_t __user *)data, sizeof(lock) ); + DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data, + sizeof(lock)); - DRM_DEBUG( "%s%s%s\n", - (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", - (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", - (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" ); + DRM_DEBUG("%s%s%s\n", + (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", + (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", + (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : ""); - WRAP_WAIT_WITH_RETURN( dev_priv ); + WRAP_WAIT_WITH_RETURN(dev_priv); - if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) { - mga_do_dma_flush( dev_priv ); + if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) { + mga_do_dma_flush(dev_priv); } - if ( lock.flags & _DRM_LOCK_QUIESCENT ) { + if (lock.flags & _DRM_LOCK_QUIESCENT) { #if MGA_DMA_DEBUG - int ret = mga_do_wait_for_idle( dev_priv ); - if ( ret < 0 ) - DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); + int ret = mga_do_wait_for_idle(dev_priv); + if (ret < 0) + DRM_INFO("%s: -EBUSY\n", __FUNCTION__); return ret; #else - return mga_do_wait_for_idle( dev_priv ); + return mga_do_wait_for_idle(dev_priv); #endif } else { return 0; } } -int mga_dma_reset( DRM_IOCTL_ARGS ) +int mga_dma_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - return mga_do_dma_reset( dev_priv ); + return mga_do_dma_reset(dev_priv); } - /* ================================================================ * DMA buffer management */ -static int mga_dma_get_buffers( DRMFILE filp, - drm_device_t *dev, drm_dma_t *d ) +static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d) { drm_buf_t *buf; int i; - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = mga_freelist_get( dev ); - if ( !buf ) return DRM_ERR(EAGAIN); + for (i = d->granted_count; i < d->request_count; i++) { + buf = mga_freelist_get(dev); + if (!buf) + return DRM_ERR(EAGAIN); buf->filp = filp; - if ( DRM_COPY_TO_USER( &d->request_indices[i], - &buf->idx, sizeof(buf->idx) ) ) + if (DRM_COPY_TO_USER(&d->request_indices[i], + &buf->idx, sizeof(buf->idx))) return DRM_ERR(EFAULT); - if ( DRM_COPY_TO_USER( &d->request_sizes[i], - &buf->total, sizeof(buf->total) ) ) + if (DRM_COPY_TO_USER(&d->request_sizes[i], + &buf->total, sizeof(buf->total))) return DRM_ERR(EFAULT); d->granted_count++; @@ -757,55 +744,55 @@ static int mga_dma_get_buffers( DRMFILE filp, return 0; } -int mga_dma_buffers( DRM_IOCTL_ARGS ) +int mga_dma_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; drm_dma_t __user *argp = (void __user *)data; drm_dma_t d; int ret = 0; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); + DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); /* Please don't send us buffers. */ - if ( d.send_count != 0 ) { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count ); + if (d.send_count != 0) { + DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", + DRM_CURRENTPID, d.send_count); return DRM_ERR(EINVAL); } /* We'll send you buffers. */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count ); + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", + DRM_CURRENTPID, d.request_count, dma->buf_count); return DRM_ERR(EINVAL); } - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); d.granted_count = 0; - if ( d.request_count ) { - ret = mga_dma_get_buffers( filp, dev, &d ); + if (d.request_count) { + ret = mga_dma_get_buffers(filp, dev, &d); } - DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); + DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); return ret; } -void mga_driver_pretakedown(drm_device_t *dev) +void mga_driver_pretakedown(drm_device_t * dev) { - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); } -int mga_driver_dma_quiescent(drm_device_t *dev) +int mga_driver_dma_quiescent(drm_device_t * dev) { drm_mga_private_t *dev_priv = dev->dev_private; - return mga_do_wait_for_idle( dev_priv ); + return mga_do_wait_for_idle(dev_priv); } diff --git a/shared-core/mga_drm.h b/shared-core/mga_drm.h index 521d4451..40f06c36 100644 --- a/shared-core/mga_drm.h +++ b/shared-core/mga_drm.h @@ -44,10 +44,10 @@ /* WARP pipe flags */ -#define MGA_F 0x1 /* fog */ -#define MGA_A 0x2 /* alpha */ -#define MGA_S 0x4 /* specular */ -#define MGA_T2 0x8 /* multitexture */ +#define MGA_F 0x1 /* fog */ +#define MGA_A 0x2 /* alpha */ +#define MGA_S 0x4 /* specular */ +#define MGA_T2 0x8 /* multitexture */ #define MGA_WARP_TGZ 0 #define MGA_WARP_TGZF (MGA_F) @@ -66,15 +66,14 @@ #define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) #define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) -#define MGA_MAX_G200_PIPES 8 /* no multitex */ +#define MGA_MAX_G200_PIPES 8 /* no multitex */ #define MGA_MAX_G400_PIPES 16 #define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES -#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ +#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ #define MGA_CARD_TYPE_G200 1 #define MGA_CARD_TYPE_G400 2 - #define MGA_FRONT 0x1 #define MGA_BACK 0x2 #define MGA_DEPTH 0x4 @@ -85,14 +84,14 @@ #define MGA_UPLOAD_TEX0 0x2 #define MGA_UPLOAD_TEX1 0x4 #define MGA_UPLOAD_PIPE 0x8 -#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ -#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ +#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ +#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ #define MGA_UPLOAD_2D 0x40 -#define MGA_WAIT_AGE 0x80 /* handled client-side */ -#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ +#define MGA_WAIT_AGE 0x80 /* handled client-side */ +#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ #if 0 -#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock - quiescent */ +#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock + quiescent */ #endif /* 32 buffers of 64k each, total 2 meg. @@ -119,8 +118,7 @@ #define DRM_MGA_IDLE_RETRY 2048 -#endif /* __MGA_SAREA_DEFINES__ */ - +#endif /* __MGA_SAREA_DEFINES__ */ /* Setup registers for 3D context */ @@ -164,25 +162,25 @@ typedef struct { /* General aging mechanism */ typedef struct { - unsigned int head; /* Position of head pointer */ - unsigned int wrap; /* Primary DMA wrap count */ + unsigned int head; /* Position of head pointer */ + unsigned int wrap; /* Primary DMA wrap count */ } drm_mga_age_t; typedef struct _drm_mga_sarea { /* The channel for communication of state information to the kernel * on firing a vertex dma buffer. */ - drm_mga_context_regs_t context_state; - drm_mga_server_regs_t server_state; - drm_mga_texture_regs_t tex_state[2]; - unsigned int warp_pipe; - unsigned int dirty; - unsigned int vertsize; + drm_mga_context_regs_t context_state; + drm_mga_server_regs_t server_state; + drm_mga_texture_regs_t tex_state[2]; + unsigned int warp_pipe; + unsigned int dirty; + unsigned int vertsize; /* The current cliprects, or a subset thereof. */ - drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS]; - unsigned int nbox; + drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS]; + unsigned int nbox; /* Information about the most recently used 3d drawable. The * client fills in the req_* fields, the server fills in the @@ -191,18 +189,18 @@ typedef struct _drm_mga_sarea { * The client clears the exported_drawable field before * clobbering the boxes data. */ - unsigned int req_drawable; /* the X drawable id */ - unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ + unsigned int req_drawable; /* the X drawable id */ + unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ - unsigned int exported_drawable; + unsigned int exported_drawable; unsigned int exported_index; - unsigned int exported_stamp; - unsigned int exported_buffers; - unsigned int exported_nfront; - unsigned int exported_nback; + unsigned int exported_stamp; + unsigned int exported_buffers; + unsigned int exported_nfront; + unsigned int exported_nback; int exported_back_x, exported_front_x, exported_w; int exported_back_y, exported_front_y, exported_h; - drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS]; + drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS]; /* Counters for aging textures and for client-side throttling. */ @@ -210,21 +208,20 @@ typedef struct _drm_mga_sarea { unsigned int last_wrap; drm_mga_age_t last_frame; - unsigned int last_enqueue; /* last time a buffer was enqueued */ + unsigned int last_enqueue; /* last time a buffer was enqueued */ unsigned int last_dispatch; /* age of the most recently dispatched buffer */ - unsigned int last_quiescent; /* */ + unsigned int last_quiescent; /* */ /* LRU lists for texture memory in agp space and on the card. */ - drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1]; + drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; unsigned int texAge[MGA_NR_TEX_HEAPS]; /* Mechanism to validate card state. */ - int ctxOwner; + int ctxOwner; } drm_mga_sarea_t; - /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmMga.h) */ @@ -255,33 +252,33 @@ typedef struct _drm_mga_sarea { #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) typedef struct _drm_mga_warp_index { - int installed; - unsigned long phys_addr; - int size; + int installed; + unsigned long phys_addr; + int size; } drm_mga_warp_index_t; typedef struct drm_mga_init { - enum { - MGA_INIT_DMA = 0x01, - MGA_CLEANUP_DMA = 0x02 + enum { + MGA_INIT_DMA = 0x01, + MGA_CLEANUP_DMA = 0x02 } func; - unsigned long sarea_priv_offset; + unsigned long sarea_priv_offset; int chipset; - int sgram; + int sgram; unsigned int maccess; - unsigned int fb_cpp; + unsigned int fb_cpp; unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; + unsigned int back_offset, back_pitch; - unsigned int depth_cpp; - unsigned int depth_offset, depth_pitch; + unsigned int depth_cpp; + unsigned int depth_offset, depth_pitch; - unsigned int texture_offset[MGA_NR_TEX_HEAPS]; - unsigned int texture_size[MGA_NR_TEX_HEAPS]; + unsigned int texture_offset[MGA_NR_TEX_HEAPS]; + unsigned int texture_size[MGA_NR_TEX_HEAPS]; unsigned long fb_offset; unsigned long mmio_offset; @@ -293,7 +290,7 @@ typedef struct drm_mga_init { typedef struct drm_mga_fullscreen { enum { - MGA_INIT_FULLSCREEN = 0x01, + MGA_INIT_FULLSCREEN = 0x01, MGA_CLEANUP_FULLSCREEN = 0x02 } func; } drm_mga_fullscreen_t; @@ -307,16 +304,16 @@ typedef struct drm_mga_clear { } drm_mga_clear_t; typedef struct drm_mga_vertex { - int idx; /* buffer to queue */ - int used; /* bytes in use */ - int discard; /* client finished with buffer? */ + int idx; /* buffer to queue */ + int used; /* bytes in use */ + int discard; /* client finished with buffer? */ } drm_mga_vertex_t; typedef struct drm_mga_indices { - int idx; /* buffer to queue */ + int idx; /* buffer to queue */ unsigned int start; unsigned int end; - int discard; /* client finished with buffer? */ + int discard; /* client finished with buffer? */ } drm_mga_indices_t; typedef struct drm_mga_iload { @@ -332,12 +329,12 @@ typedef struct _drm_mga_blit { int src_pitch, dst_pitch; int delta_sx, delta_sy; int delta_dx, delta_dy; - int height, ydir; /* flip image vertically */ + int height, ydir; /* flip image vertically */ int source_pitch, dest_pitch; } drm_mga_blit_t; /* 3.1: An ioctl to get parameters that aren't available to the 3d - * client any other way. + * client any other way. */ #define MGA_PARAM_IRQ_NR 1 diff --git a/shared-core/mga_drv.h b/shared-core/mga_drv.h index 3d8e9aef..a00fb421 100644 --- a/shared-core/mga_drv.h +++ b/shared-core/mga_drv.h @@ -62,14 +62,14 @@ typedef struct drm_mga_primary_buffer { } drm_mga_primary_buffer_t; typedef struct drm_mga_freelist { - struct drm_mga_freelist *next; - struct drm_mga_freelist *prev; + struct drm_mga_freelist *next; + struct drm_mga_freelist *prev; drm_mga_age_t age; - drm_buf_t *buf; + drm_buf_t *buf; } drm_mga_freelist_t; typedef struct { - drm_mga_freelist_t *list_entry; + drm_mga_freelist_t *list_entry; int discard; int dispatched; } drm_mga_buf_priv_t; @@ -78,8 +78,8 @@ typedef struct drm_mga_private { drm_mga_primary_buffer_t prim; drm_mga_sarea_t *sarea_priv; - drm_mga_freelist_t *head; - drm_mga_freelist_t *tail; + drm_mga_freelist_t *head; + drm_mga_freelist_t *tail; unsigned int warp_pipe; unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; @@ -113,43 +113,43 @@ typedef struct drm_mga_private { } drm_mga_private_t; /* mga_dma.c */ -extern int mga_dma_init( DRM_IOCTL_ARGS ); -extern int mga_dma_flush( DRM_IOCTL_ARGS ); -extern int mga_dma_reset( DRM_IOCTL_ARGS ); -extern int mga_dma_buffers( DRM_IOCTL_ARGS ); -extern void mga_driver_pretakedown(drm_device_t *dev); -extern int mga_driver_dma_quiescent(drm_device_t *dev); +extern int mga_dma_init(DRM_IOCTL_ARGS); +extern int mga_dma_flush(DRM_IOCTL_ARGS); +extern int mga_dma_reset(DRM_IOCTL_ARGS); +extern int mga_dma_buffers(DRM_IOCTL_ARGS); +extern void mga_driver_pretakedown(drm_device_t * dev); +extern int mga_driver_dma_quiescent(drm_device_t * dev); -extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ); -extern int mga_do_dma_idle( drm_mga_private_t *dev_priv ); -extern int mga_do_dma_reset( drm_mga_private_t *dev_priv ); -extern int mga_do_engine_reset( drm_mga_private_t *dev_priv ); -extern int mga_do_cleanup_dma( drm_device_t *dev ); +extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv); +extern int mga_do_dma_idle(drm_mga_private_t * dev_priv); +extern int mga_do_dma_reset(drm_mga_private_t * dev_priv); +extern int mga_do_engine_reset(drm_mga_private_t * dev_priv); +extern int mga_do_cleanup_dma(drm_device_t * dev); -extern void mga_do_dma_flush( drm_mga_private_t *dev_priv ); -extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ); -extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ); +extern void mga_do_dma_flush(drm_mga_private_t * dev_priv); +extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv); +extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); -extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ); +extern int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf); /* mga_state.c */ -extern int mga_dma_clear( DRM_IOCTL_ARGS ); -extern int mga_dma_swap( DRM_IOCTL_ARGS ); -extern int mga_dma_vertex( DRM_IOCTL_ARGS ); -extern int mga_dma_indices( DRM_IOCTL_ARGS ); -extern int mga_dma_iload( DRM_IOCTL_ARGS ); -extern int mga_dma_blit( DRM_IOCTL_ARGS ); -extern int mga_getparam( DRM_IOCTL_ARGS ); +extern int mga_dma_clear(DRM_IOCTL_ARGS); +extern int mga_dma_swap(DRM_IOCTL_ARGS); +extern int mga_dma_vertex(DRM_IOCTL_ARGS); +extern int mga_dma_indices(DRM_IOCTL_ARGS); +extern int mga_dma_iload(DRM_IOCTL_ARGS); +extern int mga_dma_blit(DRM_IOCTL_ARGS); +extern int mga_getparam(DRM_IOCTL_ARGS); /* mga_warp.c */ -extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); -extern int mga_warp_init( drm_mga_private_t *dev_priv ); +extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv); +extern int mga_warp_init(drm_mga_private_t * dev_priv); -extern int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); -extern irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ); -extern void mga_driver_irq_preinstall( drm_device_t *dev ); -extern void mga_driver_irq_postinstall( drm_device_t *dev ); -extern void mga_driver_irq_uninstall( drm_device_t *dev ); +extern int mga_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence); +extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS); +extern void mga_driver_irq_preinstall(drm_device_t * dev); +extern void mga_driver_irq_postinstall(drm_device_t * dev); +extern void mga_driver_irq_uninstall(drm_device_t * dev); #define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() @@ -165,7 +165,7 @@ extern void mga_driver_irq_uninstall( drm_device_t *dev ); #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) #define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) -static inline u32 _MGA_READ(u32 *addr) +static inline u32 _MGA_READ(u32 * addr) { DRM_MEMORYBARRIER(); return *(volatile u32 *)addr; @@ -187,8 +187,6 @@ static inline u32 _MGA_READ(u32 *addr) #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) - - /* ================================================================ * Helper macross... */ @@ -230,7 +228,6 @@ do { \ } \ } while (0) - /* ================================================================ * Primary DMA command stream */ @@ -315,7 +312,6 @@ do { \ write += DMA_BLOCK_SIZE; \ } while (0) - /* Buffer aging via primary DMA stream head pointer. */ @@ -342,7 +338,6 @@ do { \ } \ } while (0) - #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ MGA_DWGENGSTS | \ MGA_ENDPRDMASTS) @@ -351,8 +346,6 @@ do { \ #define MGA_DMA_DEBUG 0 - - /* A reduced set of the mga registers. */ #define MGA_CRTC_INDEX 0x1fd4 @@ -607,7 +600,6 @@ do { \ # define MGA_G400_WR_MAGIC (1 << 6) # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ - #define MGA_ILOAD_ALIGN 64 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) @@ -642,10 +634,10 @@ do { \ /* Simple idle test. */ -static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv ) +static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv) { - u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; - return ( status == MGA_ENDPRDMASTS ); + u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; + return (status == MGA_ENDPRDMASTS); } #endif diff --git a/shared-core/mga_irq.c b/shared-core/mga_irq.c index bc0b6b5d..704652d3 100644 --- a/shared-core/mga_irq.c +++ b/shared-core/mga_irq.c @@ -1,7 +1,7 @@ /* mga_irq.c -- IRQ handling for radeon -*- linux-c -*- * * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * + * * The Weather Channel (TM) funded Tungsten Graphics to develop the * initial release of the Radeon 8500 driver under the XFree86 license. * This notice must be preserved. @@ -35,68 +35,67 @@ #include "mga_drm.h" #include "mga_drv.h" -irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ) +irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS) { drm_device_t *dev = (drm_device_t *) arg; - drm_mga_private_t *dev_priv = - (drm_mga_private_t *)dev->dev_private; + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; int status; - status = MGA_READ( MGA_STATUS ); - + status = MGA_READ(MGA_STATUS); + /* VBLANK interrupt */ - if ( status & MGA_VLINEPEN ) { - MGA_WRITE( MGA_ICLEAR, MGA_VLINEICLR ); + if (status & MGA_VLINEPEN) { + MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR); atomic_inc(&dev->vbl_received); DRM_WAKEUP(&dev->vbl_queue); - drm_vbl_send_signals( dev ); + drm_vbl_send_signals(dev); return IRQ_HANDLED; } return IRQ_NONE; } -int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +int mga_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) { unsigned int cur_vblank; int ret = 0; /* Assume that the user has missed the current sequence number * by about a day rather than she wants to wait for years - * using vertical blanks... + * using vertical blanks... */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, - ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - - *sequence ) <= (1<<23) ) ); + DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, + (((cur_vblank = atomic_read(&dev->vbl_received)) + - *sequence) <= (1 << 23))); *sequence = cur_vblank; return ret; } -void mga_driver_irq_preinstall( drm_device_t *dev ) { - drm_mga_private_t *dev_priv = - (drm_mga_private_t *)dev->dev_private; +void mga_driver_irq_preinstall(drm_device_t * dev) +{ + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; /* Disable *all* interrupts */ - MGA_WRITE( MGA_IEN, 0 ); + MGA_WRITE(MGA_IEN, 0); /* Clear bits if they're already high */ - MGA_WRITE( MGA_ICLEAR, ~0 ); + MGA_WRITE(MGA_ICLEAR, ~0); } -void mga_driver_irq_postinstall( drm_device_t *dev ) { - drm_mga_private_t *dev_priv = - (drm_mga_private_t *)dev->dev_private; +void mga_driver_irq_postinstall(drm_device_t * dev) +{ + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; /* Turn on VBL interrupt */ - MGA_WRITE( MGA_IEN, MGA_VLINEIEN ); + MGA_WRITE(MGA_IEN, MGA_VLINEIEN); } -void mga_driver_irq_uninstall( drm_device_t *dev ) { - drm_mga_private_t *dev_priv = - (drm_mga_private_t *)dev->dev_private; +void mga_driver_irq_uninstall(drm_device_t * dev) +{ + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; if (!dev_priv) return; /* Disable *all* interrupts */ - MGA_WRITE( MGA_IEN, 0 ); + MGA_WRITE(MGA_IEN, 0); } diff --git a/shared-core/mga_state.c b/shared-core/mga_state.c index f676e974..59d87a23 100644 --- a/shared-core/mga_state.c +++ b/shared-core/mga_state.c @@ -37,126 +37,114 @@ #include "mga_drm.h" #include "mga_drv.h" - /* ================================================================ * DMA hardware state programming functions */ -static void mga_emit_clip_rect( drm_mga_private_t *dev_priv, - drm_clip_rect_t *box ) +static void mga_emit_clip_rect(drm_mga_private_t * dev_priv, + drm_clip_rect_t * box) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; unsigned int pitch = dev_priv->front_pitch; DMA_LOCALS; - BEGIN_DMA( 2 ); + BEGIN_DMA(2); /* Force reset of DWGCTL on G400 (eliminates clip disable bit). */ - if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { - DMA_BLOCK( MGA_DWGCTL, ctx->dwgctl, - MGA_LEN + MGA_EXEC, 0x80000000, - MGA_DWGCTL, ctx->dwgctl, - MGA_LEN + MGA_EXEC, 0x80000000 ); + if (dev_priv->chipset == MGA_CARD_TYPE_G400) { + DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl, + MGA_LEN + MGA_EXEC, 0x80000000, + MGA_DWGCTL, ctx->dwgctl, + MGA_LEN + MGA_EXEC, 0x80000000); } - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_CXBNDRY, (box->x2 << 16) | box->x1, - MGA_YTOP, box->y1 * pitch, - MGA_YBOT, box->y2 * pitch ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_CXBNDRY, (box->x2 << 16) | box->x1, + MGA_YTOP, box->y1 * pitch, MGA_YBOT, box->y2 * pitch); ADVANCE_DMA(); } -static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; DMA_LOCALS; - BEGIN_DMA( 3 ); + BEGIN_DMA(3); - DMA_BLOCK( MGA_DSTORG, ctx->dstorg, - MGA_MACCESS, ctx->maccess, - MGA_PLNWT, ctx->plnwt, - MGA_DWGCTL, ctx->dwgctl ); + DMA_BLOCK(MGA_DSTORG, ctx->dstorg, + MGA_MACCESS, ctx->maccess, + MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl); - DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, - MGA_FOGCOL, ctx->fogcolor, - MGA_WFLAG, ctx->wflag, - MGA_ZORG, dev_priv->depth_offset ); + DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl, + MGA_FOGCOL, ctx->fogcolor, + MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset); - DMA_BLOCK( MGA_FCOL, ctx->fcol, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_FCOL, ctx->fcol, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); ADVANCE_DMA(); } -static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; DMA_LOCALS; - BEGIN_DMA( 4 ); + BEGIN_DMA(4); - DMA_BLOCK( MGA_DSTORG, ctx->dstorg, - MGA_MACCESS, ctx->maccess, - MGA_PLNWT, ctx->plnwt, - MGA_DWGCTL, ctx->dwgctl ); + DMA_BLOCK(MGA_DSTORG, ctx->dstorg, + MGA_MACCESS, ctx->maccess, + MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl); - DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, - MGA_FOGCOL, ctx->fogcolor, - MGA_WFLAG, ctx->wflag, - MGA_ZORG, dev_priv->depth_offset ); + DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl, + MGA_FOGCOL, ctx->fogcolor, + MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset); - DMA_BLOCK( MGA_WFLAG1, ctx->wflag, - MGA_TDUALSTAGE0, ctx->tdualstage0, - MGA_TDUALSTAGE1, ctx->tdualstage1, - MGA_FCOL, ctx->fcol ); + DMA_BLOCK(MGA_WFLAG1, ctx->wflag, + MGA_TDUALSTAGE0, ctx->tdualstage0, + MGA_TDUALSTAGE1, ctx->tdualstage1, MGA_FCOL, ctx->fcol); - DMA_BLOCK( MGA_STENCIL, ctx->stencil, - MGA_STENCILCTL, ctx->stencilctl, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_STENCIL, ctx->stencil, + MGA_STENCILCTL, ctx->stencilctl, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); ADVANCE_DMA(); } -static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; DMA_LOCALS; - BEGIN_DMA( 4 ); + BEGIN_DMA(4); - DMA_BLOCK( MGA_TEXCTL2, tex->texctl2, - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol ); + DMA_BLOCK(MGA_TEXCTL2, tex->texctl2, + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol); - DMA_BLOCK( MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3 ); + DMA_BLOCK(MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3); - DMA_BLOCK( MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR24, tex->texwidth ); + DMA_BLOCK(MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, MGA_WR24, tex->texwidth); - DMA_BLOCK( MGA_WR34, tex->texheight, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_WR34, tex->texheight, + MGA_TEXTRANS, 0x0000ffff, + MGA_TEXTRANSHIGH, 0x0000ffff, MGA_DMAPAD, 0x00000000); ADVANCE_DMA(); } -static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; @@ -165,42 +153,38 @@ static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv ) /* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */ /* tex->texctl, tex->texctl2); */ - BEGIN_DMA( 6 ); + BEGIN_DMA(6); - DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC, - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol ); + DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC, + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol); - DMA_BLOCK( MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3 ); + DMA_BLOCK(MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3); - DMA_BLOCK( MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR49, 0x00000000 ); + DMA_BLOCK(MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000); - DMA_BLOCK( MGA_WR57, 0x00000000, - MGA_WR53, 0x00000000, - MGA_WR61, 0x00000000, - MGA_WR52, MGA_G400_WR_MAGIC ); + DMA_BLOCK(MGA_WR57, 0x00000000, + MGA_WR53, 0x00000000, + MGA_WR61, 0x00000000, MGA_WR52, MGA_G400_WR_MAGIC); - DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC, - MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC, - MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC, + MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC, + MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC, + MGA_DMAPAD, 0x00000000); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_TEXTRANS, 0x0000ffff, MGA_TEXTRANSHIGH, 0x0000ffff); ADVANCE_DMA(); } -static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1]; @@ -209,69 +193,64 @@ static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv ) /* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */ /* tex->texctl, tex->texctl2); */ - BEGIN_DMA( 5 ); + BEGIN_DMA(5); - DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 | - MGA_MAP1_ENABLE | - MGA_G400_TC2_MAGIC), - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol ); + DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 | + MGA_MAP1_ENABLE | + MGA_G400_TC2_MAGIC), + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol); - DMA_BLOCK( MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3 ); + DMA_BLOCK(MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3); - DMA_BLOCK( MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR49, 0x00000000 ); + DMA_BLOCK(MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000); - DMA_BLOCK( MGA_WR57, 0x00000000, - MGA_WR53, 0x00000000, - MGA_WR61, 0x00000000, - MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC ); + DMA_BLOCK(MGA_WR57, 0x00000000, + MGA_WR53, 0x00000000, + MGA_WR61, 0x00000000, + MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC); - DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff, - MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC ); + DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC, + MGA_TEXTRANS, 0x0000ffff, + MGA_TEXTRANSHIGH, 0x0000ffff, + MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC); ADVANCE_DMA(); } -static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int pipe = sarea_priv->warp_pipe; DMA_LOCALS; - BEGIN_DMA( 3 ); + BEGIN_DMA(3); - DMA_BLOCK( MGA_WIADDR, MGA_WMODE_SUSPEND, - MGA_WVRTXSZ, 0x00000007, - MGA_WFLAG, 0x00000000, - MGA_WR24, 0x00000000 ); + DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND, + MGA_WVRTXSZ, 0x00000007, + MGA_WFLAG, 0x00000000, MGA_WR24, 0x00000000); - DMA_BLOCK( MGA_WR25, 0x00000100, - MGA_WR34, 0x00000000, - MGA_WR42, 0x0000ffff, - MGA_WR60, 0x0000ffff ); + DMA_BLOCK(MGA_WR25, 0x00000100, + MGA_WR34, 0x00000000, + MGA_WR42, 0x0000ffff, MGA_WR60, 0x0000ffff); /* Padding required to to hardware bug. */ - DMA_BLOCK( MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] | - MGA_WMODE_START | - MGA_WAGP_ENABLE) ); + DMA_BLOCK(MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] | + MGA_WMODE_START | MGA_WAGP_ENABLE)); ADVANCE_DMA(); } -static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int pipe = sarea_priv->warp_pipe; @@ -279,145 +258,139 @@ static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv ) /* printk("mga_g400_emit_pipe %x\n", pipe); */ - BEGIN_DMA( 10 ); + BEGIN_DMA(10); - DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); - if ( pipe & MGA_T2 ) { - DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + if (pipe & MGA_T2) { + DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); - DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x1e000000 ); + DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x1e000000); } else { - if ( dev_priv->warp_pipe & MGA_T2 ) { + if (dev_priv->warp_pipe & MGA_T2) { /* Flush the WARP pipe */ - DMA_BLOCK( MGA_YDST, 0x00000000, - MGA_FXLEFT, 0x00000000, - MGA_FXRIGHT, 0x00000001, - MGA_DWGCTL, MGA_DWGCTL_FLUSH ); - - DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001, - MGA_DWGSYNC, 0x00007000, - MGA_TEXCTL2, MGA_G400_TC2_MAGIC, - MGA_LEN + MGA_EXEC, 0x00000000 ); - - DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX | - MGA_G400_TC2_MAGIC), - MGA_LEN + MGA_EXEC, 0x00000000, - MGA_TEXCTL2, MGA_G400_TC2_MAGIC, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_YDST, 0x00000000, + MGA_FXLEFT, 0x00000000, + MGA_FXRIGHT, 0x00000001, + MGA_DWGCTL, MGA_DWGCTL_FLUSH); + + DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001, + MGA_DWGSYNC, 0x00007000, + MGA_TEXCTL2, MGA_G400_TC2_MAGIC, + MGA_LEN + MGA_EXEC, 0x00000000); + + DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX | + MGA_G400_TC2_MAGIC), + MGA_LEN + MGA_EXEC, 0x00000000, + MGA_TEXCTL2, MGA_G400_TC2_MAGIC, + MGA_DMAPAD, 0x00000000); } - DMA_BLOCK( MGA_WVRTXSZ, 0x00001807, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_WVRTXSZ, 0x00001807, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); - DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x18000000 ); + DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x18000000); } - DMA_BLOCK( MGA_WFLAG, 0x00000000, - MGA_WFLAG1, 0x00000000, - MGA_WR56, MGA_G400_WR56_MAGIC, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_WFLAG, 0x00000000, + MGA_WFLAG1, 0x00000000, + MGA_WR56, MGA_G400_WR56_MAGIC, MGA_DMAPAD, 0x00000000); - DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */ - MGA_WR57, 0x00000000, /* tex0 */ - MGA_WR53, 0x00000000, /* tex1 */ - MGA_WR61, 0x00000000 ); /* tex1 */ + DMA_BLOCK(MGA_WR49, 0x00000000, /* tex0 */ + MGA_WR57, 0x00000000, /* tex0 */ + MGA_WR53, 0x00000000, /* tex1 */ + MGA_WR61, 0x00000000); /* tex1 */ - DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */ - MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */ - MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */ - MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */ + DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */ + MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */ + MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */ + MGA_WR60, MGA_G400_WR_MAGIC); /* tex1 height */ /* Padding required to to hardware bug */ - DMA_BLOCK( MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] | - MGA_WMODE_START | - MGA_WAGP_ENABLE) ); + DMA_BLOCK(MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] | + MGA_WMODE_START | MGA_WAGP_ENABLE)); ADVANCE_DMA(); } -static void mga_g200_emit_state( drm_mga_private_t *dev_priv ) +static void mga_g200_emit_state(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; - if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { - mga_g200_emit_pipe( dev_priv ); + if (sarea_priv->warp_pipe != dev_priv->warp_pipe) { + mga_g200_emit_pipe(dev_priv); dev_priv->warp_pipe = sarea_priv->warp_pipe; } - if ( dirty & MGA_UPLOAD_CONTEXT ) { - mga_g200_emit_context( dev_priv ); + if (dirty & MGA_UPLOAD_CONTEXT) { + mga_g200_emit_context(dev_priv); sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; } - if ( dirty & MGA_UPLOAD_TEX0 ) { - mga_g200_emit_tex0( dev_priv ); + if (dirty & MGA_UPLOAD_TEX0) { + mga_g200_emit_tex0(dev_priv); sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; } } -static void mga_g400_emit_state( drm_mga_private_t *dev_priv ) +static void mga_g400_emit_state(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; int multitex = sarea_priv->warp_pipe & MGA_T2; - if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { - mga_g400_emit_pipe( dev_priv ); + if (sarea_priv->warp_pipe != dev_priv->warp_pipe) { + mga_g400_emit_pipe(dev_priv); dev_priv->warp_pipe = sarea_priv->warp_pipe; } - if ( dirty & MGA_UPLOAD_CONTEXT ) { - mga_g400_emit_context( dev_priv ); + if (dirty & MGA_UPLOAD_CONTEXT) { + mga_g400_emit_context(dev_priv); sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; } - if ( dirty & MGA_UPLOAD_TEX0 ) { - mga_g400_emit_tex0( dev_priv ); + if (dirty & MGA_UPLOAD_TEX0) { + mga_g400_emit_tex0(dev_priv); sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; } - if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) { - mga_g400_emit_tex1( dev_priv ); + if ((dirty & MGA_UPLOAD_TEX1) && multitex) { + mga_g400_emit_tex1(dev_priv); sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; } } - /* ================================================================ * SAREA state verification */ /* Disallow all write destinations except the front and backbuffer. */ -static int mga_verify_context( drm_mga_private_t *dev_priv ) +static int mga_verify_context(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - if ( ctx->dstorg != dev_priv->front_offset && - ctx->dstorg != dev_priv->back_offset ) { - DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n", - ctx->dstorg, dev_priv->front_offset, - dev_priv->back_offset ); + if (ctx->dstorg != dev_priv->front_offset && + ctx->dstorg != dev_priv->back_offset) { + DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n", + ctx->dstorg, dev_priv->front_offset, + dev_priv->back_offset); ctx->dstorg = 0; return DRM_ERR(EINVAL); } @@ -427,7 +400,7 @@ static int mga_verify_context( drm_mga_private_t *dev_priv ) /* Disallow texture reads from PCI space. */ -static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) +static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit]; @@ -435,9 +408,8 @@ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK); - if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) { - DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n", - tex->texorg, unit ); + if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) { + DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit); tex->texorg = 0; return DRM_ERR(EINVAL); } @@ -445,73 +417,70 @@ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) return 0; } -static int mga_verify_state( drm_mga_private_t *dev_priv ) +static int mga_verify_state(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; int ret = 0; - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - if ( dirty & MGA_UPLOAD_CONTEXT ) - ret |= mga_verify_context( dev_priv ); + if (dirty & MGA_UPLOAD_CONTEXT) + ret |= mga_verify_context(dev_priv); - if ( dirty & MGA_UPLOAD_TEX0 ) - ret |= mga_verify_tex( dev_priv, 0 ); + if (dirty & MGA_UPLOAD_TEX0) + ret |= mga_verify_tex(dev_priv, 0); - if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { - if ( dirty & MGA_UPLOAD_TEX1 ) - ret |= mga_verify_tex( dev_priv, 1 ); + if (dev_priv->chipset == MGA_CARD_TYPE_G400) { + if (dirty & MGA_UPLOAD_TEX1) + ret |= mga_verify_tex(dev_priv, 1); - if ( dirty & MGA_UPLOAD_PIPE ) - ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES ); + if (dirty & MGA_UPLOAD_PIPE) + ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES); } else { - if ( dirty & MGA_UPLOAD_PIPE ) - ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES ); + if (dirty & MGA_UPLOAD_PIPE) + ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES); } - return ( ret == 0 ); + return (ret == 0); } -static int mga_verify_iload( drm_mga_private_t *dev_priv, - unsigned int dstorg, unsigned int length ) +static int mga_verify_iload(drm_mga_private_t * dev_priv, + unsigned int dstorg, unsigned int length) { - if ( dstorg < dev_priv->texture_offset || - dstorg + length > (dev_priv->texture_offset + - dev_priv->texture_size) ) { - DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg ); + if (dstorg < dev_priv->texture_offset || + dstorg + length > (dev_priv->texture_offset + + dev_priv->texture_size)) { + DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg); return DRM_ERR(EINVAL); } - if ( length & MGA_ILOAD_MASK ) { - DRM_ERROR( "*** bad iload length: 0x%x\n", - length & MGA_ILOAD_MASK ); + if (length & MGA_ILOAD_MASK) { + DRM_ERROR("*** bad iload length: 0x%x\n", + length & MGA_ILOAD_MASK); return DRM_ERR(EINVAL); } return 0; } -static int mga_verify_blit( drm_mga_private_t *dev_priv, - unsigned int srcorg, unsigned int dstorg ) +static int mga_verify_blit(drm_mga_private_t * dev_priv, + unsigned int srcorg, unsigned int dstorg) { - if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || - (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) { - DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n", - srcorg, dstorg ); + if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || + (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) { + DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg); return DRM_ERR(EINVAL); } return 0; } - /* ================================================================ * */ -static void mga_dma_dispatch_clear( drm_device_t *dev, - drm_mga_clear_t *clear ) +static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -520,92 +489,86 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int nbox = sarea_priv->nbox; int i; DMA_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - BEGIN_DMA( 1 ); + BEGIN_DMA(1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000); ADVANCE_DMA(); - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { drm_clip_rect_t *box = &pbox[i]; u32 height = box->y2 - box->y1; - DRM_DEBUG( " from=%d,%d to=%d,%d\n", - box->x1, box->y1, box->x2, box->y2 ); + DRM_DEBUG(" from=%d,%d to=%d,%d\n", + box->x1, box->y1, box->x2, box->y2); - if ( clear->flags & MGA_FRONT ) { - BEGIN_DMA( 2 ); + if (clear->flags & MGA_FRONT) { + BEGIN_DMA(2); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->color_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->color_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_color, - MGA_DSTORG, dev_priv->front_offset, - MGA_DWGCTL + MGA_EXEC, - dev_priv->clear_cmd ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_color, + MGA_DSTORG, dev_priv->front_offset, + MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); ADVANCE_DMA(); } + if (clear->flags & MGA_BACK) { + BEGIN_DMA(2); - if ( clear->flags & MGA_BACK ) { - BEGIN_DMA( 2 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->color_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->color_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_color, - MGA_DSTORG, dev_priv->back_offset, - MGA_DWGCTL + MGA_EXEC, - dev_priv->clear_cmd ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_color, + MGA_DSTORG, dev_priv->back_offset, + MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); ADVANCE_DMA(); } - if ( clear->flags & MGA_DEPTH ) { - BEGIN_DMA( 2 ); + if (clear->flags & MGA_DEPTH) { + BEGIN_DMA(2); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->depth_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->depth_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_depth, - MGA_DSTORG, dev_priv->depth_offset, - MGA_DWGCTL + MGA_EXEC, - dev_priv->clear_cmd ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_depth, + MGA_DSTORG, dev_priv->depth_offset, + MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); ADVANCE_DMA(); } } - BEGIN_DMA( 1 ); + BEGIN_DMA(1); /* Force reset of DWGCTL */ - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_DWGCTL, ctx->dwgctl ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl); ADVANCE_DMA(); FLUSH_DMA(); } -static void mga_dma_dispatch_swap( drm_device_t *dev ) +static void mga_dma_dispatch_swap(drm_device_t * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -614,56 +577,52 @@ static void mga_dma_dispatch_swap( drm_device_t *dev ) int nbox = sarea_priv->nbox; int i; DMA_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); sarea_priv->last_frame.head = dev_priv->prim.tail; sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; - BEGIN_DMA( 4 + nbox ); + BEGIN_DMA(4 + nbox); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000); - DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset, - MGA_MACCESS, dev_priv->maccess, - MGA_SRCORG, dev_priv->back_offset, - MGA_AR5, dev_priv->front_pitch ); + DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset, + MGA_MACCESS, dev_priv->maccess, + MGA_SRCORG, dev_priv->back_offset, + MGA_AR5, dev_priv->front_pitch); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_PLNWT, 0xffffffff, - MGA_DWGCTL, MGA_DWGCTL_COPY ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_PLNWT, 0xffffffff, MGA_DWGCTL, MGA_DWGCTL_COPY); - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { drm_clip_rect_t *box = &pbox[i]; u32 height = box->y2 - box->y1; u32 start = box->y1 * dev_priv->front_pitch; - DRM_DEBUG( " from=%d,%d to=%d,%d\n", - box->x1, box->y1, box->x2, box->y2 ); + DRM_DEBUG(" from=%d,%d to=%d,%d\n", + box->x1, box->y1, box->x2, box->y2); - DMA_BLOCK( MGA_AR0, start + box->x2 - 1, - MGA_AR3, start + box->x1, - MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1, - MGA_YDSTLEN + MGA_EXEC, - (box->y1 << 16) | height ); + DMA_BLOCK(MGA_AR0, start + box->x2 - 1, + MGA_AR3, start + box->x1, + MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1, + MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height); } - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_SRCORG, dev_priv->front_offset, - MGA_DWGCTL, ctx->dwgctl ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, + MGA_SRCORG, dev_priv->front_offset, MGA_DWGCTL, ctx->dwgctl); ADVANCE_DMA(); FLUSH_DMA(); - DRM_DEBUG( "%s... done.\n", __FUNCTION__ ); + DRM_DEBUG("%s... done.\n", __FUNCTION__); } -static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) +static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; @@ -672,46 +631,46 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) u32 length = (u32) buf->used; int i = 0; DMA_LOCALS; - DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used ); + DRM_DEBUG("vertex: buf=%d used=%d\n", buf->idx, buf->used); - if ( buf->used ) { + if (buf->used) { buf_priv->dispatched = 1; - MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); + MGA_EMIT_STATE(dev_priv, sarea_priv->dirty); do { - if ( i < sarea_priv->nbox ) { - mga_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); + if (i < sarea_priv->nbox) { + mga_emit_clip_rect(dev_priv, + &sarea_priv->boxes[i]); } - BEGIN_DMA( 1 ); + BEGIN_DMA(1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_SECADDRESS, (address | - MGA_DMA_VERTEX), - MGA_SECEND, ((address + length) | - MGA_PAGPXFER) ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_SECADDRESS, (address | + MGA_DMA_VERTEX), + MGA_SECEND, ((address + length) | + MGA_PAGPXFER)); ADVANCE_DMA(); - } while ( ++i < sarea_priv->nbox ); + } while (++i < sarea_priv->nbox); } - if ( buf_priv->discard ) { - AGE_BUFFER( buf_priv ); + if (buf_priv->discard) { + AGE_BUFFER(buf_priv); buf->pending = 0; buf->used = 0; buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); + mga_freelist_put(dev, buf); } FLUSH_DMA(); } -static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, - unsigned int start, unsigned int end ) +static void mga_dma_dispatch_indices(drm_device_t * dev, drm_buf_t * buf, + unsigned int start, unsigned int end) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; @@ -719,38 +678,38 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, u32 address = (u32) buf->bus_address; int i = 0; DMA_LOCALS; - DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end ); + DRM_DEBUG("indices: buf=%d start=%d end=%d\n", buf->idx, start, end); - if ( start != end ) { + if (start != end) { buf_priv->dispatched = 1; - MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); + MGA_EMIT_STATE(dev_priv, sarea_priv->dirty); do { - if ( i < sarea_priv->nbox ) { - mga_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); + if (i < sarea_priv->nbox) { + mga_emit_clip_rect(dev_priv, + &sarea_priv->boxes[i]); } - BEGIN_DMA( 1 ); + BEGIN_DMA(1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_SETUPADDRESS, address + start, - MGA_SETUPEND, ((address + end) | - MGA_PAGPXFER) ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_SETUPADDRESS, address + start, + MGA_SETUPEND, ((address + end) | + MGA_PAGPXFER)); ADVANCE_DMA(); - } while ( ++i < sarea_priv->nbox ); + } while (++i < sarea_priv->nbox); } - if ( buf_priv->discard ) { - AGE_BUFFER( buf_priv ); + if (buf_priv->discard) { + AGE_BUFFER(buf_priv); buf->pending = 0; buf->used = 0; buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); + mga_freelist_put(dev, buf); } FLUSH_DMA(); @@ -759,8 +718,8 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, /* This copies a 64 byte aligned agp region to the frambuffer with a * standard blit, the ioctl needs to do checking. */ -static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf, - unsigned int dstorg, unsigned int length ) +static void mga_dma_dispatch_iload(drm_device_t * dev, drm_buf_t * buf, + unsigned int dstorg, unsigned int length) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; @@ -768,52 +727,45 @@ static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf, u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM; u32 y2; DMA_LOCALS; - DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used ); + DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used); y2 = length / 64; - BEGIN_DMA( 5 ); + BEGIN_DMA(5); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000); - DMA_BLOCK( MGA_DSTORG, dstorg, - MGA_MACCESS, 0x00000000, - MGA_SRCORG, srcorg, - MGA_AR5, 64 ); + DMA_BLOCK(MGA_DSTORG, dstorg, + MGA_MACCESS, 0x00000000, MGA_SRCORG, srcorg, MGA_AR5, 64); - DMA_BLOCK( MGA_PITCH, 64, - MGA_PLNWT, 0xffffffff, - MGA_DMAPAD, 0x00000000, - MGA_DWGCTL, MGA_DWGCTL_COPY ); + DMA_BLOCK(MGA_PITCH, 64, + MGA_PLNWT, 0xffffffff, + MGA_DMAPAD, 0x00000000, MGA_DWGCTL, MGA_DWGCTL_COPY); - DMA_BLOCK( MGA_AR0, 63, - MGA_AR3, 0, - MGA_FXBNDRY, (63 << 16) | 0, - MGA_YDSTLEN + MGA_EXEC, y2 ); + DMA_BLOCK(MGA_AR0, 63, + MGA_AR3, 0, + MGA_FXBNDRY, (63 << 16) | 0, MGA_YDSTLEN + MGA_EXEC, y2); - DMA_BLOCK( MGA_PLNWT, ctx->plnwt, - MGA_SRCORG, dev_priv->front_offset, - MGA_PITCH, dev_priv->front_pitch, - MGA_DWGSYNC, 0x00007000 ); + DMA_BLOCK(MGA_PLNWT, ctx->plnwt, + MGA_SRCORG, dev_priv->front_offset, + MGA_PITCH, dev_priv->front_pitch, MGA_DWGSYNC, 0x00007000); ADVANCE_DMA(); - AGE_BUFFER( buf_priv ); + AGE_BUFFER(buf_priv); buf->pending = 0; buf->used = 0; buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); + mga_freelist_put(dev, buf); FLUSH_DMA(); } -static void mga_dma_dispatch_blit( drm_device_t *dev, - drm_mga_blit_t *blit ) +static void mga_dma_dispatch_blit(drm_device_t * dev, drm_mga_blit_t * blit) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -822,26 +774,24 @@ static void mga_dma_dispatch_blit( drm_device_t *dev, int nbox = sarea_priv->nbox; u32 scandir = 0, i; DMA_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - BEGIN_DMA( 4 + nbox ); + BEGIN_DMA(4 + nbox); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000); - DMA_BLOCK( MGA_DWGCTL, MGA_DWGCTL_COPY, - MGA_PLNWT, blit->planemask, - MGA_SRCORG, blit->srcorg, - MGA_DSTORG, blit->dstorg ); + DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY, + MGA_PLNWT, blit->planemask, + MGA_SRCORG, blit->srcorg, MGA_DSTORG, blit->dstorg); - DMA_BLOCK( MGA_SGN, scandir, - MGA_MACCESS, dev_priv->maccess, - MGA_AR5, blit->ydir * blit->src_pitch, - MGA_PITCH, blit->dst_pitch ); + DMA_BLOCK(MGA_SGN, scandir, + MGA_MACCESS, dev_priv->maccess, + MGA_AR5, blit->ydir * blit->src_pitch, + MGA_PITCH, blit->dst_pitch); - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int srcx = pbox[i].x1 + blit->delta_sx; int srcy = pbox[i].y1 + blit->delta_sy; int dstx = pbox[i].x1 + blit->delta_dx; @@ -850,52 +800,51 @@ static void mga_dma_dispatch_blit( drm_device_t *dev, int w = pbox[i].x2 - pbox[i].x1 - 1; int start; - if ( blit->ydir == -1 ) { + if (blit->ydir == -1) { srcy = blit->height - srcy - 1; } start = srcy * blit->src_pitch + srcx; - DMA_BLOCK( MGA_AR0, start + w, - MGA_AR3, start, - MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff), - MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h ); + DMA_BLOCK(MGA_AR0, start + w, + MGA_AR3, start, + MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff), + MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h); } /* Do something to flush AGP? */ /* Force reset of DWGCTL */ - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_PITCH, dev_priv->front_pitch, - MGA_DWGCTL, ctx->dwgctl ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, + MGA_PITCH, dev_priv->front_pitch, MGA_DWGCTL, ctx->dwgctl); ADVANCE_DMA(); } - /* ================================================================ * */ -int mga_dma_clear( DRM_IOCTL_ARGS ) +int mga_dma_clear(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_clear_t clear; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t __user *)data, sizeof(clear) ); + DRM_COPY_FROM_USER_IOCTL(clear, (drm_mga_clear_t __user *) data, + sizeof(clear)); - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_clear( dev, &clear ); + mga_dma_dispatch_clear(dev, &clear); /* Make sure we restore the 3D state next time. */ @@ -904,20 +853,20 @@ int mga_dma_clear( DRM_IOCTL_ARGS ) return 0; } -int mga_dma_swap( DRM_IOCTL_ARGS ) +int mga_dma_swap(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_swap( dev ); + mga_dma_dispatch_swap(dev); /* Make sure we restore the 3D state next time. */ @@ -926,7 +875,7 @@ int mga_dma_swap( DRM_IOCTL_ARGS ) return 0; } -int mga_dma_vertex( DRM_IOCTL_ARGS ) +int mga_dma_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; @@ -935,37 +884,38 @@ int mga_dma_vertex( DRM_IOCTL_ARGS ) drm_mga_buf_priv_t *buf_priv; drm_mga_vertex_t vertex; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( vertex, - (drm_mga_vertex_t __user *)data, - sizeof(vertex) ); + DRM_COPY_FROM_USER_IOCTL(vertex, + (drm_mga_vertex_t __user *) data, + sizeof(vertex)); - if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL); + if (vertex.idx < 0 || vertex.idx > dma->buf_count) + return DRM_ERR(EINVAL); buf = dma->buflist[vertex.idx]; buf_priv = buf->dev_private; buf->used = vertex.used; buf_priv->discard = vertex.discard; - if ( !mga_verify_state( dev_priv ) ) { - if ( vertex.discard ) { - if ( buf_priv->dispatched == 1 ) - AGE_BUFFER( buf_priv ); + if (!mga_verify_state(dev_priv)) { + if (vertex.discard) { + if (buf_priv->dispatched == 1) + AGE_BUFFER(buf_priv); buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); + mga_freelist_put(dev, buf); } return DRM_ERR(EINVAL); } - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_vertex( dev, buf ); + mga_dma_dispatch_vertex(dev, buf); return 0; } -int mga_dma_indices( DRM_IOCTL_ARGS ) +int mga_dma_indices(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; @@ -974,37 +924,38 @@ int mga_dma_indices( DRM_IOCTL_ARGS ) drm_mga_buf_priv_t *buf_priv; drm_mga_indices_t indices; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( indices, - (drm_mga_indices_t __user *)data, - sizeof(indices) ); + DRM_COPY_FROM_USER_IOCTL(indices, + (drm_mga_indices_t __user *) data, + sizeof(indices)); - if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL); + if (indices.idx < 0 || indices.idx > dma->buf_count) + return DRM_ERR(EINVAL); buf = dma->buflist[indices.idx]; buf_priv = buf->dev_private; buf_priv->discard = indices.discard; - if ( !mga_verify_state( dev_priv ) ) { - if ( indices.discard ) { - if ( buf_priv->dispatched == 1 ) - AGE_BUFFER( buf_priv ); + if (!mga_verify_state(dev_priv)) { + if (indices.discard) { + if (buf_priv->dispatched == 1) + AGE_BUFFER(buf_priv); buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); + mga_freelist_put(dev, buf); } return DRM_ERR(EINVAL); } - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_indices( dev, buf, indices.start, indices.end ); + mga_dma_dispatch_indices(dev, buf, indices.start, indices.end); return 0; } -int mga_dma_iload( DRM_IOCTL_ARGS ) +int mga_dma_iload(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; @@ -1012,32 +963,34 @@ int mga_dma_iload( DRM_IOCTL_ARGS ) drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_iload_t iload; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t __user *)data, sizeof(iload) ); + DRM_COPY_FROM_USER_IOCTL(iload, (drm_mga_iload_t __user *) data, + sizeof(iload)); #if 0 - if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { - if ( MGA_DMA_DEBUG ) - DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); + if (mga_do_wait_for_idle(dev_priv) < 0) { + if (MGA_DMA_DEBUG) + DRM_INFO("%s: -EBUSY\n", __FUNCTION__); return DRM_ERR(EBUSY); } #endif - if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL); + if (iload.idx < 0 || iload.idx > dma->buf_count) + return DRM_ERR(EINVAL); buf = dma->buflist[iload.idx]; buf_priv = buf->dev_private; - if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) { - mga_freelist_put( dev, buf ); + if (mga_verify_iload(dev_priv, iload.dstorg, iload.length)) { + mga_freelist_put(dev, buf); return DRM_ERR(EINVAL); } - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length ); + mga_dma_dispatch_iload(dev, buf, iload.dstorg, iload.length); /* Make sure we restore the 3D state next time. */ @@ -1046,27 +999,28 @@ int mga_dma_iload( DRM_IOCTL_ARGS ) return 0; } -int mga_dma_blit( DRM_IOCTL_ARGS ) +int mga_dma_blit(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_blit_t blit; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t __user *)data, sizeof(blit) ); + DRM_COPY_FROM_USER_IOCTL(blit, (drm_mga_blit_t __user *) data, + sizeof(blit)); - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) ) + if (mga_verify_blit(dev_priv, blit.srcorg, blit.dstorg)) return DRM_ERR(EINVAL); - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_blit( dev, &blit ); + mga_dma_dispatch_blit(dev, &blit); /* Make sure we restore the 3D state next time. */ @@ -1075,24 +1029,24 @@ int mga_dma_blit( DRM_IOCTL_ARGS ) return 0; } -int mga_getparam( DRM_IOCTL_ARGS ) +int mga_getparam(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_getparam_t param; int value; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t __user *)data, - sizeof(param) ); + DRM_COPY_FROM_USER_IOCTL(param, (drm_mga_getparam_t __user *) data, + sizeof(param)); - DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); + DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - switch( param.param ) { + switch (param.param) { case MGA_PARAM_IRQ_NR: value = dev->irq; break; @@ -1100,10 +1054,10 @@ int mga_getparam( DRM_IOCTL_ARGS ) return DRM_ERR(EINVAL); } - if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } - + return 0; } diff --git a/shared-core/mga_ucode.h b/shared-core/mga_ucode.h index fa0f82ec..b611e274 100644 --- a/shared-core/mga_ucode.h +++ b/shared-core/mga_ucode.h @@ -40,11606 +40,11606 @@ static unsigned char warp_g200_tgz[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x98, 0xA0, 0xE9, -0x40, 0x40, 0xD8, 0xEC, + 0x00, 0x98, 0xA0, 0xE9, + 0x40, 0x40, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x1F, 0xD7, 0x18, 0xBD, -0x3F, 0xD7, 0x22, 0xBD, + 0x1F, 0xD7, 0x18, 0xBD, + 0x3F, 0xD7, 0x22, 0xBD, -0x81, 0x04, -0x89, 0x04, -0x01, 0x04, -0x09, 0x04, + 0x81, 0x04, + 0x89, 0x04, + 0x01, 0x04, + 0x09, 0x04, -0xC9, 0x41, 0xC0, 0xEC, -0x11, 0x04, -0x00, 0xE0, + 0xC9, 0x41, 0xC0, 0xEC, + 0x11, 0x04, + 0x00, 0xE0, -0x41, 0xCC, 0x41, 0xCD, -0x49, 0xCC, 0x49, 0xCD, + 0x41, 0xCC, 0x41, 0xCD, + 0x49, 0xCC, 0x49, 0xCD, -0xD1, 0x41, 0xC0, 0xEC, -0x51, 0xCC, 0x51, 0xCD, + 0xD1, 0x41, 0xC0, 0xEC, + 0x51, 0xCC, 0x51, 0xCD, -0x80, 0x04, -0x10, 0x04, -0x08, 0x04, -0x00, 0xE0, + 0x80, 0x04, + 0x10, 0x04, + 0x08, 0x04, + 0x00, 0xE0, -0x00, 0xCC, 0xC0, 0xCD, -0xD1, 0x49, 0xC0, 0xEC, + 0x00, 0xCC, 0xC0, 0xCD, + 0xD1, 0x49, 0xC0, 0xEC, -0x8A, 0x1F, 0x20, 0xE9, -0x8B, 0x3F, 0x20, 0xE9, + 0x8A, 0x1F, 0x20, 0xE9, + 0x8B, 0x3F, 0x20, 0xE9, -0x41, 0x3C, 0x41, 0xAD, -0x49, 0x3C, 0x49, 0xAD, + 0x41, 0x3C, 0x41, 0xAD, + 0x49, 0x3C, 0x49, 0xAD, -0x10, 0xCC, 0x10, 0xCD, -0x08, 0xCC, 0x08, 0xCD, + 0x10, 0xCC, 0x10, 0xCD, + 0x08, 0xCC, 0x08, 0xCD, -0xB9, 0x41, 0x49, 0xBB, -0x1F, 0xF0, 0x41, 0xCD, + 0xB9, 0x41, 0x49, 0xBB, + 0x1F, 0xF0, 0x41, 0xCD, -0x51, 0x3C, 0x51, 0xAD, -0x00, 0x98, 0x80, 0xE9, + 0x51, 0x3C, 0x51, 0xAD, + 0x00, 0x98, 0x80, 0xE9, -0x72, 0x80, 0x07, 0xEA, -0x24, 0x1F, 0x20, 0xE9, + 0x72, 0x80, 0x07, 0xEA, + 0x24, 0x1F, 0x20, 0xE9, -0x15, 0x41, 0x49, 0xBD, -0x1D, 0x41, 0x51, 0xBD, + 0x15, 0x41, 0x49, 0xBD, + 0x1D, 0x41, 0x51, 0xBD, -0x2E, 0x41, 0x2A, 0xB8, -0x34, 0x53, 0xA0, 0xE8, + 0x2E, 0x41, 0x2A, 0xB8, + 0x34, 0x53, 0xA0, 0xE8, -0x15, 0x30, -0x1D, 0x30, -0x58, 0xE3, -0x00, 0xE0, + 0x15, 0x30, + 0x1D, 0x30, + 0x58, 0xE3, + 0x00, 0xE0, -0xB5, 0x40, 0x48, 0xBD, -0x3D, 0x40, 0x50, 0xBD, + 0xB5, 0x40, 0x48, 0xBD, + 0x3D, 0x40, 0x50, 0xBD, -0x24, 0x43, 0xA0, 0xE8, -0x2C, 0x4B, 0xA0, 0xE8, + 0x24, 0x43, 0xA0, 0xE8, + 0x2C, 0x4B, 0xA0, 0xE8, -0x15, 0x72, -0x09, 0xE3, -0x00, 0xE0, -0x1D, 0x72, + 0x15, 0x72, + 0x09, 0xE3, + 0x00, 0xE0, + 0x1D, 0x72, -0x35, 0x30, -0xB5, 0x30, -0xBD, 0x30, -0x3D, 0x30, + 0x35, 0x30, + 0xB5, 0x30, + 0xBD, 0x30, + 0x3D, 0x30, -0x9C, 0x97, 0x57, 0x9F, -0x00, 0x80, 0x00, 0xE8, + 0x9C, 0x97, 0x57, 0x9F, + 0x00, 0x80, 0x00, 0xE8, -0x6C, 0x64, 0xC8, 0xEC, -0x98, 0xE1, -0xB5, 0x05, + 0x6C, 0x64, 0xC8, 0xEC, + 0x98, 0xE1, + 0xB5, 0x05, -0xBD, 0x05, -0x2E, 0x30, -0x32, 0xC0, 0xA0, 0xE8, + 0xBD, 0x05, + 0x2E, 0x30, + 0x32, 0xC0, 0xA0, 0xE8, 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0x50, 0xBD, + 0x35, 0x40, 0x48, 0xBD, + 0x3D, 0x40, 0x50, 0xBD, -0x00, 0x80, 0x00, 0xE8, -0x25, 0x30, -0x2D, 0x30, + 0x00, 0x80, 0x00, 0xE8, + 0x25, 0x30, + 0x2D, 0x30, -0x35, 0x30, -0xB5, 0x30, -0xBD, 0x30, -0x3D, 0x30, + 0x35, 0x30, + 0xB5, 0x30, + 0xBD, 0x30, + 0x3D, 0x30, -0x9C, 0xA7, 0x5B, 0x9F, -0x00, 0x80, 0x00, 0xE8, + 0x9C, 0xA7, 0x5B, 0x9F, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x84, 0xFF, 0x0A, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x84, 0xFF, 0x0A, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0xC9, 0x41, 0xC8, 0xEC, -0x42, 0xE1, -0x00, 0xE0, + 0xC9, 0x41, 0xC8, 0xEC, + 0x42, 0xE1, + 0x00, 0xE0, -0x82, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x82, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x7F, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x7F, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgza[] = { -0x00, 0x98, 0xA0, 0xE9, -0x40, 0x40, 0xD8, 0xEC, + 0x00, 0x98, 0xA0, 0xE9, + 0x40, 0x40, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x1F, 0xD7, 0x18, 0xBD, -0x3F, 0xD7, 0x22, 0xBD, + 0x1F, 0xD7, 0x18, 0xBD, + 0x3F, 0xD7, 0x22, 0xBD, -0x81, 0x04, -0x89, 0x04, -0x01, 0x04, -0x09, 0x04, + 0x81, 0x04, + 0x89, 0x04, + 0x01, 0x04, + 0x09, 0x04, -0xC9, 0x41, 0xC0, 0xEC, -0x11, 0x04, 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0x00, 0xE8, + 0x73, 0xFF, 0x0A, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0xC9, 0x41, 0xC8, 0xEC, -0x42, 0xE1, -0x00, 0xE0, + 0xC9, 0x41, 0xC8, 0xEC, + 0x42, 0xE1, + 0x00, 0xE0, -0x71, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x71, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x6E, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x6E, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgzf[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 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0x9F, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x77, 0xFF, 0x0A, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x77, 0xFF, 0x0A, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0xC9, 0x41, 0xC8, 0xEC, -0x42, 0xE1, -0x00, 0xE0, + 0xC9, 0x41, 0xC8, 0xEC, + 0x42, 0xE1, + 0x00, 0xE0, -0x75, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x75, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x72, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x72, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgzs[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 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0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x66, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgzsa[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 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0x00, 0x80, 0x00, 0xE8, -0xC9, 0x41, 0xC8, 0xEC, -0x42, 0xE1, -0x00, 0xE0, + 0xC9, 0x41, 0xC8, 0xEC, + 0x42, 0xE1, + 0x00, 0xE0, -0x65, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x65, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x62, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x62, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgzsaf[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 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0x39, 0x20, 0xE9, -0x16, 0x28, 0x20, 0xE9, -0x1D, 0x3B, 0x20, 0xE9, + 0x16, 0x28, 0x20, 0xE9, + 0x1D, 0x3B, 0x20, 0xE9, -0x1E, 0x2B, 0x20, 0xE9, -0x2B, 0x32, 0x20, 0xE9, + 0x1E, 0x2B, 0x20, 0xE9, + 0x2B, 0x32, 0x20, 0xE9, -0x1C, 0x23, 0x20, 0xE9, -0x57, 0x36, 0x20, 0xE9, + 0x1C, 0x23, 0x20, 0xE9, + 0x57, 0x36, 0x20, 0xE9, -0x00, 0x80, 0xA0, 0xE9, -0x40, 0x40, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x40, 0x40, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x90, 0xE2, -0x00, 0xE0, + 0xFF, 0x80, 0xC0, 0xE9, + 0x90, 0xE2, + 0x00, 0xE0, -0x63, 0xFF, 0x20, 0xEA, -0x19, 0xC8, 0xC1, 0xCD, + 0x63, 0xFF, 0x20, 0xEA, + 0x19, 0xC8, 0xC1, 0xCD, -0x1F, 0xD7, 0x18, 0xBD, -0x3F, 0xD7, 0x22, 0xBD, + 0x1F, 0xD7, 0x18, 0xBD, + 0x3F, 0xD7, 0x22, 0xBD, -0x9F, 0x41, 0x49, 0xBD, -0x00, 0x80, 0x00, 0xE8, + 0x9F, 0x41, 0x49, 0xBD, + 0x00, 0x80, 0x00, 0xE8, -0x25, 0x41, 0x49, 0xBD, -0x2D, 0x41, 0x51, 0xBD, + 0x25, 0x41, 0x49, 0xBD, + 0x2D, 0x41, 0x51, 0xBD, -0x0D, 0x80, 0x07, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x0D, 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-0x42, 0xE1, -0x00, 0xE0, + 0xC9, 0x41, 0xC8, 0xEC, + 0x42, 0xE1, + 0x00, 0xE0, -0x60, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x60, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x5D, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x5D, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgzsf[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 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0xE9, + 0x1F, 0x62, 0x57, 0x9F, -0x0D, 0x20, -0x05, 0x20, -0x2F, 0xC0, 0x21, 0xC6, + 0x0D, 0x20, + 0x05, 0x20, + 0x2F, 0xC0, 0x21, 0xC6, -0x3F, 0x2F, 0x5D, 0x9F, -0x00, 0xE0, -0x0F, 0x20, + 0x3F, 0x2F, 0x5D, 0x9F, + 0x00, 0xE0, + 0x0F, 0x20, -0x17, 0x50, 0x56, 0x9F, -0xA5, 0x37, 0x4F, 0xE9, + 0x17, 0x50, 0x56, 0x9F, + 0xA5, 0x37, 0x4F, 0xE9, -0x06, 0xC0, 0x21, 0xC4, -0x0F, 0x17, 0x0F, 0xAF, + 0x06, 0xC0, 0x21, 0xC4, + 0x0F, 0x17, 0x0F, 0xAF, -0x37, 0x0F, 0x5C, 0x9F, -0x00, 0x80, 0x00, 0xE8, + 0x37, 0x0F, 0x5C, 0x9F, + 0x00, 0x80, 0x00, 0xE8, -0x2F, 0x20, -0x00, 0xE0, -0xA3, 0x80, 0x4F, 0xE9, + 0x2F, 0x20, + 0x00, 0xE0, + 0xA3, 0x80, 0x4F, 0xE9, -0x06, 0x20, -0x00, 0xE0, -0x1F, 0x26, 0x1F, 0xDF, + 0x06, 0x20, + 0x00, 0xE0, + 0x1F, 0x26, 0x1F, 0xDF, -0x17, 0x26, 0x17, 0xDF, -0x35, 0x17, 0x4F, 0xE9, + 0x17, 0x26, 0x17, 0xDF, + 0x35, 0x17, 0x4F, 0xE9, -0xA1, 0x1F, 0x4F, 0xE9, -0xA2, 0x3F, 0x4F, 0xE9, + 0xA1, 0x1F, 0x4F, 0xE9, + 0xA2, 0x3F, 0x4F, 0xE9, -0x06, 0x06, 0x1F, 0xAF, -0x39, 0x37, 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0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x67, 0xFF, 0x0A, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x67, 0xFF, 0x0A, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0xC9, 0x41, 0xC8, 0xEC, -0x42, 0xE1, -0x00, 0xE0, + 0xC9, 0x41, 0xC8, 0xEC, + 0x42, 0xE1, + 0x00, 0xE0, -0x65, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x65, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x62, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x62, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g400_t2gz[] = { -0x00, 0x8A, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x8A, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x0A, 0x40, 0x50, 0xBF, -0x2A, 0x40, 0x60, 0xBF, + 0x0A, 0x40, 0x50, 0xBF, + 0x2A, 0x40, 0x60, 0xBF, -0x32, 0x41, 0x51, 0xBF, -0x3A, 0x41, 0x61, 0xBF, + 0x32, 0x41, 0x51, 0xBF, + 0x3A, 0x41, 0x61, 0xBF, -0xC3, 0x6B, -0xD3, 0x6B, -0x00, 0x8A, 0x98, 0xE9, + 0xC3, 0x6B, + 0xD3, 0x6B, + 0x00, 0x8A, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 0xE2, + 0x41, 0x04, -0x7B, 0x43, 0xA0, 0xE8, -0x73, 0x53, 0xA0, 0xE8, + 0x7B, 0x43, 0xA0, 0xE8, + 0x73, 0x53, 0xA0, 0xE8, -0xAD, 0xEE, 0x23, 0x9F, -0x00, 0xE0, -0x51, 0x04, + 0xAD, 0xEE, 0x23, 0x9F, + 0x00, 0xE0, + 0x51, 0x04, -0x90, 0xE2, -0x61, 0x04, -0x31, 0x46, 0xB1, 0xE8, + 0x90, 0xE2, + 0x61, 0x04, + 0x31, 0x46, 0xB1, 0xE8, -0x51, 0x41, 0xE0, 0xEC, -0x39, 0x67, 0xB1, 0xE8, + 0x51, 0x41, 0xE0, 0xEC, + 0x39, 0x67, 0xB1, 0xE8, -0x00, 0x04, -0x46, 0xE2, -0x73, 0x63, 0xA0, 0xE8, + 0x00, 0x04, + 0x46, 0xE2, + 0x73, 0x63, 0xA0, 0xE8, -0x61, 0x41, 0xE0, 0xEC, -0x31, 0x00, -0x39, 0x00, + 0x61, 0x41, 0xE0, 0xEC, + 0x31, 0x00, + 0x39, 0x00, -0x78, 0x80, 0x15, 0xEA, -0x10, 0x04, -0x20, 0x04, + 0x78, 0x80, 0x15, 0xEA, + 0x10, 0x04, + 0x20, 0x04, -0x61, 0x51, 0xE0, 0xEC, -0x2F, 0x41, 0x60, 0xEA, + 0x61, 0x51, 0xE0, 0xEC, + 0x2F, 0x41, 0x60, 0xEA, -0x31, 0x20, -0x39, 0x20, -0x1F, 0x42, 0xA0, 0xE8, + 0x31, 0x20, + 0x39, 0x20, + 0x1F, 0x42, 0xA0, 0xE8, -0x2A, 0x42, 0x52, 0xBF, -0x0F, 0x52, 0xA0, 0xE8, + 0x2A, 0x42, 0x52, 0xBF, + 0x0F, 0x52, 0xA0, 0xE8, -0x1A, 0x42, 0x62, 0xBF, -0x1E, 0x51, 0x60, 0xEA, + 0x1A, 0x42, 0x62, 0xBF, + 0x1E, 0x51, 0x60, 0xEA, -0x73, 0x7B, 0xC8, 0xEC, -0x0E, 0x61, 0x60, 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0x00, 0xE8, + 0xBA, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x58, 0x33, 0x58, 0xCF, -0x69, 0x3B, 0x69, 0xCF, + 0x58, 0x33, 0x58, 0xCF, + 0x69, 0x3B, 0x69, 0xCF, -0x79, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x79, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_t2gzaf[] = { -0x00, 0x8A, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x8A, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x0A, 0x40, 0x50, 0xBF, -0x2A, 0x40, 0x60, 0xBF, + 0x0A, 0x40, 0x50, 0xBF, + 0x2A, 0x40, 0x60, 0xBF, -0x32, 0x41, 0x51, 0xBF, -0x3A, 0x41, 0x61, 0xBF, + 0x32, 0x41, 0x51, 0xBF, + 0x3A, 0x41, 0x61, 0xBF, -0xC3, 0x6B, -0xD3, 0x6B, -0x00, 0x8A, 0x98, 0xE9, + 0xC3, 0x6B, + 0xD3, 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0xCF, + 0x69, 0x3B, 0x69, 0xCF, -0x74, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x74, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_t2gzf[] = { -0x00, 0x8A, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x8A, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x0A, 0x40, 0x50, 0xBF, -0x2A, 0x40, 0x60, 0xBF, + 0x0A, 0x40, 0x50, 0xBF, + 0x2A, 0x40, 0x60, 0xBF, -0x32, 0x41, 0x51, 0xBF, -0x3A, 0x41, 0x61, 0xBF, + 0x32, 0x41, 0x51, 0xBF, + 0x3A, 0x41, 0x61, 0xBF, -0xC3, 0x6B, -0xD3, 0x6B, -0x00, 0x8A, 0x98, 0xE9, + 0xC3, 0x6B, + 0xD3, 0x6B, + 0x00, 0x8A, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 0xE2, + 0x41, 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0xBD, -0x3B, 0xD7, 0x1B, 0xBD, + 0x33, 0xD7, 0x0B, 0xBD, + 0x3B, 0xD7, 0x1B, 0xBD, -0x48, 0x80, 0x48, 0xCF, -0x59, 0x80, 0x59, 0xCF, + 0x48, 0x80, 0x48, 0xCF, + 0x59, 0x80, 0x59, 0xCF, -0x68, 0x33, 0x68, 0xCF, -0x49, 0x3B, 0x49, 0xCF, + 0x68, 0x33, 0x68, 0xCF, + 0x49, 0x3B, 0x49, 0xCF, -0xBB, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0xBB, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x58, 0x33, 0x58, 0xCF, -0x69, 0x3B, 0x69, 0xCF, + 0x58, 0x33, 0x58, 0xCF, + 0x69, 0x3B, 0x69, 0xCF, -0x78, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x78, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_t2gzs[] = { -0x00, 0x8A, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x8A, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 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0xEC, + 0x3C, 0xD7, 0x3C, 0xAD, + 0x2C, 0x80, 0x60, 0xEC, -0x0B, 0x2B, 0xDE, 0xE8, -0x1B, 0x80, 0xDE, 0xE8, + 0x0B, 0x2B, 0xDE, 0xE8, + 0x1B, 0x80, 0xDE, 0xE8, -0x34, 0x80, 0x34, 0xBD, -0x3C, 0x80, 0x3C, 0xBD, + 0x34, 0x80, 0x34, 0xBD, + 0x3C, 0x80, 0x3C, 0xBD, -0x33, 0xD7, 0x0B, 0xBD, -0x3B, 0xD7, 0x1B, 0xBD, + 0x33, 0xD7, 0x0B, 0xBD, + 0x3B, 0xD7, 0x1B, 0xBD, -0x48, 0x80, 0x48, 0xCF, -0x59, 0x80, 0x59, 0xCF, + 0x48, 0x80, 0x48, 0xCF, + 0x59, 0x80, 0x59, 0xCF, -0x68, 0x33, 0x68, 0xCF, -0x49, 0x3B, 0x49, 0xCF, + 0x68, 0x33, 0x68, 0xCF, + 0x49, 0x3B, 0x49, 0xCF, -0xB2, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0xB2, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x58, 0x33, 0x58, 0xCF, -0x69, 0x3B, 0x69, 0xCF, + 0x58, 0x33, 0x58, 0xCF, + 0x69, 0x3B, 0x69, 0xCF, -0x70, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x70, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_t2gzsa[] = { -0x00, 0x8A, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x8A, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x0A, 0x40, 0x50, 0xBF, -0x2A, 0x40, 0x60, 0xBF, + 0x0A, 0x40, 0x50, 0xBF, + 0x2A, 0x40, 0x60, 0xBF, -0x32, 0x41, 0x51, 0xBF, -0x3A, 0x41, 0x61, 0xBF, + 0x32, 0x41, 0x51, 0xBF, + 0x3A, 0x41, 0x61, 0xBF, -0xC3, 0x6B, -0xD3, 0x6B, -0x00, 0x8A, 0x98, 0xE9, + 0xC3, 0x6B, + 0xD3, 0x6B, + 0x00, 0x8A, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 0xE2, + 0x41, 0x04, -0x7B, 0x43, 0xA0, 0xE8, -0x73, 0x53, 0xA0, 0xE8, + 0x7B, 0x43, 0xA0, 0xE8, + 0x73, 0x53, 0xA0, 0xE8, -0xAD, 0xEE, 0x23, 0x9F, -0x00, 0xE0, -0x51, 0x04, + 0xAD, 0xEE, 0x23, 0x9F, + 0x00, 0xE0, + 0x51, 0x04, -0x90, 0xE2, -0x61, 0x04, -0x31, 0x46, 0xB1, 0xE8, + 0x90, 0xE2, + 0x61, 0x04, + 0x31, 0x46, 0xB1, 0xE8, -0x51, 0x41, 0xE0, 0xEC, -0x39, 0x67, 0xB1, 0xE8, + 0x51, 0x41, 0xE0, 0xEC, + 0x39, 0x67, 0xB1, 0xE8, -0x00, 0x04, -0x46, 0xE2, -0x73, 0x63, 0xA0, 0xE8, + 0x00, 0x04, + 0x46, 0xE2, + 0x73, 0x63, 0xA0, 0xE8, -0x61, 0x41, 0xE0, 0xEC, -0x31, 0x00, -0x39, 0x00, + 0x61, 0x41, 0xE0, 0xEC, + 0x31, 0x00, + 0x39, 0x00, -0x8A, 0x80, 0x15, 0xEA, -0x10, 0x04, -0x20, 0x04, + 0x8A, 0x80, 0x15, 0xEA, + 0x10, 0x04, + 0x20, 0x04, -0x61, 0x51, 0xE0, 0xEC, -0x2F, 0x41, 0x60, 0xEA, + 0x61, 0x51, 0xE0, 0xEC, + 0x2F, 0x41, 0x60, 0xEA, -0x31, 0x20, -0x39, 0x20, -0x1F, 0x42, 0xA0, 0xE8, + 0x31, 0x20, + 0x39, 0x20, + 0x1F, 0x42, 0xA0, 0xE8, -0x2A, 0x42, 0x52, 0xBF, -0x0F, 0x52, 0xA0, 0xE8, + 0x2A, 0x42, 0x52, 0xBF, + 0x0F, 0x52, 0xA0, 0xE8, -0x1A, 0x42, 0x62, 0xBF, -0x1E, 0x51, 0x60, 0xEA, + 0x1A, 0x42, 0x62, 0xBF, + 0x1E, 0x51, 0x60, 0xEA, -0x73, 0x7B, 0xC8, 0xEC, -0x0E, 0x61, 0x60, 0xEA, + 0x73, 0x7B, 0xC8, 0xEC, + 0x0E, 0x61, 0x60, 0xEA, -0x32, 0x40, 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warp_g400_t2gzsf[] = { -0x00, 0x8A, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x8A, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x0A, 0x40, 0x50, 0xBF, -0x2A, 0x40, 0x60, 0xBF, + 0x0A, 0x40, 0x50, 0xBF, + 0x2A, 0x40, 0x60, 0xBF, -0x32, 0x41, 0x51, 0xBF, -0x3A, 0x41, 0x61, 0xBF, + 0x32, 0x41, 0x51, 0xBF, + 0x3A, 0x41, 0x61, 0xBF, -0xC3, 0x6B, -0xD3, 0x6B, -0x00, 0x8A, 0x98, 0xE9, + 0xC3, 0x6B, + 0xD3, 0x6B, + 0x00, 0x8A, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 0xE2, + 0x41, 0x04, -0x7B, 0x43, 0xA0, 0xE8, -0x73, 0x53, 0xA0, 0xE8, + 0x7B, 0x43, 0xA0, 0xE8, + 0x73, 0x53, 0xA0, 0xE8, -0xAD, 0xEE, 0x23, 0x9F, -0x00, 0xE0, -0x51, 0x04, + 0xAD, 0xEE, 0x23, 0x9F, + 0x00, 0xE0, + 0x51, 0x04, -0x90, 0xE2, -0x61, 0x04, -0x31, 0x46, 0xB1, 0xE8, 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0x47, 0xCF, -0xD6, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0xD6, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x4E, 0x33, 0x4E, 0xCF, -0x57, 0x3B, 0x57, 0xCF, + 0x4E, 0x33, 0x4E, 0xCF, + 0x57, 0x3B, 0x57, 0xCF, -0x9D, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x9D, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgza[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 0x40, 0x50, 0xBF, + 0x22, 0x40, 0x48, 0xBF, + 0x2A, 0x40, 0x50, 0xBF, -0x32, 0x41, 0x49, 0xBF, -0x3A, 0x41, 0x51, 0xBF, + 0x32, 0x41, 0x49, 0xBF, + 0x3A, 0x41, 0x51, 0xBF, -0xC3, 0x6B, -0xCB, 0x6B, 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+ 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgzf[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 0x40, 0x50, 0xBF, + 0x22, 0x40, 0x48, 0xBF, + 0x2A, 0x40, 0x50, 0xBF, -0x32, 0x41, 0x49, 0xBF, -0x3A, 0x41, 0x51, 0xBF, + 0x32, 0x41, 0x49, 0xBF, + 0x3A, 0x41, 0x51, 0xBF, -0xC3, 0x6B, -0xCB, 0x6B, -0x00, 0x88, 0x98, 0xE9, + 0xC3, 0x6B, + 0xCB, 0x6B, + 0x00, 0x88, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 0xE2, + 0x41, 0x04, -0x7B, 0x43, 0xA0, 0xE8, -0x73, 0x4B, 0xA0, 0xE8, + 0x7B, 0x43, 0xA0, 0xE8, + 0x73, 0x4B, 0xA0, 0xE8, -0xAD, 0xEE, 0x29, 0x9F, -0x00, 0xE0, -0x49, 0x04, + 0xAD, 0xEE, 0x29, 0x9F, + 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0x57, 0xCF, -0x98, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x98, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgzs[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 0x40, 0x50, 0xBF, + 0x22, 0x40, 0x48, 0xBF, + 0x2A, 0x40, 0x50, 0xBF, -0x32, 0x41, 0x49, 0xBF, -0x3A, 0x41, 0x51, 0xBF, + 0x32, 0x41, 0x49, 0xBF, + 0x3A, 0x41, 0x51, 0xBF, -0xC3, 0x6B, -0xCB, 0x6B, -0x00, 0x88, 0x98, 0xE9, + 0xC3, 0x6B, + 0xCB, 0x6B, + 0x00, 0x88, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 0xE2, + 0x41, 0x04, -0x7B, 0x43, 0xA0, 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0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x90, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgzsa[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 0x40, 0x50, 0xBF, + 0x22, 0x40, 0x48, 0xBF, + 0x2A, 0x40, 0x50, 0xBF, -0x32, 0x41, 0x49, 0xBF, -0x3A, 0x41, 0x51, 0xBF, + 0x32, 0x41, 0x49, 0xBF, + 0x3A, 0x41, 0x51, 0xBF, -0xC3, 0x6B, -0xCB, 0x6B, -0x00, 0x88, 0x98, 0xE9, + 0xC3, 0x6B, + 0xCB, 0x6B, + 0x00, 0x88, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 0xE2, + 0x41, 0x04, -0x7B, 0x43, 0xA0, 0xE8, -0x73, 0x4B, 0xA0, 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0xD7, 0x23, 0xBD, + 0x33, 0xD7, 0x1C, 0xBD, + 0x3B, 0xD7, 0x23, 0xBD, -0x46, 0x80, 0x46, 0xCF, -0x4F, 0x80, 0x4F, 0xCF, + 0x46, 0x80, 0x46, 0xCF, + 0x4F, 0x80, 0x4F, 0xCF, -0x56, 0x33, 0x56, 0xCF, -0x47, 0x3B, 0x47, 0xCF, + 0x56, 0x33, 0x56, 0xCF, + 0x47, 0x3B, 0x47, 0xCF, -0xC5, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0xC5, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x4E, 0x33, 0x4E, 0xCF, -0x57, 0x3B, 0x57, 0xCF, + 0x4E, 0x33, 0x4E, 0xCF, + 0x57, 0x3B, 0x57, 0xCF, -0x8B, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x8B, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgzsaf[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 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-0x4F, 0x80, 0x4F, 0xCF, + 0x46, 0x80, 0x46, 0xCF, + 0x4F, 0x80, 0x4F, 0xCF, -0x56, 0x33, 0x56, 0xCF, -0x47, 0x3B, 0x47, 0xCF, + 0x56, 0x33, 0x56, 0xCF, + 0x47, 0x3B, 0x47, 0xCF, -0xC1, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0xC1, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x4E, 0x33, 0x4E, 0xCF, -0x57, 0x3B, 0x57, 0xCF, + 0x4E, 0x33, 0x4E, 0xCF, + 0x57, 0x3B, 0x57, 0xCF, -0x87, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x87, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgzsf[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 0x40, 0x50, 0xBF, + 0x22, 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+ 0x2A, 0x45, 0x4D, 0xB2, + 0x1A, 0x45, 0x55, 0xB2, -0x0A, 0x45, 0x4D, 0xB4, -0x02, 0x45, 0x55, 0xB4, + 0x0A, 0x45, 0x4D, 0xB4, + 0x02, 0x45, 0x55, 0xB4, -0x27, 0xCF, 0x75, 0xC6, -0x2A, 0x20, -0x1A, 0x20, + 0x27, 0xCF, 0x75, 0xC6, + 0x2A, 0x20, + 0x1A, 0x20, -0xA7, 0x30, 0x4F, 0xE9, -0x0A, 0x20, -0x02, 0x20, + 0xA7, 0x30, 0x4F, 0xE9, + 0x0A, 0x20, + 0x02, 0x20, -0x31, 0x53, 0x2F, 0x9F, -0x31, 0x27, 0x20, 0xE9, + 0x31, 0x53, 0x2F, 0x9F, + 0x31, 0x27, 0x20, 0xE9, -0x39, 0xE5, 0x2C, 0x9F, -0xA8, 0x38, 0x4F, 0xE9, + 0x39, 0xE5, 0x2C, 0x9F, + 0xA8, 0x38, 0x4F, 0xE9, -0x2A, 0x45, 0x4D, 0xB6, -0x1A, 0x45, 0x55, 0xB6, + 0x2A, 0x45, 0x4D, 0xB6, + 0x1A, 0x45, 0x55, 0xB6, -0x30, 0x50, 0x2E, 0x9F, -0x36, 0x31, 0x4F, 0xE9, + 0x30, 0x50, 0x2E, 0x9F, + 0x36, 0x31, 0x4F, 0xE9, -0x38, 0x21, 0x2C, 0x9F, -0x37, 0x39, 0x4F, 0xE9, + 0x38, 0x21, 0x2C, 0x9F, + 0x37, 0x39, 0x4F, 0xE9, -0x00, 0x80, 0x00, 0xE8, -0x2A, 0x20, -0x1A, 0x20, + 0x00, 0x80, 0x00, 0xE8, + 0x2A, 0x20, + 0x1A, 0x20, -0x2A, 0x46, 0x4E, 0xBF, -0x1A, 0x46, 0x56, 0xBF, + 0x2A, 0x46, 0x4E, 0xBF, + 0x1A, 0x46, 0x56, 0xBF, -0x31, 0x53, 0x2F, 0x9F, -0xA4, 0x31, 0x4F, 0xE9, + 0x31, 0x53, 0x2F, 0x9F, + 0xA4, 0x31, 0x4F, 0xE9, -0x39, 0xE5, 0x2C, 0x9F, -0xA5, 0x39, 0x4F, 0xE9, + 0x39, 0xE5, 0x2C, 0x9F, + 0xA5, 0x39, 0x4F, 0xE9, -0x0A, 0x47, 0x4F, 0xBF, -0x02, 0x47, 0x57, 0xBF, + 0x0A, 0x47, 0x4F, 0xBF, + 0x02, 0x47, 0x57, 0xBF, -0x31, 0x53, 0x2F, 0x9F, -0xA1, 0x30, 0x4F, 0xE9, + 0x31, 0x53, 0x2F, 0x9F, + 0xA1, 0x30, 0x4F, 0xE9, -0x39, 0xE5, 0x2C, 0x9F, -0xA2, 0x38, 0x4F, 0xE9, + 0x39, 0xE5, 0x2C, 0x9F, + 0xA2, 0x38, 0x4F, 0xE9, -0x2A, 0x43, 0x4B, 0xBF, -0x1A, 0x43, 0x53, 0xBF, + 0x2A, 0x43, 0x4B, 0xBF, + 0x1A, 0x43, 0x53, 0xBF, -0x30, 0x50, 0x2E, 0x9F, -0x35, 0x31, 0x4F, 0xE9, + 0x30, 0x50, 0x2E, 0x9F, + 0x35, 0x31, 0x4F, 0xE9, -0x38, 0x21, 0x2C, 0x9F, -0x39, 0x39, 0x4F, 0xE9, + 0x38, 0x21, 0x2C, 0x9F, + 0x39, 0x39, 0x4F, 0xE9, -0x31, 0x53, 0x2F, 0x9F, -0x80, 0x31, 0x57, 0xE9, + 0x31, 0x53, 0x2F, 0x9F, + 0x80, 0x31, 0x57, 0xE9, -0x39, 0xE5, 0x2C, 0x9F, -0x81, 0x39, 0x57, 0xE9, + 0x39, 0xE5, 0x2C, 0x9F, + 0x81, 0x39, 0x57, 0xE9, -0x37, 0x48, 0x50, 0xBD, -0x8A, 0x36, 0x20, 0xE9, + 0x37, 0x48, 0x50, 0xBD, + 0x8A, 0x36, 0x20, 0xE9, -0x86, 0x76, 0x57, 0xE9, -0x8B, 0x3E, 0x20, 0xE9, + 0x86, 0x76, 0x57, 0xE9, + 0x8B, 0x3E, 0x20, 0xE9, -0x82, 0x30, 0x57, 0xE9, -0x87, 0x77, 0x57, 0xE9, + 0x82, 0x30, 0x57, 0xE9, + 0x87, 0x77, 0x57, 0xE9, -0x83, 0x38, 0x57, 0xE9, -0x35, 0x49, 0x51, 0xBD, + 0x83, 0x38, 0x57, 0xE9, + 0x35, 0x49, 0x51, 0xBD, -0x84, 0x31, 0x5E, 0xE9, -0x30, 0x1F, 0x5F, 0xE9, + 0x84, 0x31, 0x5E, 0xE9, + 0x30, 0x1F, 0x5F, 0xE9, -0x85, 0x39, 0x5E, 0xE9, -0x57, 0x25, 0x20, 0xE9, + 0x85, 0x39, 0x5E, 0xE9, + 0x57, 0x25, 0x20, 0xE9, -0x2B, 0x48, 0x20, 0xE9, -0x1D, 0x37, 0xE1, 0xEA, + 0x2B, 0x48, 0x20, 0xE9, + 0x1D, 0x37, 0xE1, 0xEA, -0x1E, 0x35, 0xE1, 0xEA, -0x00, 0xE0, -0x26, 0x77, + 0x1E, 0x35, 0xE1, 0xEA, + 0x00, 0xE0, + 0x26, 0x77, -0x24, 0x49, 0x20, 0xE9, -0x9D, 0xFF, 0x20, 0xEA, + 0x24, 0x49, 0x20, 0xE9, + 0x9D, 0xFF, 0x20, 0xEA, -0x16, 0x26, 0x20, 0xE9, -0x57, 0x2E, 0xBF, 0xEA, + 0x16, 0x26, 0x20, 0xE9, + 0x57, 0x2E, 0xBF, 0xEA, -0x1C, 0x46, 0xA0, 0xE8, -0x23, 0x4E, 0xA0, 0xE8, + 0x1C, 0x46, 0xA0, 0xE8, + 0x23, 0x4E, 0xA0, 0xE8, -0x2B, 0x56, 0xA0, 0xE8, -0x1D, 0x47, 0xA0, 0xE8, + 0x2B, 0x56, 0xA0, 0xE8, + 0x1D, 0x47, 0xA0, 0xE8, -0x24, 0x4F, 0xA0, 0xE8, -0x2C, 0x57, 0xA0, 0xE8, + 0x24, 0x4F, 0xA0, 0xE8, + 0x2C, 0x57, 0xA0, 0xE8, -0x1C, 0x00, -0x23, 0x00, -0x2B, 0x00, -0x00, 0xE0, + 0x1C, 0x00, + 0x23, 0x00, + 0x2B, 0x00, + 0x00, 0xE0, -0x1D, 0x00, -0x24, 0x00, -0x2C, 0x00, -0x00, 0xE0, + 0x1D, 0x00, + 0x24, 0x00, + 0x2C, 0x00, + 0x00, 0xE0, -0x1C, 0x65, -0x23, 0x65, -0x2B, 0x65, -0x00, 0xE0, + 0x1C, 0x65, + 0x23, 0x65, + 0x2B, 0x65, + 0x00, 0xE0, -0x1D, 0x65, -0x24, 0x65, -0x2C, 0x65, -0x00, 0xE0, + 0x1D, 0x65, + 0x24, 0x65, + 0x2C, 0x65, + 0x00, 0xE0, -0x1C, 0x23, 0x60, 0xEC, -0x36, 0xD7, 0x36, 0xAD, + 0x1C, 0x23, 0x60, 0xEC, + 0x36, 0xD7, 0x36, 0xAD, -0x2B, 0x80, 0x60, 0xEC, -0x1D, 0x24, 0x60, 0xEC, + 0x2B, 0x80, 0x60, 0xEC, + 0x1D, 0x24, 0x60, 0xEC, -0x3E, 0xD7, 0x3E, 0xAD, -0x2C, 0x80, 0x60, 0xEC, + 0x3E, 0xD7, 0x3E, 0xAD, + 0x2C, 0x80, 0x60, 0xEC, -0x1C, 0x2B, 0xDE, 0xE8, -0x23, 0x80, 0xDE, 0xE8, + 0x1C, 0x2B, 0xDE, 0xE8, + 0x23, 0x80, 0xDE, 0xE8, -0x36, 0x80, 0x36, 0xBD, -0x3E, 0x80, 0x3E, 0xBD, + 0x36, 0x80, 0x36, 0xBD, + 0x3E, 0x80, 0x3E, 0xBD, -0x33, 0xD7, 0x1C, 0xBD, -0x3B, 0xD7, 0x23, 0xBD, + 0x33, 0xD7, 0x1C, 0xBD, + 0x3B, 0xD7, 0x23, 0xBD, -0x46, 0x80, 0x46, 0xCF, -0x4F, 0x80, 0x4F, 0xCF, + 0x46, 0x80, 0x46, 0xCF, + 0x4F, 0x80, 0x4F, 0xCF, -0x56, 0x33, 0x56, 0xCF, -0x47, 0x3B, 0x47, 0xCF, + 0x56, 0x33, 0x56, 0xCF, + 0x47, 0x3B, 0x47, 0xCF, -0xC5, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0xC5, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x4E, 0x33, 0x4E, 0xCF, -0x57, 0x3B, 0x57, 0xCF, + 0x4E, 0x33, 0x4E, 0xCF, + 0x57, 0x3B, 0x57, 0xCF, -0x8B, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x8B, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; diff --git a/shared-core/mga_warp.c b/shared-core/mga_warp.c index 0a3a0cc7..a5d35911 100644 --- a/shared-core/mga_warp.c +++ b/shared-core/mga_warp.c @@ -33,8 +33,7 @@ #include "mga_drv.h" #include "mga_ucode.h" - -#define MGA_WARP_CODE_ALIGN 256 /* in bytes */ +#define MGA_WARP_CODE_ALIGN 256 /* in bytes */ #define WARP_UCODE_SIZE( which ) \ ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN) @@ -48,125 +47,122 @@ do { \ vcbase += WARP_UCODE_SIZE( which ); \ } while (0) - -static unsigned int mga_warp_g400_microcode_size( drm_mga_private_t *dev_priv ) +static unsigned int mga_warp_g400_microcode_size(drm_mga_private_t * dev_priv) { unsigned int size; - size = ( WARP_UCODE_SIZE( warp_g400_tgz ) + - WARP_UCODE_SIZE( warp_g400_tgza ) + - WARP_UCODE_SIZE( warp_g400_tgzaf ) + - WARP_UCODE_SIZE( warp_g400_tgzf ) + - WARP_UCODE_SIZE( warp_g400_tgzs ) + - WARP_UCODE_SIZE( warp_g400_tgzsa ) + - WARP_UCODE_SIZE( warp_g400_tgzsaf ) + - WARP_UCODE_SIZE( warp_g400_tgzsf ) + - WARP_UCODE_SIZE( warp_g400_t2gz ) + - WARP_UCODE_SIZE( warp_g400_t2gza ) + - WARP_UCODE_SIZE( warp_g400_t2gzaf ) + - WARP_UCODE_SIZE( warp_g400_t2gzf ) + - WARP_UCODE_SIZE( warp_g400_t2gzs ) + - WARP_UCODE_SIZE( warp_g400_t2gzsa ) + - WARP_UCODE_SIZE( warp_g400_t2gzsaf ) + - WARP_UCODE_SIZE( warp_g400_t2gzsf ) ); - - size = PAGE_ALIGN( size ); - - DRM_DEBUG( "G400 ucode size = %d bytes\n", size ); + size = (WARP_UCODE_SIZE(warp_g400_tgz) + + WARP_UCODE_SIZE(warp_g400_tgza) + + WARP_UCODE_SIZE(warp_g400_tgzaf) + + WARP_UCODE_SIZE(warp_g400_tgzf) + + WARP_UCODE_SIZE(warp_g400_tgzs) + + WARP_UCODE_SIZE(warp_g400_tgzsa) + + WARP_UCODE_SIZE(warp_g400_tgzsaf) + + WARP_UCODE_SIZE(warp_g400_tgzsf) + + WARP_UCODE_SIZE(warp_g400_t2gz) + + WARP_UCODE_SIZE(warp_g400_t2gza) + + WARP_UCODE_SIZE(warp_g400_t2gzaf) + + WARP_UCODE_SIZE(warp_g400_t2gzf) + + WARP_UCODE_SIZE(warp_g400_t2gzs) + + WARP_UCODE_SIZE(warp_g400_t2gzsa) + + WARP_UCODE_SIZE(warp_g400_t2gzsaf) + + WARP_UCODE_SIZE(warp_g400_t2gzsf)); + + size = PAGE_ALIGN(size); + + DRM_DEBUG("G400 ucode size = %d bytes\n", size); return size; } -static unsigned int mga_warp_g200_microcode_size( drm_mga_private_t *dev_priv ) +static unsigned int mga_warp_g200_microcode_size(drm_mga_private_t * dev_priv) { unsigned int size; - size = ( WARP_UCODE_SIZE( warp_g200_tgz ) + - WARP_UCODE_SIZE( warp_g200_tgza ) + - WARP_UCODE_SIZE( warp_g200_tgzaf ) + - WARP_UCODE_SIZE( warp_g200_tgzf ) + - WARP_UCODE_SIZE( warp_g200_tgzs ) + - WARP_UCODE_SIZE( warp_g200_tgzsa ) + - WARP_UCODE_SIZE( warp_g200_tgzsaf ) + - WARP_UCODE_SIZE( warp_g200_tgzsf ) ); + size = (WARP_UCODE_SIZE(warp_g200_tgz) + + WARP_UCODE_SIZE(warp_g200_tgza) + + WARP_UCODE_SIZE(warp_g200_tgzaf) + + WARP_UCODE_SIZE(warp_g200_tgzf) + + WARP_UCODE_SIZE(warp_g200_tgzs) + + WARP_UCODE_SIZE(warp_g200_tgzsa) + + WARP_UCODE_SIZE(warp_g200_tgzsaf) + + WARP_UCODE_SIZE(warp_g200_tgzsf)); - size = PAGE_ALIGN( size ); + size = PAGE_ALIGN(size); - DRM_DEBUG( "G200 ucode size = %d bytes\n", size ); + DRM_DEBUG("G200 ucode size = %d bytes\n", size); return size; } -static int mga_warp_install_g400_microcode( drm_mga_private_t *dev_priv ) +static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv) { unsigned char *vcbase = dev_priv->warp->handle; unsigned long pcbase = dev_priv->warp->offset; unsigned int size; - size = mga_warp_g400_microcode_size( dev_priv ); - if ( size > dev_priv->warp->size ) { - DRM_ERROR( "microcode too large! (%u > %lu)\n", - size, dev_priv->warp->size ); + size = mga_warp_g400_microcode_size(dev_priv); + if (size > dev_priv->warp->size) { + DRM_ERROR("microcode too large! (%u > %lu)\n", + size, dev_priv->warp->size); return DRM_ERR(ENOMEM); } - memset( dev_priv->warp_pipe_phys, 0, - sizeof(dev_priv->warp_pipe_phys) ); - - WARP_UCODE_INSTALL( warp_g400_tgz, MGA_WARP_TGZ ); - WARP_UCODE_INSTALL( warp_g400_tgzf, MGA_WARP_TGZF ); - WARP_UCODE_INSTALL( warp_g400_tgza, MGA_WARP_TGZA ); - WARP_UCODE_INSTALL( warp_g400_tgzaf, MGA_WARP_TGZAF ); - WARP_UCODE_INSTALL( warp_g400_tgzs, MGA_WARP_TGZS ); - WARP_UCODE_INSTALL( warp_g400_tgzsf, MGA_WARP_TGZSF ); - WARP_UCODE_INSTALL( warp_g400_tgzsa, MGA_WARP_TGZSA ); - WARP_UCODE_INSTALL( warp_g400_tgzsaf, MGA_WARP_TGZSAF ); - - WARP_UCODE_INSTALL( warp_g400_t2gz, MGA_WARP_T2GZ ); - WARP_UCODE_INSTALL( warp_g400_t2gzf, MGA_WARP_T2GZF ); - WARP_UCODE_INSTALL( warp_g400_t2gza, MGA_WARP_T2GZA ); - WARP_UCODE_INSTALL( warp_g400_t2gzaf, MGA_WARP_T2GZAF ); - WARP_UCODE_INSTALL( warp_g400_t2gzs, MGA_WARP_T2GZS ); - WARP_UCODE_INSTALL( warp_g400_t2gzsf, MGA_WARP_T2GZSF ); - WARP_UCODE_INSTALL( warp_g400_t2gzsa, MGA_WARP_T2GZSA ); - WARP_UCODE_INSTALL( warp_g400_t2gzsaf, MGA_WARP_T2GZSAF ); + memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); + + WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ); + WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF); + WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA); + WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF); + WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS); + WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF); + WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA); + WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF); + + WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ); + WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF); + WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA); + WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF); + WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS); + WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF); + WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA); + WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF); return 0; } -static int mga_warp_install_g200_microcode( drm_mga_private_t *dev_priv ) +static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv) { unsigned char *vcbase = dev_priv->warp->handle; unsigned long pcbase = dev_priv->warp->offset; unsigned int size; - size = mga_warp_g200_microcode_size( dev_priv ); - if ( size > dev_priv->warp->size ) { - DRM_ERROR( "microcode too large! (%u > %lu)\n", - size, dev_priv->warp->size ); + size = mga_warp_g200_microcode_size(dev_priv); + if (size > dev_priv->warp->size) { + DRM_ERROR("microcode too large! (%u > %lu)\n", + size, dev_priv->warp->size); return DRM_ERR(ENOMEM); } - memset( dev_priv->warp_pipe_phys, 0, - sizeof(dev_priv->warp_pipe_phys) ); + memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); - WARP_UCODE_INSTALL( warp_g200_tgz, MGA_WARP_TGZ ); - WARP_UCODE_INSTALL( warp_g200_tgzf, MGA_WARP_TGZF ); - WARP_UCODE_INSTALL( warp_g200_tgza, MGA_WARP_TGZA ); - WARP_UCODE_INSTALL( warp_g200_tgzaf, MGA_WARP_TGZAF ); - WARP_UCODE_INSTALL( warp_g200_tgzs, MGA_WARP_TGZS ); - WARP_UCODE_INSTALL( warp_g200_tgzsf, MGA_WARP_TGZSF ); - WARP_UCODE_INSTALL( warp_g200_tgzsa, MGA_WARP_TGZSA ); - WARP_UCODE_INSTALL( warp_g200_tgzsaf, MGA_WARP_TGZSAF ); + WARP_UCODE_INSTALL(warp_g200_tgz, MGA_WARP_TGZ); + WARP_UCODE_INSTALL(warp_g200_tgzf, MGA_WARP_TGZF); + WARP_UCODE_INSTALL(warp_g200_tgza, MGA_WARP_TGZA); + WARP_UCODE_INSTALL(warp_g200_tgzaf, MGA_WARP_TGZAF); + WARP_UCODE_INSTALL(warp_g200_tgzs, MGA_WARP_TGZS); + WARP_UCODE_INSTALL(warp_g200_tgzsf, MGA_WARP_TGZSF); + WARP_UCODE_INSTALL(warp_g200_tgzsa, MGA_WARP_TGZSA); + WARP_UCODE_INSTALL(warp_g200_tgzsaf, MGA_WARP_TGZSAF); return 0; } -int mga_warp_install_microcode( drm_mga_private_t *dev_priv ) +int mga_warp_install_microcode(drm_mga_private_t * dev_priv) { - switch ( dev_priv->chipset ) { + switch (dev_priv->chipset) { case MGA_CARD_TYPE_G400: - return mga_warp_install_g400_microcode( dev_priv ); + return mga_warp_install_g400_microcode(dev_priv); case MGA_CARD_TYPE_G200: - return mga_warp_install_g200_microcode( dev_priv ); + return mga_warp_install_g200_microcode(dev_priv); default: return DRM_ERR(EINVAL); } @@ -174,35 +170,34 @@ int mga_warp_install_microcode( drm_mga_private_t *dev_priv ) #define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE) -int mga_warp_init( drm_mga_private_t *dev_priv ) +int mga_warp_init(drm_mga_private_t * dev_priv) { u32 wmisc; /* FIXME: Get rid of these damned magic numbers... */ - switch ( dev_priv->chipset ) { + switch (dev_priv->chipset) { case MGA_CARD_TYPE_G400: - MGA_WRITE( MGA_WIADDR2, MGA_WMODE_SUSPEND ); - MGA_WRITE( MGA_WGETMSB, 0x00000E00 ); - MGA_WRITE( MGA_WVRTXSZ, 0x00001807 ); - MGA_WRITE( MGA_WACCEPTSEQ, 0x18000000 ); + MGA_WRITE(MGA_WIADDR2, MGA_WMODE_SUSPEND); + MGA_WRITE(MGA_WGETMSB, 0x00000E00); + MGA_WRITE(MGA_WVRTXSZ, 0x00001807); + MGA_WRITE(MGA_WACCEPTSEQ, 0x18000000); break; case MGA_CARD_TYPE_G200: - MGA_WRITE( MGA_WIADDR, MGA_WMODE_SUSPEND ); - MGA_WRITE( MGA_WGETMSB, 0x1606 ); - MGA_WRITE( MGA_WVRTXSZ, 7 ); + MGA_WRITE(MGA_WIADDR, MGA_WMODE_SUSPEND); + MGA_WRITE(MGA_WGETMSB, 0x1606); + MGA_WRITE(MGA_WVRTXSZ, 7); break; default: return DRM_ERR(EINVAL); } - MGA_WRITE( MGA_WMISC, (MGA_WUCODECACHE_ENABLE | - MGA_WMASTER_ENABLE | - MGA_WCACHEFLUSH_ENABLE) ); - wmisc = MGA_READ( MGA_WMISC ); - if ( wmisc != WMISC_EXPECTED ) { - DRM_ERROR( "WARP engine config failed! 0x%x != 0x%x\n", - wmisc, WMISC_EXPECTED ); + MGA_WRITE(MGA_WMISC, (MGA_WUCODECACHE_ENABLE | + MGA_WMASTER_ENABLE | MGA_WCACHEFLUSH_ENABLE)); + wmisc = MGA_READ(MGA_WMISC); + if (wmisc != WMISC_EXPECTED) { + DRM_ERROR("WARP engine config failed! 0x%x != 0x%x\n", + wmisc, WMISC_EXPECTED); return DRM_ERR(EINVAL); } diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c index 172ea258..4246cc7c 100644 --- a/shared-core/r128_cce.c +++ b/shared-core/r128_cce.c @@ -80,7 +80,7 @@ static u32 r128_cce_microcode[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -int R128_READ_PLL(drm_device_t *dev, int addr) +int R128_READ_PLL(drm_device_t * dev, int addr) { drm_r128_private_t *dev_priv = dev->dev_private; @@ -89,106 +89,105 @@ int R128_READ_PLL(drm_device_t *dev, int addr) } #if R128_FIFO_DEBUG -static void r128_status( drm_r128_private_t *dev_priv ) +static void r128_status(drm_r128_private_t * dev_priv) { - printk( "GUI_STAT = 0x%08x\n", - (unsigned int)R128_READ( R128_GUI_STAT ) ); - printk( "PM4_STAT = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_STAT ) ); - printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) ); - printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) ); - printk( "PM4_MICRO_CNTL = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) ); - printk( "PM4_BUFFER_CNTL = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) ); + printk("GUI_STAT = 0x%08x\n", + (unsigned int)R128_READ(R128_GUI_STAT)); + printk("PM4_STAT = 0x%08x\n", + (unsigned int)R128_READ(R128_PM4_STAT)); + printk("PM4_BUFFER_DL_WPTR = 0x%08x\n", + (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR)); + printk("PM4_BUFFER_DL_RPTR = 0x%08x\n", + (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR)); + printk("PM4_MICRO_CNTL = 0x%08x\n", + (unsigned int)R128_READ(R128_PM4_MICRO_CNTL)); + printk("PM4_BUFFER_CNTL = 0x%08x\n", + (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL)); } #endif - /* ================================================================ * Engine, FIFO control */ -static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv ) +static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv) { u32 tmp; int i; - tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL; - R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp ); + tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL; + R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp); - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) { + for (i = 0; i < dev_priv->usec_timeout; i++) { + if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) { return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); + DRM_ERROR("failed!\n"); #endif return DRM_ERR(EBUSY); } -static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries ) +static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries) { int i; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK; - if ( slots >= entries ) return 0; - DRM_UDELAY( 1 ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK; + if (slots >= entries) + return 0; + DRM_UDELAY(1); } #if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); + DRM_ERROR("failed!\n"); #endif return DRM_ERR(EBUSY); } -static int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ) +static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) { int i, ret; - ret = r128_do_wait_for_fifo( dev_priv, 64 ); - if ( ret ) return ret; + ret = r128_do_wait_for_fifo(dev_priv, 64); + if (ret) + return ret; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) { - r128_do_pixcache_flush( dev_priv ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) { + r128_do_pixcache_flush(dev_priv); return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); + DRM_ERROR("failed!\n"); #endif return DRM_ERR(EBUSY); } - /* ================================================================ * CCE control, initialization */ /* Load the microcode for the CCE */ -static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) +static void r128_cce_load_microcode(drm_r128_private_t * dev_priv) { int i; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - r128_do_wait_for_idle( dev_priv ); + r128_do_wait_for_idle(dev_priv); - R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 ); - for ( i = 0 ; i < 256 ; i++ ) { - R128_WRITE( R128_PM4_MICROCODE_DATAH, - r128_cce_microcode[i * 2] ); - R128_WRITE( R128_PM4_MICROCODE_DATAL, - r128_cce_microcode[i * 2 + 1] ); + R128_WRITE(R128_PM4_MICROCODE_ADDR, 0); + for (i = 0; i < 256; i++) { + R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]); + R128_WRITE(R128_PM4_MICROCODE_DATAL, + r128_cce_microcode[i * 2 + 1]); } } @@ -196,51 +195,51 @@ static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) * prior to a wait for idle, as it informs the engine that the command * stream is ending. */ -static void r128_do_cce_flush( drm_r128_private_t *dev_priv ) +static void r128_do_cce_flush(drm_r128_private_t * dev_priv) { u32 tmp; - tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE; - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp ); + tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE; + R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp); } /* Wait for the CCE to go idle. */ -int r128_do_cce_idle( drm_r128_private_t *dev_priv ) +int r128_do_cce_idle(drm_r128_private_t * dev_priv) { int i; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( GET_RING_HEAD( dev_priv ) == dev_priv->ring.tail ) { - int pm4stat = R128_READ( R128_PM4_STAT ); - if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >= - dev_priv->cce_fifo_size ) && - !(pm4stat & (R128_PM4_BUSY | - R128_PM4_GUI_ACTIVE)) ) { - return r128_do_pixcache_flush( dev_priv ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) { + int pm4stat = R128_READ(R128_PM4_STAT); + if (((pm4stat & R128_PM4_FIFOCNT_MASK) >= + dev_priv->cce_fifo_size) && + !(pm4stat & (R128_PM4_BUSY | + R128_PM4_GUI_ACTIVE))) { + return r128_do_pixcache_flush(dev_priv); } } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - r128_status( dev_priv ); + DRM_ERROR("failed!\n"); + r128_status(dev_priv); #endif return DRM_ERR(EBUSY); } /* Start the Concurrent Command Engine. */ -static void r128_do_cce_start( drm_r128_private_t *dev_priv ) +static void r128_do_cce_start(drm_r128_private_t * dev_priv) { - r128_do_wait_for_idle( dev_priv ); + r128_do_wait_for_idle(dev_priv); - R128_WRITE( R128_PM4_BUFFER_CNTL, - dev_priv->cce_mode | dev_priv->ring.size_l2qw - | R128_PM4_BUFFER_CNTL_NOUPDATE ); - R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */ - R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN ); + R128_WRITE(R128_PM4_BUFFER_CNTL, + dev_priv->cce_mode | dev_priv->ring.size_l2qw + | R128_PM4_BUFFER_CNTL_NOUPDATE); + R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */ + R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN); dev_priv->cce_running = 1; } @@ -249,10 +248,10 @@ static void r128_do_cce_start( drm_r128_private_t *dev_priv ) * commands, so you must wait for the CCE command stream to complete * before calling this routine. */ -static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) +static void r128_do_cce_reset(drm_r128_private_t * dev_priv) { - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); - R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); + R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); + R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); dev_priv->ring.tail = 0; } @@ -260,121 +259,119 @@ static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) * commands, so you must flush the command stream and wait for the CCE * to go idle before calling this routine. */ -static void r128_do_cce_stop( drm_r128_private_t *dev_priv ) +static void r128_do_cce_stop(drm_r128_private_t * dev_priv) { - R128_WRITE( R128_PM4_MICRO_CNTL, 0 ); - R128_WRITE( R128_PM4_BUFFER_CNTL, - R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE ); + R128_WRITE(R128_PM4_MICRO_CNTL, 0); + R128_WRITE(R128_PM4_BUFFER_CNTL, + R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE); dev_priv->cce_running = 0; } /* Reset the engine. This will stop the CCE if it is running. */ -static int r128_do_engine_reset( drm_device_t *dev ) +static int r128_do_engine_reset(drm_device_t * dev) { drm_r128_private_t *dev_priv = dev->dev_private; u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; - r128_do_pixcache_flush( dev_priv ); + r128_do_pixcache_flush(dev_priv); - clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX ); - mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL ); + clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX); + mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL); - R128_WRITE_PLL( R128_MCLK_CNTL, - mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP ); + R128_WRITE_PLL(R128_MCLK_CNTL, + mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP); - gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL ); + gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL); /* Taken from the sample code - do not change */ - R128_WRITE( R128_GEN_RESET_CNTL, - gen_reset_cntl | R128_SOFT_RESET_GUI ); - R128_READ( R128_GEN_RESET_CNTL ); - R128_WRITE( R128_GEN_RESET_CNTL, - gen_reset_cntl & ~R128_SOFT_RESET_GUI ); - R128_READ( R128_GEN_RESET_CNTL ); + R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI); + R128_READ(R128_GEN_RESET_CNTL); + R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI); + R128_READ(R128_GEN_RESET_CNTL); - R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl ); - R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index ); - R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl ); + R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl); + R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index); + R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl); /* Reset the CCE ring */ - r128_do_cce_reset( dev_priv ); + r128_do_cce_reset(dev_priv); /* The CCE is no longer running after an engine reset */ dev_priv->cce_running = 0; /* Reset any pending vertex, indirect buffers */ - r128_freelist_reset( dev ); + r128_freelist_reset(dev); return 0; } -static void r128_cce_init_ring_buffer( drm_device_t *dev, - drm_r128_private_t *dev_priv ) +static void r128_cce_init_ring_buffer(drm_device_t * dev, + drm_r128_private_t * dev_priv) { u32 ring_start; u32 tmp; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* The manual (p. 2) says this address is in "VM space". This * means it's an offset from the start of AGP space. */ #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) + if (!dev_priv->is_pci) ring_start = dev_priv->cce_ring->offset - dev->agp->base; else #endif ring_start = dev_priv->cce_ring->offset - dev->sg->handle; - R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET ); + R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET); - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); - R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); + R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); + R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); /* Set watermark control */ - R128_WRITE( R128_PM4_BUFFER_WM_CNTL, - ((R128_WATERMARK_L/4) << R128_WMA_SHIFT) - | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT) - | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT) - | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) ); + R128_WRITE(R128_PM4_BUFFER_WM_CNTL, + ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT) + | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT) + | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT) + | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT)); /* Force read. Why? Because it's in the examples... */ - R128_READ( R128_PM4_BUFFER_ADDR ); + R128_READ(R128_PM4_BUFFER_ADDR); /* Turn on bus mastering */ - tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS; - R128_WRITE( R128_BUS_CNTL, tmp ); + tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS; + R128_WRITE(R128_BUS_CNTL, tmp); } -static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) +static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init) { drm_r128_private_t *dev_priv; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - dev_priv = drm_alloc( sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); - if ( dev_priv == NULL ) + dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER); + if (dev_priv == NULL) return DRM_ERR(ENOMEM); - memset( dev_priv, 0, sizeof(drm_r128_private_t) ); + memset(dev_priv, 0, sizeof(drm_r128_private_t)); dev_priv->is_pci = init->is_pci; - if ( dev_priv->is_pci && !dev->sg ) { - DRM_ERROR( "PCI GART memory not allocated!\n" ); + if (dev_priv->is_pci && !dev->sg) { + DRM_ERROR("PCI GART memory not allocated!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } dev_priv->usec_timeout = init->usec_timeout; - if ( dev_priv->usec_timeout < 1 || - dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) { - DRM_DEBUG( "TIMEOUT problem!\n" ); + if (dev_priv->usec_timeout < 1 || + dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) { + DRM_DEBUG("TIMEOUT problem!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } @@ -382,23 +379,23 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) /* GH: Simple idle check. */ - atomic_set( &dev_priv->idle_count, 0 ); + atomic_set(&dev_priv->idle_count, 0); /* We don't support anything other than bus-mastering ring mode, * but the ring can be in either AGP or PCI space for the ring * read pointer. */ - if ( ( init->cce_mode != R128_PM4_192BM ) && - ( init->cce_mode != R128_PM4_128BM_64INDBM ) && - ( init->cce_mode != R128_PM4_64BM_128INDBM ) && - ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) { - DRM_DEBUG( "Bad cce_mode!\n" ); + if ((init->cce_mode != R128_PM4_192BM) && + (init->cce_mode != R128_PM4_128BM_64INDBM) && + (init->cce_mode != R128_PM4_64BM_128INDBM) && + (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) { + DRM_DEBUG("Bad cce_mode!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } - switch ( init->cce_mode ) { + switch (init->cce_mode) { case R128_PM4_NONPM4: dev_priv->cce_fifo_size = 0; break; @@ -419,7 +416,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) break; } - switch ( init->fb_bpp ) { + switch (init->fb_bpp) { case 16: dev_priv->color_fmt = R128_DATATYPE_RGB565; break; @@ -428,12 +425,12 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) dev_priv->color_fmt = R128_DATATYPE_ARGB8888; break; } - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; - switch ( init->depth_bpp ) { + switch (init->depth_bpp) { case 16: dev_priv->depth_fmt = R128_DATATYPE_RGB565; break; @@ -443,219 +440,220 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; break; } - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - dev_priv->span_offset = init->span_offset; + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; + dev_priv->span_offset = init->span_offset; - dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) | + dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) | (dev_priv->front_offset >> 5)); - dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) | + dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) | (dev_priv->back_offset >> 5)); - dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | + dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | (dev_priv->depth_offset >> 5) | R128_DST_TILE); - dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | + dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | (dev_priv->span_offset >> 5)); DRM_GETSAREA(); - - if(!dev_priv->sarea) { + + if (!dev_priv->sarea) { DRM_ERROR("could not find sarea!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if(!dev_priv->mmio) { + if (!dev_priv->mmio) { DRM_ERROR("could not find mmio region!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset); - if(!dev_priv->cce_ring) { + if (!dev_priv->cce_ring) { DRM_ERROR("could not find cce ring region!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); - if(!dev_priv->ring_rptr) { + if (!dev_priv->ring_rptr) { DRM_ERROR("could not find ring read pointer!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if(!dev->agp_buffer_map) { + if (!dev->agp_buffer_map) { DRM_ERROR("could not find dma buffer region!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } - if ( !dev_priv->is_pci ) { - dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset); - if(!dev_priv->agp_textures) { + if (!dev_priv->is_pci) { + dev_priv->agp_textures = + drm_core_findmap(dev, init->agp_textures_offset); + if (!dev_priv->agp_textures) { DRM_ERROR("could not find agp texture region!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } } dev_priv->sarea_priv = - (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); + (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle + + init->sarea_priv_offset); #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { - drm_core_ioremap( dev_priv->cce_ring, dev ); - drm_core_ioremap( dev_priv->ring_rptr, dev ); - drm_core_ioremap( dev->agp_buffer_map, dev ); - if(!dev_priv->cce_ring->handle || - !dev_priv->ring_rptr->handle || - !dev->agp_buffer_map->handle) { + if (!dev_priv->is_pci) { + drm_core_ioremap(dev_priv->cce_ring, dev); + drm_core_ioremap(dev_priv->ring_rptr, dev); + drm_core_ioremap(dev->agp_buffer_map, dev); + if (!dev_priv->cce_ring->handle || + !dev_priv->ring_rptr->handle || + !dev->agp_buffer_map->handle) { DRM_ERROR("Could not ioremap agp regions!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(ENOMEM); } } else #endif { - dev_priv->cce_ring->handle = - (void *)dev_priv->cce_ring->offset; + dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset; dev_priv->ring_rptr->handle = - (void *)dev_priv->ring_rptr->offset; - dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; + (void *)dev_priv->ring_rptr->offset; + dev->agp_buffer_map->handle = + (void *)dev->agp_buffer_map->offset; } #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) + if (!dev_priv->is_pci) dev_priv->cce_buffers_offset = dev->agp->base; else #endif dev_priv->cce_buffers_offset = dev->sg->handle; - dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle; - dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle + dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle; + dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle + init->ring_size / sizeof(u32)); dev_priv->ring.size = init->ring_size; - dev_priv->ring.size_l2qw = get_order( init->ring_size / 8 ); + dev_priv->ring.size_l2qw = get_order(init->ring_size / 8); - dev_priv->ring.tail_mask = - (dev_priv->ring.size / sizeof(u32)) - 1; + dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = 128; dev_priv->sarea_priv->last_frame = 0; - R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); + R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); dev_priv->sarea_priv->last_dispatch = 0; - R128_WRITE( R128_LAST_DISPATCH_REG, - dev_priv->sarea_priv->last_dispatch ); + R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch); #if __OS_HAS_AGP - if ( dev_priv->is_pci ) { + if (dev_priv->is_pci) { #endif - if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart, - &dev_priv->bus_pci_gart) ) { - DRM_ERROR( "failed to init PCI GART!\n" ); + if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart, + &dev_priv->bus_pci_gart)) { + DRM_ERROR("failed to init PCI GART!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(ENOMEM); } - R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart ); + R128_WRITE(R128_PCI_GART_PAGE, dev_priv->bus_pci_gart); #if __OS_HAS_AGP } #endif - r128_cce_init_ring_buffer( dev, dev_priv ); - r128_cce_load_microcode( dev_priv ); + r128_cce_init_ring_buffer(dev, dev_priv); + r128_cce_load_microcode(dev_priv); dev->dev_private = (void *)dev_priv; - r128_do_engine_reset( dev ); + r128_do_engine_reset(dev); return 0; } -int r128_do_cleanup_cce( drm_device_t *dev ) +int r128_do_cleanup_cce(drm_device_t * dev) { /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private * is freed, it's too late. */ - if ( dev->irq_enabled ) drm_irq_uninstall(dev); + if (dev->irq_enabled) + drm_irq_uninstall(dev); - if ( dev->dev_private ) { + if (dev->dev_private) { drm_r128_private_t *dev_priv = dev->dev_private; #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { - if ( dev_priv->cce_ring != NULL ) - drm_core_ioremapfree( dev_priv->cce_ring, dev ); - if ( dev_priv->ring_rptr != NULL ) - drm_core_ioremapfree( dev_priv->ring_rptr, dev ); - if ( dev->agp_buffer_map != NULL ) { - drm_core_ioremapfree( dev->agp_buffer_map, dev ); + if (!dev_priv->is_pci) { + if (dev_priv->cce_ring != NULL) + drm_core_ioremapfree(dev_priv->cce_ring, dev); + if (dev_priv->ring_rptr != NULL) + drm_core_ioremapfree(dev_priv->ring_rptr, dev); + if (dev->agp_buffer_map != NULL) { + drm_core_ioremapfree(dev->agp_buffer_map, dev); dev->agp_buffer_map = NULL; } } else #endif { - if (!drm_ati_pcigart_cleanup( dev, - dev_priv->phys_pci_gart, - dev_priv->bus_pci_gart )) - DRM_ERROR( "failed to cleanup PCI GART!\n" ); + if (!drm_ati_pcigart_cleanup(dev, + dev_priv->phys_pci_gart, + dev_priv->bus_pci_gart)) + DRM_ERROR("failed to cleanup PCI GART!\n"); } - drm_free( dev->dev_private, sizeof(drm_r128_private_t), - DRM_MEM_DRIVER ); + drm_free(dev->dev_private, sizeof(drm_r128_private_t), + DRM_MEM_DRIVER); dev->dev_private = NULL; } return 0; } -int r128_cce_init( DRM_IOCTL_ARGS ) +int r128_cce_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_init_t init; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( init, (drm_r128_init_t __user *)data, sizeof(init) ); + DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data, + sizeof(init)); - switch ( init.func ) { + switch (init.func) { case R128_INIT_CCE: - return r128_do_init_cce( dev, &init ); + return r128_do_init_cce(dev, &init); case R128_CLEANUP_CCE: - return r128_do_cleanup_cce( dev ); + return r128_do_cleanup_cce(dev); } return DRM_ERR(EINVAL); } -int r128_cce_start( DRM_IOCTL_ARGS ) +int r128_cce_start(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) { - DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ ); + if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { + DRM_DEBUG("%s while CCE running\n", __FUNCTION__); return 0; } - r128_do_cce_start( dev_priv ); + r128_do_cce_start(dev_priv); return 0; } @@ -663,61 +661,63 @@ int r128_cce_start( DRM_IOCTL_ARGS ) /* Stop the CCE. The engine must have been idled before calling this * routine. */ -int r128_cce_stop( DRM_IOCTL_ARGS ) +int r128_cce_stop(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_cce_stop_t stop; int ret; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *)data, sizeof(stop) ); + DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data, + sizeof(stop)); /* Flush any pending CCE commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. */ - if ( stop.flush ) { - r128_do_cce_flush( dev_priv ); + if (stop.flush) { + r128_do_cce_flush(dev_priv); } /* If we fail to make the engine go idle, we return an error * code so that the DRM ioctl wrapper can try again. */ - if ( stop.idle ) { - ret = r128_do_cce_idle( dev_priv ); - if ( ret ) return ret; + if (stop.idle) { + ret = r128_do_cce_idle(dev_priv); + if (ret) + return ret; } /* Finally, we can turn off the CCE. If the engine isn't idle, * we will get some dropped triangles as they won't be fully * rendered before the CCE is shut down. */ - r128_do_cce_stop( dev_priv ); + r128_do_cce_stop(dev_priv); /* Reset the engine */ - r128_do_engine_reset( dev ); + r128_do_engine_reset(dev); return 0; } /* Just reset the CCE ring. Called as part of an X Server engine reset. */ -int r128_cce_reset( DRM_IOCTL_ARGS ) +int r128_cce_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_DEBUG("%s called before init done\n", __FUNCTION__); return DRM_ERR(EINVAL); } - r128_do_cce_reset( dev_priv ); + r128_do_cce_reset(dev_priv); /* The CCE is no longer running after an engine reset */ dev_priv->cce_running = 0; @@ -725,37 +725,36 @@ int r128_cce_reset( DRM_IOCTL_ARGS ) return 0; } -int r128_cce_idle( DRM_IOCTL_ARGS ) +int r128_cce_idle(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( dev_priv->cce_running ) { - r128_do_cce_flush( dev_priv ); + if (dev_priv->cce_running) { + r128_do_cce_flush(dev_priv); } - return r128_do_cce_idle( dev_priv ); + return r128_do_cce_idle(dev_priv); } -int r128_engine_reset( DRM_IOCTL_ARGS ) +int r128_engine_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - return r128_do_engine_reset( dev ); + return r128_do_engine_reset(dev); } -int r128_fullscreen( DRM_IOCTL_ARGS ) +int r128_fullscreen(DRM_IOCTL_ARGS) { return DRM_ERR(EINVAL); } - /* ================================================================ * Freelist management */ @@ -763,7 +762,7 @@ int r128_fullscreen( DRM_IOCTL_ARGS ) #define R128_BUFFER_FREE 0 #if 0 -static int r128_freelist_init( drm_device_t *dev ) +static int r128_freelist_init(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; @@ -772,27 +771,26 @@ static int r128_freelist_init( drm_device_t *dev ) drm_r128_freelist_t *entry; int i; - dev_priv->head = drm_alloc( sizeof(drm_r128_freelist_t), - DRM_MEM_DRIVER ); - if ( dev_priv->head == NULL ) + dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); + if (dev_priv->head == NULL) return DRM_ERR(ENOMEM); - memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) ); + memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t)); dev_priv->head->age = R128_BUFFER_USED; - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - entry = drm_alloc( sizeof(drm_r128_freelist_t), - DRM_MEM_DRIVER ); - if ( !entry ) return DRM_ERR(ENOMEM); + entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); + if (!entry) + return DRM_ERR(ENOMEM); entry->age = R128_BUFFER_FREE; entry->buf = buf; entry->prev = dev_priv->head; entry->next = dev_priv->head->next; - if ( !entry->next ) + if (!entry->next) dev_priv->tail = entry; buf_priv->discard = 0; @@ -801,7 +799,7 @@ static int r128_freelist_init( drm_device_t *dev ) dev_priv->head->next = entry; - if ( dev_priv->head->next ) + if (dev_priv->head->next) dev_priv->head->next->prev = entry; } @@ -810,7 +808,7 @@ static int r128_freelist_init( drm_device_t *dev ) } #endif -drm_buf_t *r128_freelist_get( drm_device_t *dev ) +drm_buf_t *r128_freelist_get(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; @@ -820,20 +818,20 @@ drm_buf_t *r128_freelist_get( drm_device_t *dev ) /* FIXME: Optimize -- use freelist code */ - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if ( buf->filp == 0 ) + if (buf->filp == 0) return buf; } - for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { - u32 done_age = R128_READ( R128_LAST_DISPATCH_REG ); + for (t = 0; t < dev_priv->usec_timeout; t++) { + u32 done_age = R128_READ(R128_LAST_DISPATCH_REG); - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if ( buf->pending && buf_priv->age <= done_age ) { + if (buf->pending && buf_priv->age <= done_age) { /* The buffer has been processed, so it * can now be used. */ @@ -841,63 +839,63 @@ drm_buf_t *r128_freelist_get( drm_device_t *dev ) return buf; } } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } - DRM_DEBUG( "returning NULL!\n" ); + DRM_DEBUG("returning NULL!\n"); return NULL; } -void r128_freelist_reset( drm_device_t *dev ) +void r128_freelist_reset(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; int i; - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[i]; drm_r128_buf_priv_t *buf_priv = buf->dev_private; buf_priv->age = 0; } } - /* ================================================================ * CCE command submission */ -int r128_wait_ring( drm_r128_private_t *dev_priv, int n ) +int r128_wait_ring(drm_r128_private_t * dev_priv, int n) { drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - r128_update_ring_snapshot( dev_priv ); - if ( ring->space >= n ) + for (i = 0; i < dev_priv->usec_timeout; i++) { + r128_update_ring_snapshot(dev_priv); + if (ring->space >= n) return 0; - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } /* FIXME: This is being ignored... */ - DRM_ERROR( "failed!\n" ); + DRM_ERROR("failed!\n"); return DRM_ERR(EBUSY); } -static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) +static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d) { int i; drm_buf_t *buf; - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = r128_freelist_get( dev ); - if ( !buf ) return DRM_ERR(EAGAIN); + for (i = d->granted_count; i < d->request_count; i++) { + buf = r128_freelist_get(dev); + if (!buf) + return DRM_ERR(EAGAIN); buf->filp = filp; - if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, - sizeof(buf->idx) ) ) + if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, + sizeof(buf->idx))) return DRM_ERR(EFAULT); - if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, - sizeof(buf->total) ) ) + if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, + sizeof(buf->total))) return DRM_ERR(EFAULT); d->granted_count++; @@ -905,7 +903,7 @@ static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) return 0; } -int r128_cce_buffers( DRM_IOCTL_ARGS ) +int r128_cce_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; @@ -913,33 +911,33 @@ int r128_cce_buffers( DRM_IOCTL_ARGS ) drm_dma_t __user *argp = (void __user *)data; drm_dma_t d; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); + DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); /* Please don't send us buffers. */ - if ( d.send_count != 0 ) { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count ); + if (d.send_count != 0) { + DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", + DRM_CURRENTPID, d.send_count); return DRM_ERR(EINVAL); } /* We'll send you buffers. */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count ); + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", + DRM_CURRENTPID, d.request_count, dma->buf_count); return DRM_ERR(EINVAL); } d.granted_count = 0; - if ( d.request_count ) { - ret = r128_cce_get_buffers( filp, dev, &d ); + if (d.request_count) { + ret = r128_cce_get_buffers(filp, dev, &d); } - DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d) ); + DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); return ret; } diff --git a/shared-core/r128_drm.h b/shared-core/r128_drm.h index 0cba17d1..607836ab 100644 --- a/shared-core/r128_drm.h +++ b/shared-core/r128_drm.h @@ -93,7 +93,7 @@ #define R128_MAX_TEXTURE_LEVELS 11 #define R128_MAX_TEXTURE_UNITS 2 -#endif /* __R128_SAREA_DEFINES__ */ +#endif /* __R128_SAREA_DEFINES__ */ typedef struct { /* Context state - can be written in one large chunk */ @@ -140,7 +140,6 @@ typedef struct { unsigned int tex_border_color; } drm_r128_texture_regs_t; - typedef struct drm_r128_sarea { /* The channel for communication of state information to the kernel * on firing a vertex buffer. @@ -161,14 +160,13 @@ typedef struct drm_r128_sarea { unsigned int last_frame; unsigned int last_dispatch; - drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1]; + drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; unsigned int tex_age[R128_NR_TEX_HEAPS]; int ctx_owner; - int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ - int pfCurrentPage; /* which buffer is being displayed? */ + int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ + int pfCurrentPage; /* which buffer is being displayed? */ } drm_r128_sarea_t; - /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmR128.h) */ @@ -220,7 +218,7 @@ typedef struct drm_r128_sarea { typedef struct drm_r128_init { enum { - R128_INIT_CCE = 0x01, + R128_INIT_CCE = 0x01, R128_CLEANUP_CCE = 0x02 } func; #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) @@ -278,9 +276,9 @@ typedef struct drm_r128_clear { typedef struct drm_r128_vertex { int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ + int idx; /* Index of vertex buffer */ + int count; /* Number of vertices in buffer */ + int discard; /* Client finished with buffer? */ } drm_r128_vertex_t; typedef struct drm_r128_indices { @@ -288,7 +286,7 @@ typedef struct drm_r128_indices { int idx; int start; int end; - int discard; /* Client finished with buffer? */ + int discard; /* Client finished with buffer? */ } drm_r128_indices_t; typedef struct drm_r128_blit { @@ -302,10 +300,10 @@ typedef struct drm_r128_blit { typedef struct drm_r128_depth { enum { - R128_WRITE_SPAN = 0x01, - R128_WRITE_PIXELS = 0x02, - R128_READ_SPAN = 0x03, - R128_READ_PIXELS = 0x04 + R128_WRITE_SPAN = 0x01, + R128_WRITE_PIXELS = 0x02, + R128_READ_SPAN = 0x03, + R128_READ_PIXELS = 0x04 } func; int n; int __user *x; @@ -327,13 +325,13 @@ typedef struct drm_r128_indirect { typedef struct drm_r128_fullscreen { enum { - R128_INIT_FULLSCREEN = 0x01, + R128_INIT_FULLSCREEN = 0x01, R128_CLEANUP_FULLSCREEN = 0x02 } func; } drm_r128_fullscreen_t; /* 2.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. + * client any other way. */ #define R128_PARAM_IRQ_NR 1 diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h index 9cec2f3e..ed259498 100644 --- a/shared-core/r128_drv.h +++ b/shared-core/r128_drv.h @@ -46,14 +46,13 @@ #define DRIVER_MINOR 5 #define DRIVER_PATCHLEVEL 0 - #define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR ) typedef struct drm_r128_freelist { - unsigned int age; - drm_buf_t *buf; - struct drm_r128_freelist *next; - struct drm_r128_freelist *prev; + unsigned int age; + drm_buf_t *buf; + struct drm_r128_freelist *next; + struct drm_r128_freelist *prev; } drm_r128_freelist_t; typedef struct drm_r128_ring_buffer { @@ -77,8 +76,8 @@ typedef struct drm_r128_private { int cce_fifo_size; int cce_running; - drm_r128_freelist_t *head; - drm_r128_freelist_t *tail; + drm_r128_freelist_t *head; + drm_r128_freelist_t *tail; int usec_timeout; int is_pci; @@ -121,48 +120,48 @@ typedef struct drm_r128_buf_priv { int prim; int discard; int dispatched; - drm_r128_freelist_t *list_entry; + drm_r128_freelist_t *list_entry; } drm_r128_buf_priv_t; /* r128_cce.c */ -extern int r128_cce_init( DRM_IOCTL_ARGS ); -extern int r128_cce_start( DRM_IOCTL_ARGS ); -extern int r128_cce_stop( DRM_IOCTL_ARGS ); -extern int r128_cce_reset( DRM_IOCTL_ARGS ); -extern int r128_cce_idle( DRM_IOCTL_ARGS ); -extern int r128_engine_reset( DRM_IOCTL_ARGS ); -extern int r128_fullscreen( DRM_IOCTL_ARGS ); -extern int r128_cce_buffers( DRM_IOCTL_ARGS ); -extern int r128_getparam( DRM_IOCTL_ARGS ); +extern int r128_cce_init(DRM_IOCTL_ARGS); +extern int r128_cce_start(DRM_IOCTL_ARGS); +extern int r128_cce_stop(DRM_IOCTL_ARGS); +extern int r128_cce_reset(DRM_IOCTL_ARGS); +extern int r128_cce_idle(DRM_IOCTL_ARGS); +extern int r128_engine_reset(DRM_IOCTL_ARGS); +extern int r128_fullscreen(DRM_IOCTL_ARGS); +extern int r128_cce_buffers(DRM_IOCTL_ARGS); +extern int r128_getparam(DRM_IOCTL_ARGS); -extern void r128_freelist_reset( drm_device_t *dev ); -extern drm_buf_t *r128_freelist_get( drm_device_t *dev ); +extern void r128_freelist_reset(drm_device_t * dev); +extern drm_buf_t *r128_freelist_get(drm_device_t * dev); -extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n ); +extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n); -extern int r128_do_cce_idle( drm_r128_private_t *dev_priv ); -extern int r128_do_cleanup_cce( drm_device_t *dev ); -extern int r128_do_cleanup_pageflip( drm_device_t *dev ); +extern int r128_do_cce_idle(drm_r128_private_t * dev_priv); +extern int r128_do_cleanup_cce(drm_device_t * dev); +extern int r128_do_cleanup_pageflip(drm_device_t * dev); /* r128_state.c */ -extern int r128_cce_clear( DRM_IOCTL_ARGS ); -extern int r128_cce_swap( DRM_IOCTL_ARGS ); -extern int r128_cce_flip( DRM_IOCTL_ARGS ); -extern int r128_cce_vertex( DRM_IOCTL_ARGS ); -extern int r128_cce_indices( DRM_IOCTL_ARGS ); -extern int r128_cce_blit( DRM_IOCTL_ARGS ); -extern int r128_cce_depth( DRM_IOCTL_ARGS ); -extern int r128_cce_stipple( DRM_IOCTL_ARGS ); -extern int r128_cce_indirect( DRM_IOCTL_ARGS ); - -extern int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); - -extern irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS ); -extern void r128_driver_irq_preinstall( drm_device_t *dev ); -extern void r128_driver_irq_postinstall( drm_device_t *dev ); -extern void r128_driver_irq_uninstall( drm_device_t *dev ); -extern void r128_driver_pretakedown(drm_device_t *dev); -extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp); +extern int r128_cce_clear(DRM_IOCTL_ARGS); +extern int r128_cce_swap(DRM_IOCTL_ARGS); +extern int r128_cce_flip(DRM_IOCTL_ARGS); +extern int r128_cce_vertex(DRM_IOCTL_ARGS); +extern int r128_cce_indices(DRM_IOCTL_ARGS); +extern int r128_cce_blit(DRM_IOCTL_ARGS); +extern int r128_cce_depth(DRM_IOCTL_ARGS); +extern int r128_cce_stipple(DRM_IOCTL_ARGS); +extern int r128_cce_indirect(DRM_IOCTL_ARGS); + +extern int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence); + +extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS); +extern void r128_driver_irq_preinstall(drm_device_t * dev); +extern void r128_driver_irq_postinstall(drm_device_t * dev); +extern void r128_driver_irq_uninstall(drm_device_t * dev); +extern void r128_driver_pretakedown(drm_device_t * dev); +extern void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp); /* Register definitions, register access macros and drmAddMap constants * for Rage 128 kernel driver. @@ -271,7 +270,6 @@ extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp); # define R128_EVENT_CRTC_OFFSET (1 << 0) #define R128_WINDOW_XY_OFFSET 0x1bcc - /* CCE registers */ #define R128_PM4_BUFFER_OFFSET 0x0700 @@ -322,7 +320,6 @@ extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp); #define R128_PM4_FIFO_DATA_EVEN 0x1000 #define R128_PM4_FIFO_DATA_ODD 0x1004 - /* CCE command packets */ #define R128_CCE_PACKET0 0x00000000 @@ -400,8 +397,7 @@ do { \ R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ } while (0) -extern int R128_READ_PLL(drm_device_t *dev, int addr); - +extern int R128_READ_PLL(drm_device_t * dev, int addr); #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ ((n) << 16) | ((reg) >> 2)) @@ -411,13 +407,11 @@ extern int R128_READ_PLL(drm_device_t *dev, int addr); #define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ (pkt) | ((n) << 16)) - -static __inline__ void -r128_update_ring_snapshot( drm_r128_private_t *dev_priv ) +static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv) { drm_r128_ring_buffer_t *ring = &dev_priv->ring; - ring->space = (GET_RING_HEAD( dev_priv ) - ring->tail) * sizeof(u32); - if ( ring->space <= 0 ) + ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32); + if (ring->space <= 0) ring->space += ring->size; } @@ -458,7 +452,6 @@ do { \ OUT_RING( R128_EVENT_CRTC_OFFSET ); \ } while (0) - /* ================================================================ * Ring control */ @@ -528,4 +521,4 @@ do { \ write &= tail_mask; \ } while (0) -#endif /* __R128_DRV_H__ */ +#endif /* __R128_DRV_H__ */ diff --git a/shared-core/r128_irq.c b/shared-core/r128_irq.c index 643a3078..27eb0e31 100644 --- a/shared-core/r128_irq.c +++ b/shared-core/r128_irq.c @@ -1,7 +1,7 @@ /* r128_irq.c -- IRQ handling for radeon -*- linux-c -*- * * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * + * * The Weather Channel (TM) funded Tungsten Graphics to develop the * initial release of the Radeon 8500 driver under the XFree86 license. * This notice must be preserved. @@ -35,68 +35,67 @@ #include "r128_drm.h" #include "r128_drv.h" -irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS ) +irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS) { drm_device_t *dev = (drm_device_t *) arg; - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; + drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; int status; - status = R128_READ( R128_GEN_INT_STATUS ); - + status = R128_READ(R128_GEN_INT_STATUS); + /* VBLANK interrupt */ - if ( status & R128_CRTC_VBLANK_INT ) { - R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK ); + if (status & R128_CRTC_VBLANK_INT) { + R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); atomic_inc(&dev->vbl_received); DRM_WAKEUP(&dev->vbl_queue); - drm_vbl_send_signals( dev ); + drm_vbl_send_signals(dev); return IRQ_HANDLED; } return IRQ_NONE; } -int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) { unsigned int cur_vblank; int ret = 0; /* Assume that the user has missed the current sequence number * by about a day rather than she wants to wait for years - * using vertical blanks... + * using vertical blanks... */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, - ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - - *sequence ) <= (1<<23) ) ); + DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, + (((cur_vblank = atomic_read(&dev->vbl_received)) + - *sequence) <= (1 << 23))); *sequence = cur_vblank; return ret; } -void r128_driver_irq_preinstall( drm_device_t *dev ) { - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; +void r128_driver_irq_preinstall(drm_device_t * dev) +{ + drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; /* Disable *all* interrupts */ - R128_WRITE( R128_GEN_INT_CNTL, 0 ); + R128_WRITE(R128_GEN_INT_CNTL, 0); /* Clear vblank bit if it's already high */ - R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK ); + R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); } -void r128_driver_irq_postinstall( drm_device_t *dev ) { - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; +void r128_driver_irq_postinstall(drm_device_t * dev) +{ + drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; /* Turn on VBL interrupt */ - R128_WRITE( R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN ); + R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN); } -void r128_driver_irq_uninstall( drm_device_t *dev ) { - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; +void r128_driver_irq_uninstall(drm_device_t * dev) +{ + drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; if (!dev_priv) return; /* Disable *all* interrupts */ - R128_WRITE( R128_GEN_INT_CNTL, 0 ); + R128_WRITE(R128_GEN_INT_CNTL, 0); } diff --git a/shared-core/r128_state.c b/shared-core/r128_state.c index ed643682..155fe936 100644 --- a/shared-core/r128_state.c +++ b/shared-core/r128_state.c @@ -32,235 +32,233 @@ #include "r128_drm.h" #include "r128_drv.h" - /* ================================================================ * CCE hardware state programming functions */ -static void r128_emit_clip_rects( drm_r128_private_t *dev_priv, - drm_clip_rect_t *boxes, int count ) +static void r128_emit_clip_rects(drm_r128_private_t * dev_priv, + drm_clip_rect_t * boxes, int count) { u32 aux_sc_cntl = 0x00000000; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( (count < 3? count: 3) * 5 + 2 ); + BEGIN_RING((count < 3 ? count : 3) * 5 + 2); - if ( count >= 1 ) { - OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) ); - OUT_RING( boxes[0].x1 ); - OUT_RING( boxes[0].x2 - 1 ); - OUT_RING( boxes[0].y1 ); - OUT_RING( boxes[0].y2 - 1 ); + if (count >= 1) { + OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); + OUT_RING(boxes[0].x1); + OUT_RING(boxes[0].x2 - 1); + OUT_RING(boxes[0].y1); + OUT_RING(boxes[0].y2 - 1); aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR); } - if ( count >= 2 ) { - OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) ); - OUT_RING( boxes[1].x1 ); - OUT_RING( boxes[1].x2 - 1 ); - OUT_RING( boxes[1].y1 ); - OUT_RING( boxes[1].y2 - 1 ); + if (count >= 2) { + OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); + OUT_RING(boxes[1].x1); + OUT_RING(boxes[1].x2 - 1); + OUT_RING(boxes[1].y1); + OUT_RING(boxes[1].y2 - 1); aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR); } - if ( count >= 3 ) { - OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) ); - OUT_RING( boxes[2].x1 ); - OUT_RING( boxes[2].x2 - 1 ); - OUT_RING( boxes[2].y1 ); - OUT_RING( boxes[2].y2 - 1 ); + if (count >= 3) { + OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3)); + OUT_RING(boxes[2].x1); + OUT_RING(boxes[2].x2 - 1); + OUT_RING(boxes[2].y1); + OUT_RING(boxes[2].y2 - 1); aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR); } - OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) ); - OUT_RING( aux_sc_cntl ); + OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0)); + OUT_RING(aux_sc_cntl); ADVANCE_RING(); } -static __inline__ void r128_emit_core( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) ); - OUT_RING( ctx->scale_3d_cntl ); + OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0)); + OUT_RING(ctx->scale_3d_cntl); ADVANCE_RING(); } -static __inline__ void r128_emit_context( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 13 ); - - OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) ); - OUT_RING( ctx->dst_pitch_offset_c ); - OUT_RING( ctx->dp_gui_master_cntl_c ); - OUT_RING( ctx->sc_top_left_c ); - OUT_RING( ctx->sc_bottom_right_c ); - OUT_RING( ctx->z_offset_c ); - OUT_RING( ctx->z_pitch_c ); - OUT_RING( ctx->z_sten_cntl_c ); - OUT_RING( ctx->tex_cntl_c ); - OUT_RING( ctx->misc_3d_state_cntl_reg ); - OUT_RING( ctx->texture_clr_cmp_clr_c ); - OUT_RING( ctx->texture_clr_cmp_msk_c ); - OUT_RING( ctx->fog_color_c ); + DRM_DEBUG(" %s\n", __FUNCTION__); + + BEGIN_RING(13); + + OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11)); + OUT_RING(ctx->dst_pitch_offset_c); + OUT_RING(ctx->dp_gui_master_cntl_c); + OUT_RING(ctx->sc_top_left_c); + OUT_RING(ctx->sc_bottom_right_c); + OUT_RING(ctx->z_offset_c); + OUT_RING(ctx->z_pitch_c); + OUT_RING(ctx->z_sten_cntl_c); + OUT_RING(ctx->tex_cntl_c); + OUT_RING(ctx->misc_3d_state_cntl_reg); + OUT_RING(ctx->texture_clr_cmp_clr_c); + OUT_RING(ctx->texture_clr_cmp_msk_c); + OUT_RING(ctx->fog_color_c); ADVANCE_RING(); } -static __inline__ void r128_emit_setup( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 3 ); + BEGIN_RING(3); - OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) ); - OUT_RING( ctx->setup_cntl ); - OUT_RING( ctx->pm4_vc_fpu_setup ); + OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP)); + OUT_RING(ctx->setup_cntl); + OUT_RING(ctx->pm4_vc_fpu_setup); ADVANCE_RING(); } -static __inline__ void r128_emit_masks( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 5 ); + BEGIN_RING(5); - OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); - OUT_RING( ctx->dp_write_mask ); + OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); + OUT_RING(ctx->dp_write_mask); - OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) ); - OUT_RING( ctx->sten_ref_mask_c ); - OUT_RING( ctx->plane_3d_mask_c ); + OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1)); + OUT_RING(ctx->sten_ref_mask_c); + OUT_RING(ctx->plane_3d_mask_c); ADVANCE_RING(); } -static __inline__ void r128_emit_window( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) ); - OUT_RING( ctx->window_xy_offset ); + OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0)); + OUT_RING(ctx->window_xy_offset); ADVANCE_RING(); } -static __inline__ void r128_emit_tex0( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0]; int i; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS ); + BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS); - OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C, - 2 + R128_MAX_TEXTURE_LEVELS ) ); - OUT_RING( tex->tex_cntl ); - OUT_RING( tex->tex_combine_cntl ); - OUT_RING( ctx->tex_size_pitch_c ); - for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { - OUT_RING( tex->tex_offset[i] ); + OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C, + 2 + R128_MAX_TEXTURE_LEVELS)); + OUT_RING(tex->tex_cntl); + OUT_RING(tex->tex_combine_cntl); + OUT_RING(ctx->tex_size_pitch_c); + for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) { + OUT_RING(tex->tex_offset[i]); } - OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) ); - OUT_RING( ctx->constant_color_c ); - OUT_RING( tex->tex_border_color ); + OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1)); + OUT_RING(ctx->constant_color_c); + OUT_RING(tex->tex_border_color); ADVANCE_RING(); } -static __inline__ void r128_emit_tex1( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; int i; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS ); + BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS); - OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C, - 1 + R128_MAX_TEXTURE_LEVELS ) ); - OUT_RING( tex->tex_cntl ); - OUT_RING( tex->tex_combine_cntl ); - for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { - OUT_RING( tex->tex_offset[i] ); + OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS)); + OUT_RING(tex->tex_cntl); + OUT_RING(tex->tex_combine_cntl); + for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) { + OUT_RING(tex->tex_offset[i]); } - OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) ); - OUT_RING( tex->tex_border_color ); + OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0)); + OUT_RING(tex->tex_border_color); ADVANCE_RING(); } -static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_state(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; - DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); + DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty); - if ( dirty & R128_UPLOAD_CORE ) { - r128_emit_core( dev_priv ); + if (dirty & R128_UPLOAD_CORE) { + r128_emit_core(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_CORE; } - if ( dirty & R128_UPLOAD_CONTEXT ) { - r128_emit_context( dev_priv ); + if (dirty & R128_UPLOAD_CONTEXT) { + r128_emit_context(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; } - if ( dirty & R128_UPLOAD_SETUP ) { - r128_emit_setup( dev_priv ); + if (dirty & R128_UPLOAD_SETUP) { + r128_emit_setup(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_SETUP; } - if ( dirty & R128_UPLOAD_MASKS ) { - r128_emit_masks( dev_priv ); + if (dirty & R128_UPLOAD_MASKS) { + r128_emit_masks(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_MASKS; } - if ( dirty & R128_UPLOAD_WINDOW ) { - r128_emit_window( dev_priv ); + if (dirty & R128_UPLOAD_WINDOW) { + r128_emit_window(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; } - if ( dirty & R128_UPLOAD_TEX0 ) { - r128_emit_tex0( dev_priv ); + if (dirty & R128_UPLOAD_TEX0) { + r128_emit_tex0(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_TEX0; } - if ( dirty & R128_UPLOAD_TEX1 ) { - r128_emit_tex1( dev_priv ); + if (dirty & R128_UPLOAD_TEX1) { + r128_emit_tex1(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_TEX1; } @@ -270,26 +268,23 @@ static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv ) sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; } - #if R128_PERFORMANCE_BOXES /* ================================================================ * Performance monitoring functions */ -static void r128_clear_box( drm_r128_private_t *dev_priv, - int x, int y, int w, int h, - int r, int g, int b ) +static void r128_clear_box(drm_r128_private_t * dev_priv, + int x, int y, int w, int h, int r, int g, int b) { u32 pitch, offset; u32 fb_bpp, color; RING_LOCALS; - switch ( dev_priv->fb_bpp ) { + switch (dev_priv->fb_bpp) { case 16: fb_bpp = R128_GMC_DST_16BPP; color = (((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | - ((b & 0xf8) >> 3)); + ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); break; case 24: fb_bpp = R128_GMC_DST_24BPP; @@ -297,7 +292,7 @@ static void r128_clear_box( drm_r128_private_t *dev_priv, break; case 32: fb_bpp = R128_GMC_DST_32BPP; - color = (((0xff) << 24) | (r << 16) | (g << 8) | b); + color = (((0xff) << 24) | (r << 16) | (g << 8) | b); break; default: return; @@ -306,60 +301,58 @@ static void r128_clear_box( drm_r128_private_t *dev_priv, offset = dev_priv->back_offset; pitch = dev_priv->back_pitch >> 3; - BEGIN_RING( 6 ); + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - fb_bpp | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + fb_bpp | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS); - OUT_RING( (pitch << 21) | (offset >> 5) ); - OUT_RING( color ); + OUT_RING((pitch << 21) | (offset >> 5)); + OUT_RING(color); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } -static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv ) +static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv) { - if ( atomic_read( &dev_priv->idle_count ) == 0 ) { - r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); + if (atomic_read(&dev_priv->idle_count) == 0) { + r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); } else { - atomic_set( &dev_priv->idle_count, 0 ); + atomic_set(&dev_priv->idle_count, 0); } } #endif - /* ================================================================ * CCE command dispatch functions */ -static void r128_print_dirty( const char *msg, unsigned int flags ) +static void r128_print_dirty(const char *msg, unsigned int flags) { - DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", - msg, - flags, - (flags & R128_UPLOAD_CORE) ? "core, " : "", - (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", - (flags & R128_UPLOAD_SETUP) ? "setup, " : "", - (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", - (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", - (flags & R128_UPLOAD_MASKS) ? "masks, " : "", - (flags & R128_UPLOAD_WINDOW) ? "window, " : "", - (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", - (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" ); + DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", + msg, + flags, + (flags & R128_UPLOAD_CORE) ? "core, " : "", + (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", + (flags & R128_UPLOAD_SETUP) ? "setup, " : "", + (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", + (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", + (flags & R128_UPLOAD_MASKS) ? "masks, " : "", + (flags & R128_UPLOAD_WINDOW) ? "window, " : "", + (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", + (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : ""); } -static void r128_cce_dispatch_clear( drm_device_t *dev, - drm_r128_clear_t *clear ) +static void r128_cce_dispatch_clear(drm_device_t * dev, + drm_r128_clear_t * clear) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -368,102 +361,103 @@ static void r128_cce_dispatch_clear( drm_device_t *dev, unsigned int flags = clear->flags; int i; RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { + if (dev_priv->page_flipping && dev_priv->current_page == 1) { unsigned int tmp = flags; flags &= ~(R128_FRONT | R128_BACK); - if ( tmp & R128_FRONT ) flags |= R128_BACK; - if ( tmp & R128_BACK ) flags |= R128_FRONT; + if (tmp & R128_FRONT) + flags |= R128_BACK; + if (tmp & R128_BACK) + flags |= R128_FRONT; } - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; - DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", - pbox[i].x1, pbox[i].y1, pbox[i].x2, - pbox[i].y2, flags ); + DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n", + pbox[i].x1, pbox[i].y1, pbox[i].x2, + pbox[i].y2, flags); - if ( flags & (R128_FRONT | R128_BACK) ) { - BEGIN_RING( 2 ); + if (flags & (R128_FRONT | R128_BACK)) { + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); - OUT_RING( clear->color_mask ); + OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); + OUT_RING(clear->color_mask); ADVANCE_RING(); } - if ( flags & R128_FRONT ) { - BEGIN_RING( 6 ); + if (flags & R128_FRONT) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS); - OUT_RING( dev_priv->front_pitch_offset_c ); - OUT_RING( clear->clear_color ); + OUT_RING(dev_priv->front_pitch_offset_c); + OUT_RING(clear->clear_color); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } - if ( flags & R128_BACK ) { - BEGIN_RING( 6 ); + if (flags & R128_BACK) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS); - OUT_RING( dev_priv->back_pitch_offset_c ); - OUT_RING( clear->clear_color ); + OUT_RING(dev_priv->back_pitch_offset_c); + OUT_RING(clear->clear_color); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } - if ( flags & R128_DEPTH ) { - BEGIN_RING( 6 ); + if (flags & R128_DEPTH) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( clear->clear_depth ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(clear->clear_depth); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } } } -static void r128_cce_dispatch_swap( drm_device_t *dev ) +static void r128_cce_dispatch_swap(drm_device_t * dev) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -471,48 +465,46 @@ static void r128_cce_dispatch_swap( drm_device_t *dev ) drm_clip_rect_t *pbox = sarea_priv->boxes; int i; RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); #if R128_PERFORMANCE_BOXES /* Do some trivial performance monitoring... */ - r128_cce_performance_boxes( dev_priv ); + r128_cce_performance_boxes(dev_priv); #endif - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; - BEGIN_RING( 7 ); + BEGIN_RING(7); - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); + OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | + R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (dev_priv->color_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_MEMORY | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); /* Make this work even if front & back are flipped: */ if (dev_priv->current_page == 0) { - OUT_RING( dev_priv->back_pitch_offset_c ); - OUT_RING( dev_priv->front_pitch_offset_c ); - } - else { - OUT_RING( dev_priv->front_pitch_offset_c ); - OUT_RING( dev_priv->back_pitch_offset_c ); + OUT_RING(dev_priv->back_pitch_offset_c); + OUT_RING(dev_priv->front_pitch_offset_c); + } else { + OUT_RING(dev_priv->front_pitch_offset_c); + OUT_RING(dev_priv->back_pitch_offset_c); } - OUT_RING( (x << 16) | y ); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } @@ -523,38 +515,37 @@ static void r128_cce_dispatch_swap( drm_device_t *dev ) */ dev_priv->sarea_priv->last_frame++; - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); - OUT_RING( dev_priv->sarea_priv->last_frame ); + OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); + OUT_RING(dev_priv->sarea_priv->last_frame); ADVANCE_RING(); } -static void r128_cce_dispatch_flip( drm_device_t *dev ) +static void r128_cce_dispatch_flip(drm_device_t * dev) { drm_r128_private_t *dev_priv = dev->dev_private; RING_LOCALS; - DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", - __FUNCTION__, - dev_priv->current_page, - dev_priv->sarea_priv->pfCurrentPage); + DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage); #if R128_PERFORMANCE_BOXES /* Do some trivial performance monitoring... */ - r128_cce_performance_boxes( dev_priv ); + r128_cce_performance_boxes(dev_priv); #endif - BEGIN_RING( 4 ); + BEGIN_RING(4); R128_WAIT_UNTIL_PAGE_FLIPPED(); - OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) ); + OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0)); - if ( dev_priv->current_page == 0 ) { - OUT_RING( dev_priv->back_offset ); + if (dev_priv->current_page == 0) { + OUT_RING(dev_priv->back_offset); } else { - OUT_RING( dev_priv->front_offset ); + OUT_RING(dev_priv->front_offset); } ADVANCE_RING(); @@ -565,18 +556,17 @@ static void r128_cce_dispatch_flip( drm_device_t *dev ) */ dev_priv->sarea_priv->last_frame++; dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = - 1 - dev_priv->current_page; + 1 - dev_priv->current_page; - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); - OUT_RING( dev_priv->sarea_priv->last_frame ); + OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); + OUT_RING(dev_priv->sarea_priv->last_frame); ADVANCE_RING(); } -static void r128_cce_dispatch_vertex( drm_device_t *dev, - drm_buf_t *buf ) +static void r128_cce_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; @@ -587,50 +577,50 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev, int prim = buf_priv->prim; int i = 0; RING_LOCALS; - DRM_DEBUG( "buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox ); + DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox); - if ( 0 ) - r128_print_dirty( "dispatch_vertex", sarea_priv->dirty ); + if (0) + r128_print_dirty("dispatch_vertex", sarea_priv->dirty); - if ( buf->used ) { + if (buf->used) { buf_priv->dispatched = 1; - if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { - r128_emit_state( dev_priv ); + if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) { + r128_emit_state(dev_priv); } do { /* Emit the next set of up to three cliprects */ - if ( i < sarea_priv->nbox ) { - r128_emit_clip_rects( dev_priv, - &sarea_priv->boxes[i], - sarea_priv->nbox - i ); + if (i < sarea_priv->nbox) { + r128_emit_clip_rects(dev_priv, + &sarea_priv->boxes[i], + sarea_priv->nbox - i); } /* Emit the vertex buffer rendering commands */ - BEGIN_RING( 5 ); + BEGIN_RING(5); - OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) ); - OUT_RING( offset ); - OUT_RING( size ); - OUT_RING( format ); - OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | - (size << R128_CCE_VC_CNTL_NUM_SHIFT) ); + OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3)); + OUT_RING(offset); + OUT_RING(size); + OUT_RING(format); + OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | + (size << R128_CCE_VC_CNTL_NUM_SHIFT)); ADVANCE_RING(); i += 3; - } while ( i < sarea_priv->nbox ); + } while (i < sarea_priv->nbox); } - if ( buf_priv->discard ) { + if (buf_priv->discard) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the vertex buffer age */ - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); + OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); + OUT_RING(buf_priv->age); ADVANCE_RING(); @@ -646,17 +636,15 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev, sarea_priv->nbox = 0; } -static void r128_cce_dispatch_indirect( drm_device_t *dev, - drm_buf_t *buf, - int start, int end ) +static void r128_cce_dispatch_indirect(drm_device_t * dev, + drm_buf_t * buf, int start, int end) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; RING_LOCALS; - DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", - buf->idx, start, end ); + DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); - if ( start != end ) { + if (start != end) { int offset = buf->bus_address + start; int dwords = (end - start + 3) / sizeof(u32); @@ -664,33 +652,33 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev, * dwords, so if we've been given an odd number we must * pad the data with a Type-2 CCE packet. */ - if ( dwords & 1 ) { + if (dwords & 1) { u32 *data = (u32 *) - ((char *)dev->agp_buffer_map->handle - + buf->offset + start); - data[dwords++] = cpu_to_le32( R128_CCE_PACKET2 ); + ((char *)dev->agp_buffer_map->handle + + buf->offset + start); + data[dwords++] = cpu_to_le32(R128_CCE_PACKET2); } buf_priv->dispatched = 1; /* Fire off the indirect buffer */ - BEGIN_RING( 3 ); + BEGIN_RING(3); - OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) ); - OUT_RING( offset ); - OUT_RING( dwords ); + OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1)); + OUT_RING(offset); + OUT_RING(dwords); ADVANCE_RING(); } - if ( buf_priv->discard ) { + if (buf_priv->discard) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the indirect buffer age */ - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); + OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); + OUT_RING(buf_priv->age); ADVANCE_RING(); @@ -703,10 +691,9 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev, dev_priv->sarea_priv->last_dispatch++; } -static void r128_cce_dispatch_indices( drm_device_t *dev, - drm_buf_t *buf, - int start, int end, - int count ) +static void r128_cce_dispatch_indices(drm_device_t * dev, + drm_buf_t * buf, + int start, int end, int count) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; @@ -718,62 +705,62 @@ static void r128_cce_dispatch_indices( drm_device_t *dev, int dwords; int i = 0; RING_LOCALS; - DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count ); + DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count); - if ( 0 ) - r128_print_dirty( "dispatch_indices", sarea_priv->dirty ); + if (0) + r128_print_dirty("dispatch_indices", sarea_priv->dirty); - if ( start != end ) { + if (start != end) { buf_priv->dispatched = 1; - if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { - r128_emit_state( dev_priv ); + if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) { + r128_emit_state(dev_priv); } dwords = (end - start + 3) / sizeof(u32); - data = (u32 *)((char *)dev->agp_buffer_map->handle - + buf->offset + start); + data = (u32 *) ((char *)dev->agp_buffer_map->handle + + buf->offset + start); - data[0] = cpu_to_le32( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, - dwords-2 ) ); + data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, + dwords - 2)); - data[1] = cpu_to_le32( offset ); - data[2] = cpu_to_le32( R128_MAX_VB_VERTS ); - data[3] = cpu_to_le32( format ); - data[4] = cpu_to_le32( (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | - (count << 16)) ); + data[1] = cpu_to_le32(offset); + data[2] = cpu_to_le32(R128_MAX_VB_VERTS); + data[3] = cpu_to_le32(format); + data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | + (count << 16))); - if ( count & 0x1 ) { + if (count & 0x1) { #ifdef __LITTLE_ENDIAN - data[dwords-1] &= 0x0000ffff; + data[dwords - 1] &= 0x0000ffff; #else - data[dwords-1] &= 0xffff0000; + data[dwords - 1] &= 0xffff0000; #endif } do { /* Emit the next set of up to three cliprects */ - if ( i < sarea_priv->nbox ) { - r128_emit_clip_rects( dev_priv, - &sarea_priv->boxes[i], - sarea_priv->nbox - i ); + if (i < sarea_priv->nbox) { + r128_emit_clip_rects(dev_priv, + &sarea_priv->boxes[i], + sarea_priv->nbox - i); } - r128_cce_dispatch_indirect( dev, buf, start, end ); + r128_cce_dispatch_indirect(dev, buf, start, end); i += 3; - } while ( i < sarea_priv->nbox ); + } while (i < sarea_priv->nbox); } - if ( buf_priv->discard ) { + if (buf_priv->discard) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the vertex buffer age */ - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); + OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); + OUT_RING(buf_priv->age); ADVANCE_RING(); @@ -788,9 +775,8 @@ static void r128_cce_dispatch_indices( drm_device_t *dev, sarea_priv->nbox = 0; } -static int r128_cce_dispatch_blit( DRMFILE filp, - drm_device_t *dev, - drm_r128_blit_t *blit ) +static int r128_cce_dispatch_blit(DRMFILE filp, + drm_device_t * dev, drm_r128_blit_t * blit) { drm_r128_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; @@ -799,13 +785,13 @@ static int r128_cce_dispatch_blit( DRMFILE filp, u32 *data; int dword_shift, dwords; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* The compiler won't optimize away a division by a variable, * even if the only legal values are powers of two. Thus, we'll * use a shift instead. */ - switch ( blit->format ) { + switch (blit->format) { case R128_DATATYPE_ARGB8888: dword_shift = 0; break; @@ -821,7 +807,7 @@ static int r128_cce_dispatch_blit( DRMFILE filp, dword_shift = 2; break; default: - DRM_ERROR( "invalid blit format %d\n", blit->format ); + DRM_ERROR("invalid blit format %d\n", blit->format); return DRM_ERR(EINVAL); } @@ -830,10 +816,10 @@ static int r128_cce_dispatch_blit( DRMFILE filp, * data from the host data blit, otherwise part of the texture * image may be corrupted. */ - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); - OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI ); + OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); + OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI); ADVANCE_RING(); @@ -842,13 +828,13 @@ static int r128_cce_dispatch_blit( DRMFILE filp, buf = dma->buflist[blit->idx]; buf_priv = buf->dev_private; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", blit->idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", blit->idx); return DRM_ERR(EINVAL); } @@ -856,45 +842,43 @@ static int r128_cce_dispatch_blit( DRMFILE filp, dwords = (blit->width * blit->height) >> dword_shift; - data = (u32 *)((char *)dev->agp_buffer_map->handle + buf->offset); - - data[0] = cpu_to_le32( CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ) ); - data[1] = cpu_to_le32( (R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (blit->format << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_HOST_DATA | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS) ); - - data[2] = cpu_to_le32( (blit->pitch << 21) | (blit->offset >> 5) ); - data[3] = cpu_to_le32( 0xffffffff ); - data[4] = cpu_to_le32( 0xffffffff ); - data[5] = cpu_to_le32( (blit->y << 16) | blit->x ); - data[6] = cpu_to_le32( (blit->height << 16) | blit->width ); - data[7] = cpu_to_le32( dwords ); + data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); + + data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6)); + data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (blit->format << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_HOST_DATA | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS)); + + data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5)); + data[3] = cpu_to_le32(0xffffffff); + data[4] = cpu_to_le32(0xffffffff); + data[5] = cpu_to_le32((blit->y << 16) | blit->x); + data[6] = cpu_to_le32((blit->height << 16) | blit->width); + data[7] = cpu_to_le32(dwords); buf->used = (dwords + 8) * sizeof(u32); - r128_cce_dispatch_indirect( dev, buf, 0, buf->used ); + r128_cce_dispatch_indirect(dev, buf, 0, buf->used); /* Flush the pixel cache after the blit completes. This ensures * the texture data is written out to memory before rendering * continues. */ - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); - OUT_RING( R128_PC_FLUSH_GUI ); + OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); + OUT_RING(R128_PC_FLUSH_GUI); ADVANCE_RING(); return 0; } - /* ================================================================ * Tiled depth buffer management * @@ -902,8 +886,8 @@ static int r128_cce_dispatch_blit( DRMFILE filp, * have hardware stencil support. */ -static int r128_cce_dispatch_write_span( drm_device_t *dev, - drm_r128_depth_t *depth ) +static int r128_cce_dispatch_write_span(drm_device_t * dev, + drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, x, y; @@ -911,95 +895,95 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev, u8 *mask; int i, buffer_size, mask_size; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); count = depth->n; if (count > 4096 || count <= 0) return DRM_ERR(EMSGSIZE); - if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { + if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { return DRM_ERR(EFAULT); } - if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { + if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { return DRM_ERR(EFAULT); } buffer_size = depth->n * sizeof(u32); - buffer = drm_alloc( buffer_size, DRM_MEM_BUFS ); - if ( buffer == NULL ) + buffer = drm_alloc(buffer_size, DRM_MEM_BUFS); + if (buffer == NULL) return DRM_ERR(ENOMEM); - if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { - drm_free( buffer, buffer_size, DRM_MEM_BUFS); + if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } mask_size = depth->n * sizeof(u8); - if ( depth->mask ) { - mask = drm_alloc( mask_size, DRM_MEM_BUFS ); - if ( mask == NULL ) { - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + if (depth->mask) { + mask = drm_alloc(mask_size, DRM_MEM_BUFS); + if (mask == NULL) { + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); - drm_free( mask, mask_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { + drm_free(buffer, buffer_size, DRM_MEM_BUFS); + drm_free(mask, mask_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - for ( i = 0 ; i < count ; i++, x++ ) { - if ( mask[i] ) { - BEGIN_RING( 6 ); + for (i = 0; i < count; i++, x++) { + if (mask[i]) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(buffer[i]); - OUT_RING( (x << 16) | y ); - OUT_RING( (1 << 16) | 1 ); + OUT_RING((x << 16) | y); + OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } - drm_free( mask, mask_size, DRM_MEM_BUFS ); + drm_free(mask, mask_size, DRM_MEM_BUFS); } else { - for ( i = 0 ; i < count ; i++, x++ ) { - BEGIN_RING( 6 ); + for (i = 0; i < count; i++, x++) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(buffer[i]); - OUT_RING( (x << 16) | y ); - OUT_RING( (1 << 16) | 1 ); + OUT_RING((x << 16) | y); + OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return 0; } -static int r128_cce_dispatch_write_pixels( drm_device_t *dev, - drm_r128_depth_t *depth ) +static int r128_cce_dispatch_write_pixels(drm_device_t * dev, + drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, *x, *y; @@ -1007,7 +991,7 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev, u8 *mask; int i, xbuf_size, ybuf_size, buffer_size, mask_size; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); count = depth->n; if (count > 4096 || count <= 0) @@ -1015,270 +999,266 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev, xbuf_size = count * sizeof(*x); ybuf_size = count * sizeof(*y); - x = drm_alloc( xbuf_size, DRM_MEM_BUFS ); - if ( x == NULL ) { + x = drm_alloc(xbuf_size, DRM_MEM_BUFS); + if (x == NULL) { return DRM_ERR(ENOMEM); } - y = drm_alloc( ybuf_size, DRM_MEM_BUFS ); - if ( y == NULL ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); + y = drm_alloc(ybuf_size, DRM_MEM_BUFS); + if (y == NULL) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - if ( DRM_COPY_FROM_USER( y, depth->y, xbuf_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } buffer_size = depth->n * sizeof(u32); - buffer = drm_alloc( buffer_size, DRM_MEM_BUFS ); - if ( buffer == NULL ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + buffer = drm_alloc(buffer_size, DRM_MEM_BUFS); + if (buffer == NULL) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - if ( depth->mask ) { + if (depth->mask) { mask_size = depth->n * sizeof(u8); - mask = drm_alloc( mask_size, DRM_MEM_BUFS ); - if ( mask == NULL ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + mask = drm_alloc(mask_size, DRM_MEM_BUFS); + if (mask == NULL) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); - drm_free( mask, mask_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); + drm_free(buffer, buffer_size, DRM_MEM_BUFS); + drm_free(mask, mask_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - for ( i = 0 ; i < count ; i++ ) { - if ( mask[i] ) { - BEGIN_RING( 6 ); + for (i = 0; i < count; i++) { + if (mask[i]) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(buffer[i]); - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (1 << 16) | 1 ); + OUT_RING((x[i] << 16) | y[i]); + OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } - drm_free( mask, mask_size, DRM_MEM_BUFS ); + drm_free(mask, mask_size, DRM_MEM_BUFS); } else { - for ( i = 0 ; i < count ; i++ ) { - BEGIN_RING( 6 ); + for (i = 0; i < count; i++) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(buffer[i]); - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (1 << 16) | 1 ); + OUT_RING((x[i] << 16) | y[i]); + OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return 0; } -static int r128_cce_dispatch_read_span( drm_device_t *dev, - drm_r128_depth_t *depth ) +static int r128_cce_dispatch_read_span(drm_device_t * dev, + drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, x, y; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); count = depth->n; if (count > 4096 || count <= 0) return DRM_ERR(EMSGSIZE); - if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { + if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { return DRM_ERR(EFAULT); } - if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { + if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { return DRM_ERR(EFAULT); } - BEGIN_RING( 7 ); + BEGIN_RING(7); - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); + OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | + R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_MEMORY | + R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( dev_priv->span_pitch_offset_c ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(dev_priv->span_pitch_offset_c); - OUT_RING( (x << 16) | y ); - OUT_RING( (0 << 16) | 0 ); - OUT_RING( (count << 16) | 1 ); + OUT_RING((x << 16) | y); + OUT_RING((0 << 16) | 0); + OUT_RING((count << 16) | 1); ADVANCE_RING(); return 0; } -static int r128_cce_dispatch_read_pixels( drm_device_t *dev, - drm_r128_depth_t *depth ) +static int r128_cce_dispatch_read_pixels(drm_device_t * dev, + drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, *x, *y; int i, xbuf_size, ybuf_size; RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); count = depth->n; if (count > 4096 || count <= 0) return DRM_ERR(EMSGSIZE); - if ( count > dev_priv->depth_pitch ) { + if (count > dev_priv->depth_pitch) { count = dev_priv->depth_pitch; } xbuf_size = count * sizeof(*x); ybuf_size = count * sizeof(*y); - x = drm_alloc( xbuf_size, DRM_MEM_BUFS ); - if ( x == NULL ) { + x = drm_alloc(xbuf_size, DRM_MEM_BUFS); + if (x == NULL) { return DRM_ERR(ENOMEM); } - y = drm_alloc( ybuf_size, DRM_MEM_BUFS ); - if ( y == NULL ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); + y = drm_alloc(ybuf_size, DRM_MEM_BUFS); + if (y == NULL) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - if ( DRM_COPY_FROM_USER( y, depth->y, ybuf_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - for ( i = 0 ; i < count ; i++ ) { - BEGIN_RING( 7 ); + for (i = 0; i < count; i++) { + BEGIN_RING(7); - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); + OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | + R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_MEMORY | + R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( dev_priv->span_pitch_offset_c ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(dev_priv->span_pitch_offset_c); - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (i << 16) | 0 ); - OUT_RING( (1 << 16) | 1 ); + OUT_RING((x[i] << 16) | y[i]); + OUT_RING((i << 16) | 0); + OUT_RING((1 << 16) | 1); ADVANCE_RING(); } - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return 0; } - /* ================================================================ * Polygon stipple */ -static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple ) +static void r128_cce_dispatch_stipple(drm_device_t * dev, u32 * stipple) { drm_r128_private_t *dev_priv = dev->dev_private; int i; RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - BEGIN_RING( 33 ); + BEGIN_RING(33); - OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) ); - for ( i = 0 ; i < 32 ; i++ ) { - OUT_RING( stipple[i] ); + OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31)); + for (i = 0; i < 32; i++) { + OUT_RING(stipple[i]); } ADVANCE_RING(); } - /* ================================================================ * IOCTL functions */ -int r128_cce_clear( DRM_IOCTL_ARGS ) +int r128_cce_clear(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_clear_t clear; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( clear, (drm_r128_clear_t __user *) data, - sizeof(clear) ); + DRM_COPY_FROM_USER_IOCTL(clear, (drm_r128_clear_t __user *) data, + sizeof(clear)); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; - r128_cce_dispatch_clear( dev, &clear ); + r128_cce_dispatch_clear(dev, &clear); COMMIT_RING(); /* Make sure we restore the 3D state next time. @@ -1288,17 +1268,17 @@ int r128_cce_clear( DRM_IOCTL_ARGS ) return 0; } -static int r128_do_init_pageflip( drm_device_t *dev ) +static int r128_do_init_pageflip(drm_device_t * dev) { drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET ); - dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL ); + dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET); + dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL); - R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset ); - R128_WRITE( R128_CRTC_OFFSET_CNTL, - dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL ); + R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset); + R128_WRITE(R128_CRTC_OFFSET_CNTL, + dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL); dev_priv->page_flipping = 1; dev_priv->current_page = 0; @@ -1307,16 +1287,16 @@ static int r128_do_init_pageflip( drm_device_t *dev ) return 0; } -int r128_do_cleanup_pageflip( drm_device_t *dev ) +int r128_do_cleanup_pageflip(drm_device_t * dev) { drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset ); - R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); + R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset); + R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl); if (dev_priv->current_page != 0) { - r128_cce_dispatch_flip( dev ); + r128_cce_dispatch_flip(dev); COMMIT_RING(); } @@ -1325,43 +1305,43 @@ int r128_do_cleanup_pageflip( drm_device_t *dev ) } /* Swapping and flipping are different operations, need different ioctls. - * They can & should be intermixed to support multiple 3d windows. + * They can & should be intermixed to support multiple 3d windows. */ -int r128_cce_flip( DRM_IOCTL_ARGS ) +int r128_cce_flip(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - if (!dev_priv->page_flipping) - r128_do_init_pageflip( dev ); + if (!dev_priv->page_flipping) + r128_do_init_pageflip(dev); - r128_cce_dispatch_flip( dev ); + r128_cce_dispatch_flip(dev); COMMIT_RING(); return 0; } -int r128_cce_swap( DRM_IOCTL_ARGS ) +int r128_cce_swap(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; - r128_cce_dispatch_swap( dev ); + r128_cce_dispatch_swap(dev); dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS); @@ -1369,7 +1349,7 @@ int r128_cce_swap( DRM_IOCTL_ARGS ) return 0; } -int r128_cce_vertex( DRM_IOCTL_ARGS ) +int r128_cce_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; @@ -1378,44 +1358,43 @@ int r128_cce_vertex( DRM_IOCTL_ARGS ) drm_r128_buf_priv_t *buf_priv; drm_r128_vertex_t vertex; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( vertex, (drm_r128_vertex_t __user *) data, - sizeof(vertex) ); + DRM_COPY_FROM_USER_IOCTL(vertex, (drm_r128_vertex_t __user *) data, + sizeof(vertex)); - DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", - DRM_CURRENTPID, - vertex.idx, vertex.count, vertex.discard ); + DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", + DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard); - if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1 ); + if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + vertex.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - if ( vertex.prim < 0 || - vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { - DRM_ERROR( "buffer prim %d\n", vertex.prim ); + if (vertex.prim < 0 || + vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { + DRM_ERROR("buffer prim %d\n", vertex.prim); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[vertex.idx]; buf_priv = buf->dev_private; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", vertex.idx); return DRM_ERR(EINVAL); } @@ -1423,13 +1402,13 @@ int r128_cce_vertex( DRM_IOCTL_ARGS ) buf_priv->prim = vertex.prim; buf_priv->discard = vertex.discard; - r128_cce_dispatch_vertex( dev, buf ); + r128_cce_dispatch_vertex(dev, buf); COMMIT_RING(); return 0; } -int r128_cce_indices( DRM_IOCTL_ARGS ) +int r128_cce_indices(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; @@ -1439,55 +1418,54 @@ int r128_cce_indices( DRM_IOCTL_ARGS ) drm_r128_indices_t elts; int count; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( elts, (drm_r128_indices_t __user *) data, - sizeof(elts) ); + DRM_COPY_FROM_USER_IOCTL(elts, (drm_r128_indices_t __user *) data, + sizeof(elts)); - DRM_DEBUG( "pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, - elts.idx, elts.start, elts.end, elts.discard ); + DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, + elts.idx, elts.start, elts.end, elts.discard); - if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - elts.idx, dma->buf_count - 1 ); + if (elts.idx < 0 || elts.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + elts.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - if ( elts.prim < 0 || - elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { - DRM_ERROR( "buffer prim %d\n", elts.prim ); + if (elts.prim < 0 || elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { + DRM_ERROR("buffer prim %d\n", elts.prim); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[elts.idx]; buf_priv = buf->dev_private; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", elts.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", elts.idx); return DRM_ERR(EINVAL); } count = (elts.end - elts.start) / sizeof(u16); elts.start -= R128_INDEX_PRIM_OFFSET; - if ( elts.start & 0x7 ) { - DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); + if (elts.start & 0x7) { + DRM_ERROR("misaligned buffer 0x%x\n", elts.start); return DRM_ERR(EINVAL); } - if ( elts.start < buf->used ) { - DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); + if (elts.start < buf->used) { + DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); return DRM_ERR(EINVAL); } @@ -1495,13 +1473,13 @@ int r128_cce_indices( DRM_IOCTL_ARGS ) buf_priv->prim = elts.prim; buf_priv->discard = elts.discard; - r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count ); + r128_cce_dispatch_indices(dev, buf, elts.start, elts.end, count); COMMIT_RING(); return 0; } -int r128_cce_blit( DRM_IOCTL_ARGS ) +int r128_cce_blit(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; @@ -1509,83 +1487,82 @@ int r128_cce_blit( DRM_IOCTL_ARGS ) drm_r128_blit_t blit; int ret; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( blit, (drm_r128_blit_t __user *) data, - sizeof(blit) ); + DRM_COPY_FROM_USER_IOCTL(blit, (drm_r128_blit_t __user *) data, + sizeof(blit)); - DRM_DEBUG( "pid=%d index=%d\n", DRM_CURRENTPID, blit.idx ); + DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit.idx); - if ( blit.idx < 0 || blit.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - blit.idx, dma->buf_count - 1 ); + if (blit.idx < 0 || blit.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + blit.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); - ret = r128_cce_dispatch_blit( filp, dev, &blit ); + ret = r128_cce_dispatch_blit(filp, dev, &blit); COMMIT_RING(); return ret; } -int r128_cce_depth( DRM_IOCTL_ARGS ) +int r128_cce_depth(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_depth_t depth; int ret; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( depth, (drm_r128_depth_t __user *) data, - sizeof(depth) ); + DRM_COPY_FROM_USER_IOCTL(depth, (drm_r128_depth_t __user *) data, + sizeof(depth)); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); ret = DRM_ERR(EINVAL); - switch ( depth.func ) { + switch (depth.func) { case R128_WRITE_SPAN: - ret = r128_cce_dispatch_write_span( dev, &depth ); + ret = r128_cce_dispatch_write_span(dev, &depth); case R128_WRITE_PIXELS: - ret = r128_cce_dispatch_write_pixels( dev, &depth ); + ret = r128_cce_dispatch_write_pixels(dev, &depth); case R128_READ_SPAN: - ret = r128_cce_dispatch_read_span( dev, &depth ); + ret = r128_cce_dispatch_read_span(dev, &depth); case R128_READ_PIXELS: - ret = r128_cce_dispatch_read_pixels( dev, &depth ); + ret = r128_cce_dispatch_read_pixels(dev, &depth); } COMMIT_RING(); return ret; } -int r128_cce_stipple( DRM_IOCTL_ARGS ) +int r128_cce_stipple(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_stipple_t stipple; u32 mask[32]; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( stipple, (drm_r128_stipple_t __user *) data, - sizeof(stipple) ); + DRM_COPY_FROM_USER_IOCTL(stipple, (drm_r128_stipple_t __user *) data, + sizeof(stipple)); - if ( DRM_COPY_FROM_USER( &mask, stipple.mask, - 32 * sizeof(u32) ) ) - return DRM_ERR( EFAULT ); + if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) + return DRM_ERR(EFAULT); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - r128_cce_dispatch_stipple( dev, mask ); + r128_cce_dispatch_stipple(dev, mask); COMMIT_RING(); return 0; } -int r128_cce_indirect( DRM_IOCTL_ARGS ) +int r128_cce_indirect(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; @@ -1597,47 +1574,46 @@ int r128_cce_indirect( DRM_IOCTL_ARGS ) RING_LOCALS; #endif - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( indirect, (drm_r128_indirect_t __user *) data, - sizeof(indirect) ); + DRM_COPY_FROM_USER_IOCTL(indirect, (drm_r128_indirect_t __user *) data, + sizeof(indirect)); - DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", - indirect.idx, indirect.start, - indirect.end, indirect.discard ); + DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n", + indirect.idx, indirect.start, indirect.end, indirect.discard); - if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - indirect.idx, dma->buf_count - 1 ); + if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + indirect.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } buf = dma->buflist[indirect.idx]; buf_priv = buf->dev_private; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", indirect.idx); return DRM_ERR(EINVAL); } - if ( indirect.start < buf->used ) { - DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", - indirect.start, buf->used ); + if (indirect.start < buf->used) { + DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", + indirect.start, buf->used); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf->used = indirect.end; buf_priv->discard = indirect.discard; @@ -1646,7 +1622,7 @@ int r128_cce_indirect( DRM_IOCTL_ARGS ) /* Wait for the 3D stream to idle before the indirect buffer * containing 2D acceleration commands is processed. */ - BEGIN_RING( 2 ); + BEGIN_RING(2); RADEON_WAIT_UNTIL_3D_IDLE(); ADVANCE_RING(); #endif @@ -1655,30 +1631,30 @@ int r128_cce_indirect( DRM_IOCTL_ARGS ) * X server. This is insecure and is thus only available to * privileged clients. */ - r128_cce_dispatch_indirect( dev, buf, indirect.start, indirect.end ); + r128_cce_dispatch_indirect(dev, buf, indirect.start, indirect.end); COMMIT_RING(); return 0; } -int r128_getparam( DRM_IOCTL_ARGS ) +int r128_getparam(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_getparam_t param; int value; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( param, (drm_r128_getparam_t __user *)data, - sizeof(param) ); + DRM_COPY_FROM_USER_IOCTL(param, (drm_r128_getparam_t __user *) data, + sizeof(param)); - DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); + DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - switch( param.param ) { + switch (param.param) { case R128_PARAM_IRQ_NR: value = dev->irq; break; @@ -1686,25 +1662,25 @@ int r128_getparam( DRM_IOCTL_ARGS ) return DRM_ERR(EINVAL); } - if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } - + return 0; } -void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp) +void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp) { - if ( dev->dev_private ) { + if (dev->dev_private) { drm_r128_private_t *dev_priv = dev->dev_private; - if ( dev_priv->page_flipping ) { - r128_do_cleanup_pageflip( dev ); + if (dev_priv->page_flipping) { + r128_do_cleanup_pageflip(dev); } - } + } } -void r128_driver_pretakedown(drm_device_t *dev) +void r128_driver_pretakedown(drm_device_t * dev) { - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); } diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 98bc4c46..33a10ab5 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -37,526 +37,524 @@ /* CP microcode (from ATI) */ static u32 R200_cp_microcode[][2] = { - { 0x21007000, 0000000000 }, - { 0x20007000, 0000000000 }, - { 0x000000ab, 0x00000004 }, - { 0x000000af, 0x00000004 }, - { 0x66544a49, 0000000000 }, - { 0x49494174, 0000000000 }, - { 0x54517d83, 0000000000 }, - { 0x498d8b64, 0000000000 }, - { 0x49494949, 0000000000 }, - { 0x49da493c, 0000000000 }, - { 0x49989898, 0000000000 }, - { 0xd34949d5, 0000000000 }, - { 0x9dc90e11, 0000000000 }, - { 0xce9b9b9b, 0000000000 }, - { 0x000f0000, 0x00000016 }, - { 0x352e232c, 0000000000 }, - { 0x00000013, 0x00000004 }, - { 0x000f0000, 0x00000016 }, - { 0x352e272c, 0000000000 }, - { 0x000f0001, 0x00000016 }, - { 0x3239362f, 0000000000 }, - { 0x000077ef, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00000016, 0x00000004 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000002 }, - { 0x00000016, 0x00000004 }, - { 0x000077e0, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x000037e1, 0x00000002 }, - { 0x040067e1, 0x00000006 }, - { 0x000077e0, 0x00000002 }, - { 0x000077e1, 0x00000002 }, - { 0x000077e1, 0x00000006 }, - { 0xffffffff, 0000000000 }, - { 0x10000000, 0000000000 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000006 }, - { 0x00007675, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802b, 0x00000002 }, - { 0x04002676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0000002e, 0x00000018 }, - { 0x0000002e, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x0000002f, 0x00000018 }, - { 0x0000002f, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x01605000, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00098000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x64c0603d, 0x00000004 }, - { 0x00080000, 0x00000016 }, - { 0000000000, 0000000000 }, - { 0x0400251d, 0x00000002 }, - { 0x00007580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x04002580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x00000046, 0x00000004 }, - { 0x00005000, 0000000000 }, - { 0x00061000, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x00019000, 0x00000002 }, - { 0x00011055, 0x00000014 }, - { 0x00000055, 0x00000012 }, - { 0x0400250f, 0x00000002 }, - { 0x0000504a, 0x00000004 }, - { 0x00007565, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000051, 0x00000004 }, - { 0x01e655b4, 0x00000002 }, - { 0x4401b0dc, 0x00000002 }, - { 0x01c110dc, 0x00000002 }, - { 0x2666705d, 0x00000018 }, - { 0x040c2565, 0x00000002 }, - { 0x0000005d, 0x00000018 }, - { 0x04002564, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000054, 0x00000004 }, - { 0x00401060, 0x00000008 }, - { 0x00101000, 0x00000002 }, - { 0x000d80ff, 0x00000002 }, - { 0x00800063, 0x00000008 }, - { 0x000f9000, 0x00000002 }, - { 0x000e00ff, 0x00000002 }, - { 0000000000, 0x00000006 }, - { 0x00000080, 0x00000018 }, - { 0x00000054, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00009000, 0x00000002 }, - { 0x00041000, 0x00000002 }, - { 0x0c00350e, 0x00000002 }, - { 0x00049000, 0x00000002 }, - { 0x00051000, 0x00000002 }, - { 0x01e785f8, 0x00000002 }, - { 0x00200000, 0x00000002 }, - { 0x00600073, 0x0000000c }, - { 0x00007563, 0x00000002 }, - { 0x006075f0, 0x00000021 }, - { 0x20007068, 0x00000004 }, - { 0x00005068, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00007577, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x0000750f, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00600076, 0x0000000c }, - { 0x006075f0, 0x00000021 }, - { 0x000075f8, 0x00000002 }, - { 0x00000076, 0x00000004 }, - { 0x000a750e, 0x00000002 }, - { 0x0020750f, 0x00000002 }, - { 0x00600079, 0x00000004 }, - { 0x00007570, 0x00000002 }, - { 0x00007571, 0x00000002 }, - { 0x00007572, 0x00000006 }, - { 0x00005000, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00007568, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000084, 0x0000000c }, - { 0x00058000, 0x00000002 }, - { 0x0c607562, 0x00000002 }, - { 0x00000086, 0x00000004 }, - { 0x00600085, 0x00000004 }, - { 0x400070dd, 0000000000 }, - { 0x000380dd, 0x00000002 }, - { 0x00000093, 0x0000001c }, - { 0x00065095, 0x00000018 }, - { 0x040025bb, 0x00000002 }, - { 0x00061096, 0x00000018 }, - { 0x040075bc, 0000000000 }, - { 0x000075bb, 0x00000002 }, - { 0x000075bc, 0000000000 }, - { 0x00090000, 0x00000006 }, - { 0x00090000, 0x00000002 }, - { 0x000d8002, 0x00000006 }, - { 0x00005000, 0x00000002 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x01665000, 0x00000002 }, - { 0x000a0000, 0x00000002 }, - { 0x000671cc, 0x00000002 }, - { 0x0286f1cd, 0x00000002 }, - { 0x000000a3, 0x00000010 }, - { 0x21007000, 0000000000 }, - { 0x000000aa, 0x0000001c }, - { 0x00065000, 0x00000002 }, - { 0x000a0000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x000b0000, 0x00000002 }, - { 0x38067000, 0x00000002 }, - { 0x000a00a6, 0x00000004 }, - { 0x20007000, 0000000000 }, - { 0x01200000, 0x00000002 }, - { 0x20077000, 0x00000002 }, - { 0x01200000, 0x00000002 }, - { 0x20007000, 0000000000 }, - { 0x00061000, 0x00000002 }, - { 0x0120751b, 0x00000002 }, - { 0x8040750a, 0x00000002 }, - { 0x8040750b, 0x00000002 }, - { 0x00110000, 0x00000002 }, - { 0x000380dd, 0x00000002 }, - { 0x000000bd, 0x0000001c }, - { 0x00061096, 0x00000018 }, - { 0x844075bd, 0x00000002 }, - { 0x00061095, 0x00000018 }, - { 0x840075bb, 0x00000002 }, - { 0x00061096, 0x00000018 }, - { 0x844075bc, 0x00000002 }, - { 0x000000c0, 0x00000004 }, - { 0x804075bd, 0x00000002 }, - { 0x800075bb, 0x00000002 }, - { 0x804075bc, 0x00000002 }, - { 0x00108000, 0x00000002 }, - { 0x01400000, 0x00000002 }, - { 0x006000c4, 0x0000000c }, - { 0x20c07000, 0x00000020 }, - { 0x000000c6, 0x00000012 }, - { 0x00800000, 0x00000006 }, - { 0x0080751d, 0x00000006 }, - { 0x000025bb, 0x00000002 }, - { 0x000040c0, 0x00000004 }, - { 0x0000775c, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460275d, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x00007999, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460299b, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x01e00830, 0x00000002 }, - { 0x21007000, 0000000000 }, - { 0x00005000, 0x00000002 }, - { 0x00038042, 0x00000002 }, - { 0x040025e0, 0x00000002 }, - { 0x000075e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000380d9, 0x00000002 }, - { 0x04007394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, + {0x21007000, 0000000000}, + {0x20007000, 0000000000}, + {0x000000ab, 0x00000004}, + {0x000000af, 0x00000004}, + {0x66544a49, 0000000000}, + {0x49494174, 0000000000}, + {0x54517d83, 0000000000}, + {0x498d8b64, 0000000000}, + {0x49494949, 0000000000}, + {0x49da493c, 0000000000}, + {0x49989898, 0000000000}, + {0xd34949d5, 0000000000}, + {0x9dc90e11, 0000000000}, + {0xce9b9b9b, 0000000000}, + {0x000f0000, 0x00000016}, + {0x352e232c, 0000000000}, + {0x00000013, 0x00000004}, + {0x000f0000, 0x00000016}, + {0x352e272c, 0000000000}, + {0x000f0001, 0x00000016}, + {0x3239362f, 0000000000}, + {0x000077ef, 0x00000002}, + {0x00061000, 0x00000002}, + {0x00000020, 0x0000001a}, + {0x00004000, 0x0000001e}, + {0x00061000, 0x00000002}, + {0x00000020, 0x0000001a}, + {0x00004000, 0x0000001e}, + {0x00061000, 0x00000002}, + {0x00000020, 0x0000001a}, + {0x00004000, 0x0000001e}, + {0x00000016, 0x00000004}, + {0x0003802a, 0x00000002}, + {0x040067e0, 0x00000002}, + {0x00000016, 0x00000004}, + {0x000077e0, 0x00000002}, + {0x00065000, 0x00000002}, + {0x000037e1, 0x00000002}, + {0x040067e1, 0x00000006}, + {0x000077e0, 0x00000002}, + {0x000077e1, 0x00000002}, + {0x000077e1, 0x00000006}, + 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{0x000077e1, 0x00000006}, + {0xffffffff, 0000000000}, + {0x10000000, 0000000000}, + {0x0003802b, 0x00000002}, + {0x040067e0, 0x00000006}, + {0x00007675, 0x00000002}, + {0x00007676, 0x00000002}, + {0x00007677, 0x00000002}, + {0x00007678, 0x00000006}, + {0x0003802c, 0x00000002}, + {0x04002676, 0x00000002}, + {0x00007677, 0x00000002}, + {0x00007678, 0x00000006}, + {0x0000002f, 0x00000018}, + {0x0000002f, 0x00000018}, + {0000000000, 0x00000006}, + {0x00000030, 0x00000018}, + {0x00000030, 0x00000018}, + {0000000000, 0x00000006}, + {0x01605000, 0x00000002}, + {0x00065000, 0x00000002}, + {0x00098000, 0x00000002}, + {0x00061000, 0x00000002}, + {0x64c0603e, 0x00000004}, + {0x000380e6, 0x00000002}, + {0x040025c5, 0x00000002}, + {0x00080000, 0x00000016}, + {0000000000, 0000000000}, + {0x0400251d, 0x00000002}, + {0x00007580, 0x00000002}, + {0x00067581, 0x00000002}, + {0x04002580, 0x00000002}, + {0x00067581, 0x00000002}, + {0x00000049, 0x00000004}, + {0x00005000, 0000000000}, + {0x000380e6, 0x00000002}, + {0x040025c5, 0x00000002}, + {0x00061000, 0x00000002}, + {0x0000750e, 0x00000002}, + {0x00019000, 0x00000002}, + {0x00011055, 0x00000014}, + {0x00000055, 0x00000012}, + {0x0400250f, 0x00000002}, + {0x0000504f, 0x00000004}, + {0x000380e6, 0x00000002}, + {0x040025c5, 0x00000002}, + {0x00007565, 0x00000002}, + {0x00007566, 0x00000002}, + {0x00000058, 0x00000004}, + {0x000380e6, 0x00000002}, + {0x040025c5, 0x00000002}, + {0x01e655b4, 0x00000002}, + {0x4401b0e4, 0x00000002}, + {0x01c110e4, 0x00000002}, + {0x26667066, 0x00000018}, + {0x040c2565, 0x00000002}, + {0x00000066, 0x00000018}, + {0x04002564, 0x00000002}, + {0x00007566, 0x00000002}, + {0x0000005d, 0x00000004}, + {0x00401069, 0x00000008}, + {0x00101000, 0x00000002}, + {0x000d80ff, 0x00000002}, + {0x0080006c, 0x00000008}, + {0x000f9000, 0x00000002}, + {0x000e00ff, 0x00000002}, + {0000000000, 0x00000006}, + {0x0000008f, 0x00000018}, + {0x0000005b, 0x00000004}, + {0x000380e6, 0x00000002}, + {0x040025c5, 0x00000002}, + {0x00007576, 0x00000002}, + {0x00065000, 0x00000002}, + {0x00009000, 0x00000002}, + {0x00041000, 0x00000002}, + {0x0c00350e, 0x00000002}, + {0x00049000, 0x00000002}, + {0x00051000, 0x00000002}, + {0x01e785f8, 0x00000002}, + {0x00200000, 0x00000002}, + {0x0060007e, 0x0000000c}, + {0x00007563, 0x00000002}, + {0x006075f0, 0x00000021}, + {0x20007073, 0x00000004}, + {0x00005073, 0x00000004}, + {0x000380e6, 0x00000002}, + {0x040025c5, 0x00000002}, + {0x00007576, 0x00000002}, + {0x00007577, 0x00000002}, + {0x0000750e, 0x00000002}, + {0x0000750f, 0x00000002}, + {0x00a05000, 0x00000002}, + {0x00600083, 0x0000000c}, + {0x006075f0, 0x00000021}, + {0x000075f8, 0x00000002}, + {0x00000083, 0x00000004}, + {0x000a750e, 0x00000002}, + {0x000380e6, 0x00000002}, + {0x040025c5, 0x00000002}, + {0x0020750f, 0x00000002}, + {0x00600086, 0x00000004}, + {0x00007570, 0x00000002}, + {0x00007571, 0x00000002}, + {0x00007572, 0x00000006}, + {0x000380e6, 0x00000002}, + {0x040025c5, 0x00000002}, + {0x00005000, 0x00000002}, + {0x00a05000, 0x00000002}, + {0x00007568, 0x00000002}, + {0x00061000, 0x00000002}, + {0x00000095, 0x0000000c}, + {0x00058000, 0x00000002}, + {0x0c607562, 0x00000002}, + {0x00000097, 0x00000004}, + {0x000380e6, 0x00000002}, + {0x040025c5, 0x00000002}, + {0x00600096, 0x00000004}, + {0x400070e5, 0000000000}, + {0x000380e6, 0x00000002}, + {0x040025c5, 0x00000002}, + {0x000380e5, 0x00000002}, + {0x000000a8, 0x0000001c}, + {0x000650aa, 0x00000018}, + {0x040025bb, 0x00000002}, + {0x000610ab, 0x00000018}, + {0x040075bc, 0000000000}, + {0x000075bb, 0x00000002}, + {0x000075bc, 0000000000}, + {0x00090000, 0x00000006}, + {0x00090000, 0x00000002}, + {0x000d8002, 0x00000006}, + {0x00007832, 0x00000002}, + {0x00005000, 0x00000002}, + {0x000380e7, 0x00000002}, + {0x04002c97, 0x00000002}, + {0x00007820, 0x00000002}, + {0x00007821, 0x00000002}, + {0x00007800, 0000000000}, + {0x01200000, 0x00000002}, + {0x20077000, 0x00000002}, + {0x01200000, 0x00000002}, + {0x20007000, 0x00000002}, + {0x00061000, 0x00000002}, + {0x0120751b, 0x00000002}, + {0x8040750a, 0x00000002}, + {0x8040750b, 0x00000002}, + {0x00110000, 0x00000002}, + {0x000380e5, 0x00000002}, + {0x000000c6, 0x0000001c}, + {0x000610ab, 0x00000018}, + {0x844075bd, 0x00000002}, + {0x000610aa, 0x00000018}, + {0x840075bb, 0x00000002}, + {0x000610ab, 0x00000018}, + {0x844075bc, 0x00000002}, + {0x000000c9, 0x00000004}, + {0x804075bd, 0x00000002}, + {0x800075bb, 0x00000002}, + {0x804075bc, 0x00000002}, + {0x00108000, 0x00000002}, + {0x01400000, 0x00000002}, + {0x006000cd, 0x0000000c}, + {0x20c07000, 0x00000020}, + {0x000000cf, 0x00000012}, + {0x00800000, 0x00000006}, + {0x0080751d, 0x00000006}, + {0000000000, 0000000000}, + {0x0000775c, 0x00000002}, + {0x00a05000, 0x00000002}, + {0x00661000, 0x00000002}, + {0x0460275d, 0x00000020}, + {0x00004000, 0000000000}, + {0x01e00830, 0x00000002}, + {0x21007000, 0000000000}, + {0x6464614d, 0000000000}, + {0x69687420, 0000000000}, + {0x00000073, 0000000000}, + {0000000000, 0000000000}, + {0x00005000, 0x00000002}, + {0x000380d0, 0x00000002}, + {0x040025e0, 0x00000002}, + {0x000075e1, 0000000000}, + {0x00000001, 0000000000}, + {0x000380e0, 0x00000002}, + {0x04002394, 0x00000002}, + {0x00005000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0x00000008, 0000000000}, + {0x00000004, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, }; - -int RADEON_READ_PLL(drm_device_t *dev, int addr) +int RADEON_READ_PLL(drm_device_t * dev, int addr) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -565,138 +563,133 @@ int RADEON_READ_PLL(drm_device_t *dev, int addr) } #if RADEON_FIFO_DEBUG -static void radeon_status( drm_radeon_private_t *dev_priv ) +static void radeon_status(drm_radeon_private_t * dev_priv) { - printk( "%s:\n", __FUNCTION__ ); - printk( "RBBM_STATUS = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) ); - printk( "CP_RB_RTPR = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) ); - printk( "CP_RB_WTPR = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) ); - printk( "AIC_CNTL = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) ); - printk( "AIC_STAT = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_STAT ) ); - printk( "AIC_PT_BASE = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) ); - printk( "TLB_ADDR = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) ); - printk( "TLB_DATA = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) ); + printk("%s:\n", __FUNCTION__); + printk("RBBM_STATUS = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); + printk("CP_RB_RTPR = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); + printk("CP_RB_WTPR = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); + printk("AIC_CNTL = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); + printk("AIC_STAT = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_AIC_STAT)); + printk("AIC_PT_BASE = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); + printk("TLB_ADDR = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); + printk("TLB_DATA = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); } #endif - /* ================================================================ * Engine, FIFO control */ -static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv ) +static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) { u32 tmp; int i; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ); + tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT); tmp |= RADEON_RB2D_DC_FLUSH_ALL; - RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp ); + RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp); - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ) - & RADEON_RB2D_DC_BUSY) ) { + for (i = 0; i < dev_priv->usec_timeout; i++) { + if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT) + & RADEON_RB2D_DC_BUSY)) { return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if RADEON_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - radeon_status( dev_priv ); + DRM_ERROR("failed!\n"); + radeon_status(dev_priv); #endif return DRM_ERR(EBUSY); } -static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv, - int entries ) +static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) { int i; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - int slots = ( RADEON_READ( RADEON_RBBM_STATUS ) - & RADEON_RBBM_FIFOCNT_MASK ); - if ( slots >= entries ) return 0; - DRM_UDELAY( 1 ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + int slots = (RADEON_READ(RADEON_RBBM_STATUS) + & RADEON_RBBM_FIFOCNT_MASK); + if (slots >= entries) + return 0; + DRM_UDELAY(1); } #if RADEON_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - radeon_status( dev_priv ); + DRM_ERROR("failed!\n"); + radeon_status(dev_priv); #endif return DRM_ERR(EBUSY); } -static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv ) +static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) { int i, ret; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - ret = radeon_do_wait_for_fifo( dev_priv, 64 ); - if ( ret ) return ret; + ret = radeon_do_wait_for_fifo(dev_priv, 64); + if (ret) + return ret; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(RADEON_READ( RADEON_RBBM_STATUS ) - & RADEON_RBBM_ACTIVE) ) { - radeon_do_pixcache_flush( dev_priv ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + if (!(RADEON_READ(RADEON_RBBM_STATUS) + & RADEON_RBBM_ACTIVE)) { + radeon_do_pixcache_flush(dev_priv); return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if RADEON_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - radeon_status( dev_priv ); + DRM_ERROR("failed!\n"); + radeon_status(dev_priv); #endif return DRM_ERR(EBUSY); } - /* ================================================================ * CP control, initialization */ /* Load the microcode for the CP */ -static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv ) +static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) { int i; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - radeon_do_wait_for_idle( dev_priv ); + radeon_do_wait_for_idle(dev_priv); - RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 ); + RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); - if (dev_priv->is_r200) - { + if (dev_priv->is_r200) { DRM_INFO("Loading R200 Microcode\n"); - for ( i = 0 ; i < 256 ; i++ ) - { - RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, - R200_cp_microcode[i][1] ); - RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, - R200_cp_microcode[i][0] ); + for (i = 0; i < 256; i++) { + RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, + R200_cp_microcode[i][1]); + RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, + R200_cp_microcode[i][0]); } - } - else - { - for ( i = 0 ; i < 256 ; i++ ) { - RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, - radeon_cp_microcode[i][1] ); - RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, - radeon_cp_microcode[i][0] ); + } else { + for (i = 0; i < 256; i++) { + RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, + radeon_cp_microcode[i][1]); + RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, + radeon_cp_microcode[i][0]); } } } @@ -705,25 +698,25 @@ static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv ) * prior to a wait for idle, as it informs the engine that the command * stream is ending. */ -static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv ) +static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) { - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); #if 0 u32 tmp; - tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31); - RADEON_WRITE( RADEON_CP_RB_WPTR, tmp ); + tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); + RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); #endif } /* Wait for the CP to go idle. */ -int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ) +int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) { RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - BEGIN_RING( 6 ); + BEGIN_RING(6); RADEON_PURGE_CACHE(); RADEON_PURGE_ZCACHE(); @@ -732,23 +725,23 @@ int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ) ADVANCE_RING(); COMMIT_RING(); - return radeon_do_wait_for_idle( dev_priv ); + return radeon_do_wait_for_idle(dev_priv); } /* Start the Command Processor. */ -static void radeon_do_cp_start( drm_radeon_private_t *dev_priv ) +static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) { RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - radeon_do_wait_for_idle( dev_priv ); + radeon_do_wait_for_idle(dev_priv); - RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode ); + RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); dev_priv->cp_running = 1; - BEGIN_RING( 6 ); + BEGIN_RING(6); RADEON_PURGE_CACHE(); RADEON_PURGE_ZCACHE(); @@ -762,14 +755,14 @@ static void radeon_do_cp_start( drm_radeon_private_t *dev_priv ) * commands, so you must wait for the CP command stream to complete * before calling this routine. */ -static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv ) +static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) { u32 cur_read_ptr; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); - RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); - SET_RING_HEAD( dev_priv, cur_read_ptr ); + cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); + RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); + SET_RING_HEAD(dev_priv, cur_read_ptr); dev_priv->ring.tail = cur_read_ptr; } @@ -777,120 +770,116 @@ static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv ) * commands, so you must flush the command stream and wait for the CP * to go idle before calling this routine. */ -static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv ) +static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) { - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS ); + RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); dev_priv->cp_running = 0; } /* Reset the engine. This will stop the CP if it is running. */ -static int radeon_do_engine_reset( drm_device_t *dev ) +static int radeon_do_engine_reset(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; - DRM_DEBUG( "\n" ); - - radeon_do_pixcache_flush( dev_priv ); - - clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX ); - mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL ); - - RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl | - RADEON_FORCEON_MCLKA | - RADEON_FORCEON_MCLKB | - RADEON_FORCEON_YCLKA | - RADEON_FORCEON_YCLKB | - RADEON_FORCEON_MC | - RADEON_FORCEON_AIC ) ); - - rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET ); + DRM_DEBUG("\n"); - RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset | - RADEON_SOFT_RESET_CP | + radeon_do_pixcache_flush(dev_priv); + + clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); + mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); + + RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | + RADEON_FORCEON_MCLKA | + RADEON_FORCEON_MCLKB | + RADEON_FORCEON_YCLKA | + RADEON_FORCEON_YCLKB | + RADEON_FORCEON_MC | + RADEON_FORCEON_AIC)); + + rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); + + RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | + RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB)); + RADEON_READ(RADEON_RBBM_SOFT_RESET); + RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & + ~(RADEON_SOFT_RESET_CP | RADEON_SOFT_RESET_HI | RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_RE | RADEON_SOFT_RESET_PP | RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB ) ); - RADEON_READ( RADEON_RBBM_SOFT_RESET ); - RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset & - ~( RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | - RADEON_SOFT_RESET_SE | - RADEON_SOFT_RESET_RE | - RADEON_SOFT_RESET_PP | - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB ) ) ); - RADEON_READ( RADEON_RBBM_SOFT_RESET ); - - - RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl ); - RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index ); - RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset ); + RADEON_SOFT_RESET_RB))); + RADEON_READ(RADEON_RBBM_SOFT_RESET); + + RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); + RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); + RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); /* Reset the CP ring */ - radeon_do_cp_reset( dev_priv ); + radeon_do_cp_reset(dev_priv); /* The CP is no longer running after an engine reset */ dev_priv->cp_running = 0; /* Reset any pending vertex, indirect buffers */ - radeon_freelist_reset( dev ); + radeon_freelist_reset(dev); return 0; } -static void radeon_cp_init_ring_buffer( drm_device_t *dev, - drm_radeon_private_t *dev_priv ) +static void radeon_cp_init_ring_buffer(drm_device_t * dev, + drm_radeon_private_t * dev_priv) { u32 ring_start, cur_read_ptr; u32 tmp; /* Initialize the memory controller */ - RADEON_WRITE( RADEON_MC_FB_LOCATION, - ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 ) - | ( dev_priv->fb_location >> 16 ) ); + RADEON_WRITE(RADEON_MC_FB_LOCATION, + ((dev_priv->gart_vm_start - 1) & 0xffff0000) + | (dev_priv->fb_location >> 16)); #if __OS_HAS_AGP if (dev_priv->flags & CHIP_IS_AGP) { - RADEON_WRITE( RADEON_MC_AGP_LOCATION, - (((dev_priv->gart_vm_start - 1 + - dev_priv->gart_size) & 0xffff0000) | - (dev_priv->gart_vm_start >> 16)) ); + RADEON_WRITE(RADEON_MC_AGP_LOCATION, + (((dev_priv->gart_vm_start - 1 + + dev_priv->gart_size) & 0xffff0000) | + (dev_priv->gart_vm_start >> 16))); ring_start = (dev_priv->cp_ring->offset - - dev->agp->base - + dev_priv->gart_vm_start); + - dev->agp->base + dev_priv->gart_vm_start); } else #endif ring_start = (dev_priv->cp_ring->offset - - dev->sg->handle - + dev_priv->gart_vm_start); + - dev->sg->handle + dev_priv->gart_vm_start); - RADEON_WRITE( RADEON_CP_RB_BASE, ring_start ); + RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); /* Set the write pointer delay */ - RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); + RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); /* Initialize the ring buffer's read and write pointers */ - cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); - RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); - SET_RING_HEAD( dev_priv, cur_read_ptr ); + cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); + RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); + SET_RING_HEAD(dev_priv, cur_read_ptr); dev_priv->ring.tail = cur_read_ptr; #if __OS_HAS_AGP if (dev_priv->flags & CHIP_IS_AGP) { /* set RADEON_AGP_BASE here instead of relying on X from user space */ - RADEON_WRITE( RADEON_AGP_BASE, (unsigned int)dev->agp->base ); - RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, - dev_priv->ring_rptr->offset - - dev->agp->base - + dev_priv->gart_vm_start); + RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); + RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, + dev_priv->ring_rptr->offset + - dev->agp->base + dev_priv->gart_vm_start); } else #endif { @@ -900,11 +889,10 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev, tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; page_ofs = tmp_ofs >> PAGE_SHIFT; - RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, - entry->busaddr[page_ofs]); - DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", - (unsigned long) entry->busaddr[page_ofs], - entry->handle + tmp_ofs ); + RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); + DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", + (unsigned long)entry->busaddr[page_ofs], + entry->handle + tmp_ofs); } /* Initialize the scratch register pointer. This will cause @@ -914,108 +902,110 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev, * We simply put this behind the ring read pointer, this works * with PCI GART as well as (whatever kind of) AGP GART */ - RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR ) - + RADEON_SCRATCH_REG_OFFSET ); + RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) + + RADEON_SCRATCH_REG_OFFSET); dev_priv->scratch = ((__volatile__ u32 *) dev_priv->ring_rptr->handle + (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); - RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); + RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); /* Writeback doesn't seem to work everywhere, test it first */ - DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); - RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); + DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); + RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); - for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) { - if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef ) + for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { + if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == + 0xdeadbeef) break; - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } - if ( tmp < dev_priv->usec_timeout ) { + if (tmp < dev_priv->usec_timeout) { dev_priv->writeback_works = 1; - DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp ); + DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp); } else { dev_priv->writeback_works = 0; - DRM_DEBUG( "writeback test failed\n" ); + DRM_DEBUG("writeback test failed\n"); } dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; - RADEON_WRITE( RADEON_LAST_FRAME_REG, - dev_priv->sarea_priv->last_frame ); + RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; - RADEON_WRITE( RADEON_LAST_DISPATCH_REG, - dev_priv->sarea_priv->last_dispatch ); + RADEON_WRITE(RADEON_LAST_DISPATCH_REG, + dev_priv->sarea_priv->last_dispatch); dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; - RADEON_WRITE( RADEON_LAST_CLEAR_REG, - dev_priv->sarea_priv->last_clear ); + RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); /* Set ring buffer size */ #ifdef __BIG_ENDIAN - RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT ); + RADEON_WRITE(RADEON_CP_RB_CNTL, + dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT); #else - RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw ); + RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw); #endif - radeon_do_wait_for_idle( dev_priv ); + radeon_do_wait_for_idle(dev_priv); /* Turn on bus mastering */ - tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS; - RADEON_WRITE( RADEON_BUS_CNTL, tmp ); + tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; + RADEON_WRITE(RADEON_BUS_CNTL, tmp); /* Sync everything up */ - RADEON_WRITE( RADEON_ISYNC_CNTL, - (RADEON_ISYNC_ANY2D_IDLE3D | - RADEON_ISYNC_ANY3D_IDLE2D | - RADEON_ISYNC_WAIT_IDLEGUI | - RADEON_ISYNC_CPSCRATCH_IDLEGUI) ); + RADEON_WRITE(RADEON_ISYNC_CNTL, + (RADEON_ISYNC_ANY2D_IDLE3D | + RADEON_ISYNC_ANY3D_IDLE2D | + RADEON_ISYNC_WAIT_IDLEGUI | + RADEON_ISYNC_CPSCRATCH_IDLEGUI)); } /* Enable or disable PCI GART on the chip */ -static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on ) +static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) { - u32 tmp = RADEON_READ( RADEON_AIC_CNTL ); + u32 tmp = RADEON_READ(RADEON_AIC_CNTL); - if ( on ) { - RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN ); + if (on) { + RADEON_WRITE(RADEON_AIC_CNTL, + tmp | RADEON_PCIGART_TRANSLATE_EN); /* set PCI GART page-table base address */ - RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart ); + RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart); /* set address range for PCI address translate */ - RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start ); - RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start - + dev_priv->gart_size - 1); + RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); + RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start + + dev_priv->gart_size - 1); /* Turn off AGP aperture -- is this required for PCI GART? */ - RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ - RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ + RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ + RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ } else { - RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN ); + RADEON_WRITE(RADEON_AIC_CNTL, + tmp & ~RADEON_PCIGART_TRANSLATE_EN); } } -static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) +static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) { drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - if ( (!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg ) { - DRM_ERROR( "PCI GART memory not allocated!\n" ); + if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) { + DRM_ERROR("PCI GART memory not allocated!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev_priv->usec_timeout = init->usec_timeout; - if ( dev_priv->usec_timeout < 1 || - dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) { - DRM_DEBUG( "TIMEOUT problem!\n" ); + if (dev_priv->usec_timeout < 1 || + dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { + DRM_DEBUG("TIMEOUT problem!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } @@ -1028,14 +1018,14 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) * but the ring can be in either AGP or PCI space for the ring * read pointer. */ - if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) && - ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) { - DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode ); + if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && + (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { + DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } - switch ( init->fb_bpp ) { + switch (init->fb_bpp) { case 16: dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; break; @@ -1044,12 +1034,12 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; break; } - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; - switch ( init->depth_bpp ) { + switch (init->depth_bpp) { case 16: dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; break; @@ -1058,8 +1048,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; break; } - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; /* Hardware state for depth clears. Remove this if/when we no * longer clear the depth buffer with a 3D rectangle. Hard-code @@ -1068,16 +1058,15 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) */ dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | (dev_priv->color_fmt << 10) | - (1<<15)); + (1 << 15)); - dev_priv->depth_clear.rb3d_zstencilcntl = - (dev_priv->depth_fmt | - RADEON_Z_TEST_ALWAYS | - RADEON_STENCIL_TEST_ALWAYS | - RADEON_STENCIL_S_FAIL_REPLACE | - RADEON_STENCIL_ZPASS_REPLACE | - RADEON_STENCIL_ZFAIL_REPLACE | - RADEON_Z_WRITE_ENABLE); + dev_priv->depth_clear.rb3d_zstencilcntl = + (dev_priv->depth_fmt | + RADEON_Z_TEST_ALWAYS | + RADEON_STENCIL_TEST_ALWAYS | + RADEON_STENCIL_S_FAIL_REPLACE | + RADEON_STENCIL_ZPASS_REPLACE | + RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | RADEON_BFACE_SOLID | @@ -1099,41 +1088,42 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) dev_priv->ring_rptr_offset = init->ring_rptr_offset; dev_priv->buffers_offset = init->buffers_offset; dev_priv->gart_textures_offset = init->gart_textures_offset; - - if(!dev_priv->sarea) { + + if (!dev_priv->sarea) { DRM_ERROR("could not find sarea!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if(!dev_priv->mmio) { + if (!dev_priv->mmio) { DRM_ERROR("could not find mmio region!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); - if(!dev_priv->cp_ring) { + if (!dev_priv->cp_ring) { DRM_ERROR("could not find cp ring region!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); - if(!dev_priv->ring_rptr) { + if (!dev_priv->ring_rptr) { DRM_ERROR("could not find ring read pointer!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if(!dev->agp_buffer_map) { + if (!dev->agp_buffer_map) { DRM_ERROR("could not find dma buffer region!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } - if ( init->gart_textures_offset ) { - dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset); - if ( !dev_priv->gart_textures ) { + if (init->gart_textures_offset) { + dev_priv->gart_textures = + drm_core_findmap(dev, init->gart_textures_offset); + if (!dev_priv->gart_textures) { DRM_ERROR("could not find GART texture region!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); @@ -1141,17 +1131,17 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) } dev_priv->sarea_priv = - (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); + (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + + init->sarea_priv_offset); #if __OS_HAS_AGP - if ( dev_priv->flags & CHIP_IS_AGP ) { - drm_core_ioremap( dev_priv->cp_ring, dev ); - drm_core_ioremap( dev_priv->ring_rptr, dev ); - drm_core_ioremap( dev->agp_buffer_map, dev ); - if(!dev_priv->cp_ring->handle || - !dev_priv->ring_rptr->handle || - !dev->agp_buffer_map->handle) { + if (dev_priv->flags & CHIP_IS_AGP) { + drm_core_ioremap(dev_priv->cp_ring, dev); + drm_core_ioremap(dev_priv->ring_rptr, dev); + drm_core_ioremap(dev->agp_buffer_map, dev); + if (!dev_priv->cp_ring->handle || + !dev_priv->ring_rptr->handle || + !dev->agp_buffer_map->handle) { DRM_ERROR("could not find ioremap agp regions!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); @@ -1159,129 +1149,126 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) } else #endif { - dev_priv->cp_ring->handle = - (void *)dev_priv->cp_ring->offset; + dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; dev_priv->ring_rptr->handle = - (void *)dev_priv->ring_rptr->offset; - dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; - - DRM_DEBUG( "dev_priv->cp_ring->handle %p\n", - dev_priv->cp_ring->handle ); - DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n", - dev_priv->ring_rptr->handle ); - DRM_DEBUG( "dev->agp_buffer_map->handle %p\n", - dev->agp_buffer_map->handle ); + (void *)dev_priv->ring_rptr->offset; + dev->agp_buffer_map->handle = + (void *)dev->agp_buffer_map->offset; + + DRM_DEBUG("dev_priv->cp_ring->handle %p\n", + dev_priv->cp_ring->handle); + DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", + dev_priv->ring_rptr->handle); + DRM_DEBUG("dev->agp_buffer_map->handle %p\n", + dev->agp_buffer_map->handle); } - dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION ) - & 0xffff ) << 16; + dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION) + & 0xffff) << 16; - dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) | - ( ( dev_priv->front_offset - + dev_priv->fb_location ) >> 10 ) ); + dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | + ((dev_priv->front_offset + + dev_priv->fb_location) >> 10)); - dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) | - ( ( dev_priv->back_offset - + dev_priv->fb_location ) >> 10 ) ); - - dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) | - ( ( dev_priv->depth_offset - + dev_priv->fb_location ) >> 10 ) ); + dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | + ((dev_priv->back_offset + + dev_priv->fb_location) >> 10)); + dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | + ((dev_priv->depth_offset + + dev_priv->fb_location) >> 10)); dev_priv->gart_size = init->gart_size; dev_priv->gart_vm_start = dev_priv->fb_location - + RADEON_READ( RADEON_CONFIG_APER_SIZE ); + + RADEON_READ(RADEON_CONFIG_APER_SIZE); #if __OS_HAS_AGP if (dev_priv->flags & CHIP_IS_AGP) dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset - - dev->agp->base - + dev_priv->gart_vm_start); + - dev->agp->base + + dev_priv->gart_vm_start); else #endif dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset - - dev->sg->handle - + dev_priv->gart_vm_start); - - DRM_DEBUG( "dev_priv->gart_size %d\n", - dev_priv->gart_size ); - DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n", - dev_priv->gart_vm_start ); - DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n", - dev_priv->gart_buffers_offset ); - - dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle; - dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle + - dev->sg->handle + + dev_priv->gart_vm_start); + + DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); + DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); + DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", + dev_priv->gart_buffers_offset); + + dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; + dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle + init->ring_size / sizeof(u32)); dev_priv->ring.size = init->ring_size; - dev_priv->ring.size_l2qw = get_order( init->ring_size / 8 ); + dev_priv->ring.size_l2qw = get_order(init->ring_size / 8); - dev_priv->ring.tail_mask = - (dev_priv->ring.size / sizeof(u32)) - 1; + dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; #if __OS_HAS_AGP if (dev_priv->flags & CHIP_IS_AGP) { /* Turn off PCI GART */ - radeon_set_pcigart( dev_priv, 0 ); + radeon_set_pcigart(dev_priv, 0); } else #endif { - if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart, - &dev_priv->bus_pci_gart)) { - DRM_ERROR( "failed to init PCI GART!\n" ); + if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart, + &dev_priv->bus_pci_gart)) { + DRM_ERROR("failed to init PCI GART!\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(ENOMEM); } /* Turn on PCI GART */ - radeon_set_pcigart( dev_priv, 1 ); + radeon_set_pcigart(dev_priv, 1); } - radeon_cp_load_microcode( dev_priv ); - radeon_cp_init_ring_buffer( dev, dev_priv ); + radeon_cp_load_microcode(dev_priv); + radeon_cp_init_ring_buffer(dev, dev_priv); dev_priv->last_buf = 0; - radeon_do_engine_reset( dev ); + radeon_do_engine_reset(dev); return 0; } -int radeon_do_cleanup_cp( drm_device_t *dev ) +int radeon_do_cleanup_cp(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private * is freed, it's too late. */ - if ( dev->irq_enabled ) drm_irq_uninstall(dev); + if (dev->irq_enabled) + drm_irq_uninstall(dev); #if __OS_HAS_AGP if (dev_priv->flags & CHIP_IS_AGP) { - if ( dev_priv->cp_ring != NULL ) { - drm_core_ioremapfree( dev_priv->cp_ring, dev ); + if (dev_priv->cp_ring != NULL) { + drm_core_ioremapfree(dev_priv->cp_ring, dev); dev_priv->cp_ring = NULL; } - if ( dev_priv->ring_rptr != NULL ) { - drm_core_ioremapfree( dev_priv->ring_rptr, dev ); + if (dev_priv->ring_rptr != NULL) { + drm_core_ioremapfree(dev_priv->ring_rptr, dev); dev_priv->ring_rptr = NULL; } - if ( dev->agp_buffer_map != NULL ) { - drm_core_ioremapfree( dev->agp_buffer_map, dev ); + if (dev->agp_buffer_map != NULL) { + drm_core_ioremapfree(dev->agp_buffer_map, dev); dev->agp_buffer_map = NULL; } } else #endif { - if (!drm_ati_pcigart_cleanup( dev, - dev_priv->phys_pci_gart, - dev_priv->bus_pci_gart )) - DRM_ERROR( "failed to cleanup PCI GART!\n" ); + if (!drm_ati_pcigart_cleanup(dev, + dev_priv->phys_pci_gart, + dev_priv->bus_pci_gart)) + DRM_ERROR("failed to cleanup PCI GART!\n"); } /* only clear to the start of flags */ memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); @@ -1289,20 +1276,20 @@ int radeon_do_cleanup_cp( drm_device_t *dev ) return 0; } -/* This code will reinit the Radeon CP hardware after a resume from disc. - * AFAIK, it would be very difficult to pickle the state at suspend time, so +/* This code will reinit the Radeon CP hardware after a resume from disc. + * AFAIK, it would be very difficult to pickle the state at suspend time, so * here we make sure that all Radeon hardware initialisation is re-done without * affecting running applications. * * Charl P. Botha */ -static int radeon_do_resume_cp( drm_device_t *dev ) +static int radeon_do_resume_cp(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - if ( !dev_priv ) { - DRM_ERROR( "Called with no initialization\n" ); - return DRM_ERR( EINVAL ); + if (!dev_priv) { + DRM_ERROR("Called with no initialization\n"); + return DRM_ERR(EINVAL); } DRM_DEBUG("Starting radeon_do_resume_cp()\n"); @@ -1310,64 +1297,64 @@ static int radeon_do_resume_cp( drm_device_t *dev ) #if __OS_HAS_AGP if (dev_priv->flags & CHIP_IS_AGP) { /* Turn off PCI GART */ - radeon_set_pcigart( dev_priv, 0 ); + radeon_set_pcigart(dev_priv, 0); } else #endif { /* Turn on PCI GART */ - radeon_set_pcigart( dev_priv, 1 ); + radeon_set_pcigart(dev_priv, 1); } - radeon_cp_load_microcode( dev_priv ); - radeon_cp_init_ring_buffer( dev, dev_priv ); + radeon_cp_load_microcode(dev_priv); + radeon_cp_init_ring_buffer(dev, dev_priv); - radeon_do_engine_reset( dev ); + radeon_do_engine_reset(dev); DRM_DEBUG("radeon_do_resume_cp() complete\n"); return 0; } - -int radeon_cp_init( DRM_IOCTL_ARGS ) +int radeon_cp_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_init_t init; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) ); + DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data, + sizeof(init)); - switch ( init.func ) { + switch (init.func) { case RADEON_INIT_CP: case RADEON_INIT_R200_CP: - return radeon_do_init_cp( dev, &init ); + return radeon_do_init_cp(dev, &init); case RADEON_CLEANUP_CP: - return radeon_do_cleanup_cp( dev ); + return radeon_do_cleanup_cp(dev); } return DRM_ERR(EINVAL); } -int radeon_cp_start( DRM_IOCTL_ARGS ) +int radeon_cp_start(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( dev_priv->cp_running ) { - DRM_DEBUG( "%s while CP running\n", __FUNCTION__ ); + if (dev_priv->cp_running) { + DRM_DEBUG("%s while CP running\n", __FUNCTION__); return 0; } - if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) { - DRM_DEBUG( "%s called with bogus CP mode (%d)\n", - __FUNCTION__, dev_priv->cp_mode ); + if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { + DRM_DEBUG("%s called with bogus CP mode (%d)\n", + __FUNCTION__, dev_priv->cp_mode); return 0; } - radeon_do_cp_start( dev_priv ); + radeon_do_cp_start(dev_priv); return 0; } @@ -1375,17 +1362,18 @@ int radeon_cp_start( DRM_IOCTL_ARGS ) /* Stop the CP. The engine must have been idled before calling this * routine. */ -int radeon_cp_stop( DRM_IOCTL_ARGS ) +int radeon_cp_stop(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_cp_stop_t stop; int ret; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) ); + DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data, + sizeof(stop)); if (!dev_priv->cp_running) return 0; @@ -1393,32 +1381,32 @@ int radeon_cp_stop( DRM_IOCTL_ARGS ) /* Flush any pending CP commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. */ - if ( stop.flush ) { - radeon_do_cp_flush( dev_priv ); + if (stop.flush) { + radeon_do_cp_flush(dev_priv); } /* If we fail to make the engine go idle, we return an error * code so that the DRM ioctl wrapper can try again. */ - if ( stop.idle ) { - ret = radeon_do_cp_idle( dev_priv ); - if ( ret ) return ret; + if (stop.idle) { + ret = radeon_do_cp_idle(dev_priv); + if (ret) + return ret; } /* Finally, we can turn off the CP. If the engine isn't idle, * we will get some dropped triangles as they won't be fully * rendered before the CP is shut down. */ - radeon_do_cp_stop( dev_priv ); + radeon_do_cp_stop(dev_priv); /* Reset the engine */ - radeon_do_engine_reset( dev ); + radeon_do_engine_reset(dev); return 0; } - -void radeon_do_release( drm_device_t *dev ) +void radeon_do_release(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; int ret; @@ -1427,7 +1415,7 @@ void radeon_do_release( drm_device_t *dev ) if (dev_priv->cp_running) { /* Stop the cp */ - while ((ret = radeon_do_cp_idle( dev_priv )) != 0) { + while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { DRM_DEBUG("radeon_do_cp_idle %d\n", ret); #ifdef __linux__ schedule(); @@ -1435,39 +1423,39 @@ void radeon_do_release( drm_device_t *dev ) tsleep(&ret, PZERO, "rdnrel", 1); #endif } - radeon_do_cp_stop( dev_priv ); - radeon_do_engine_reset( dev ); + radeon_do_cp_stop(dev_priv); + radeon_do_engine_reset(dev); } /* Disable *all* interrupts */ - if (dev_priv->mmio) /* remove this after permanent addmaps */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); + if (dev_priv->mmio) /* remove this after permanent addmaps */ + RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); /* Free memory heap structures */ - radeon_mem_takedown( &(dev_priv->gart_heap) ); - radeon_mem_takedown( &(dev_priv->fb_heap) ); + radeon_mem_takedown(&(dev_priv->gart_heap)); + radeon_mem_takedown(&(dev_priv->fb_heap)); /* deallocate kernel resources */ - radeon_do_cleanup_cp( dev ); + radeon_do_cleanup_cp(dev); } } /* Just reset the CP ring. Called as part of an X Server engine reset. */ -int radeon_cp_reset( DRM_IOCTL_ARGS ) +int radeon_cp_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_DEBUG("%s called before init done\n", __FUNCTION__); return DRM_ERR(EINVAL); } - radeon_do_cp_reset( dev_priv ); + radeon_do_cp_reset(dev_priv); /* The CP is no longer running after an engine reset */ dev_priv->cp_running = 0; @@ -1475,50 +1463,47 @@ int radeon_cp_reset( DRM_IOCTL_ARGS ) return 0; } -int radeon_cp_idle( DRM_IOCTL_ARGS ) +int radeon_cp_idle(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - return radeon_do_cp_idle( dev_priv ); + return radeon_do_cp_idle(dev_priv); } /* Added by Charl P. Botha to call radeon_do_resume_cp(). */ -int radeon_cp_resume( DRM_IOCTL_ARGS ) +int radeon_cp_resume(DRM_IOCTL_ARGS) { DRM_DEVICE; return radeon_do_resume_cp(dev); } - -int radeon_engine_reset( DRM_IOCTL_ARGS ) +int radeon_engine_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - return radeon_do_engine_reset( dev ); + return radeon_do_engine_reset(dev); } - /* ================================================================ * Fullscreen mode */ /* KW: Deprecated to say the least: */ -int radeon_fullscreen( DRM_IOCTL_ARGS ) +int radeon_fullscreen(DRM_IOCTL_ARGS) { return 0; } - /* ================================================================ * Freelist management */ @@ -1527,20 +1512,20 @@ int radeon_fullscreen( DRM_IOCTL_ARGS ) * bufs until freelist code is used. Note this hides a problem with * the scratch register * (used to keep track of last buffer * completed) being written to before * the last buffer has actually - * completed rendering. + * completed rendering. * * KW: It's also a good way to find free buffers quickly. * * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't * sleep. However, bugs in older versions of radeon_accel.c mean that * we essentially have to do this, else old clients will break. - * + * * However, it does leave open a potential deadlock where all the * buffers are held by other clients, which can't release them because - * they can't get the lock. + * they can't get the lock. */ -drm_buf_t *radeon_freelist_get( drm_device_t *dev ) +drm_buf_t *radeon_freelist_get(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1549,19 +1534,19 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev ) int i, t; int start; - if ( ++dev_priv->last_buf >= dma->buf_count ) + if (++dev_priv->last_buf >= dma->buf_count) dev_priv->last_buf = 0; start = dev_priv->last_buf; - for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { - u32 done_age = GET_SCRATCH( 1 ); - DRM_DEBUG("done_age = %d\n",done_age); - for ( i = start ; i < dma->buf_count ; i++ ) { + for (t = 0; t < dev_priv->usec_timeout; t++) { + u32 done_age = GET_SCRATCH(1); + DRM_DEBUG("done_age = %d\n", done_age); + for (i = start; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if ( buf->filp == 0 || (buf->pending && - buf_priv->age <= done_age) ) { + if (buf->filp == 0 || (buf->pending && + buf_priv->age <= done_age)) { dev_priv->stats.requested_bufs++; buf->pending = 0; return buf; @@ -1570,16 +1555,17 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev ) } if (t) { - DRM_UDELAY( 1 ); + DRM_UDELAY(1); dev_priv->stats.freelist_loops++; } } - DRM_DEBUG( "returning NULL!\n" ); + DRM_DEBUG("returning NULL!\n"); return NULL; } + #if 0 -drm_buf_t *radeon_freelist_get( drm_device_t *dev ) +drm_buf_t *radeon_freelist_get(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1589,18 +1575,18 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev ) int start; u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); - if ( ++dev_priv->last_buf >= dma->buf_count ) + if (++dev_priv->last_buf >= dma->buf_count) dev_priv->last_buf = 0; start = dev_priv->last_buf; dev_priv->stats.freelist_loops++; - - for ( t = 0 ; t < 2 ; t++ ) { - for ( i = start ; i < dma->buf_count ; i++ ) { + + for (t = 0; t < 2; t++) { + for (i = start; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if ( buf->filp == 0 || (buf->pending && - buf_priv->age <= done_age) ) { + if (buf->filp == 0 || (buf->pending && + buf_priv->age <= done_age)) { dev_priv->stats.requested_bufs++; buf->pending = 0; return buf; @@ -1613,73 +1599,74 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev ) } #endif -void radeon_freelist_reset( drm_device_t *dev ) +void radeon_freelist_reset(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; int i; dev_priv->last_buf = 0; - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[i]; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; buf_priv->age = 0; } } - /* ================================================================ * CP command submission */ -int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ) +int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) { drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i; - u32 last_head = GET_RING_HEAD( dev_priv ); + u32 last_head = GET_RING_HEAD(dev_priv); - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - u32 head = GET_RING_HEAD( dev_priv ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + u32 head = GET_RING_HEAD(dev_priv); ring->space = (head - ring->tail) * sizeof(u32); - if ( ring->space <= 0 ) + if (ring->space <= 0) ring->space += ring->size; - if ( ring->space > n ) + if (ring->space > n) return 0; - + dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; if (head != last_head) i = 0; last_head = head; - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } /* FIXME: This return value is ignored in the BEGIN_RING macro! */ #if RADEON_FIFO_DEBUG - radeon_status( dev_priv ); - DRM_ERROR( "failed!\n" ); + radeon_status(dev_priv); + DRM_ERROR("failed!\n"); #endif return DRM_ERR(EBUSY); } -static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) +static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev, + drm_dma_t * d) { int i; drm_buf_t *buf; - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = radeon_freelist_get( dev ); - if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */ + for (i = d->granted_count; i < d->request_count; i++) { + buf = radeon_freelist_get(dev); + if (!buf) + return DRM_ERR(EBUSY); /* NOTE: broken client */ buf->filp = filp; - if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, - sizeof(buf->idx) ) ) + if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, + sizeof(buf->idx))) return DRM_ERR(EFAULT); - if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, - sizeof(buf->total) ) ) + if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, + sizeof(buf->total))) return DRM_ERR(EFAULT); d->granted_count++; @@ -1687,7 +1674,7 @@ static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d return 0; } -int radeon_cp_buffers( DRM_IOCTL_ARGS ) +int radeon_cp_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; @@ -1695,95 +1682,101 @@ int radeon_cp_buffers( DRM_IOCTL_ARGS ) drm_dma_t __user *argp = (void __user *)data; drm_dma_t d; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); + DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); /* Please don't send us buffers. */ - if ( d.send_count != 0 ) { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count ); + if (d.send_count != 0) { + DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", + DRM_CURRENTPID, d.send_count); return DRM_ERR(EINVAL); } /* We'll send you buffers. */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count ); + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", + DRM_CURRENTPID, d.request_count, dma->buf_count); return DRM_ERR(EINVAL); } d.granted_count = 0; - if ( d.request_count ) { - ret = radeon_cp_get_buffers( filp, dev, &d ); + if (d.request_count) { + ret = radeon_cp_get_buffers(filp, dev, &d); } - DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); + DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); return ret; } /* Always create a map record for MMIO and FB memory, done from DRIVER_POSTINIT */ -int radeon_preinit( struct drm_device *dev, unsigned long flags ) +int radeon_preinit(struct drm_device *dev, unsigned long flags) { u32 save, temp; drm_radeon_private_t *dev_priv; int ret = 0; - dev_priv = drm_alloc( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER ); - if ( dev_priv == NULL ) + dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); + if (dev_priv == NULL) return DRM_ERR(ENOMEM); - memset( dev_priv, 0, sizeof(drm_radeon_private_t) ); + memset(dev_priv, 0, sizeof(drm_radeon_private_t)); dev->dev_private = (void *)dev_priv; dev_priv->flags = flags; /* registers */ - if( (ret = drm_initmap( dev, pci_resource_start( dev->pdev, 2 ), - pci_resource_len( dev->pdev, 2 ), _DRM_REGISTERS, 0 ))) + if ((ret = drm_initmap(dev, pci_resource_start(dev->pdev, 2), + pci_resource_len(dev->pdev, 2), _DRM_REGISTERS, + 0))) return ret; /* framebuffer */ - if( (ret = drm_initmap( dev, pci_resource_start( dev->pdev, 0 ), - pci_resource_len( dev->pdev, 0 ), _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING ))) + if ((ret = drm_initmap(dev, pci_resource_start(dev->pdev, 0), + pci_resource_len(dev->pdev, 0), + _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING))) return ret; /* There are signatures in BIOS and PCI-SSID for a PCI card, but they are not very reliable. - Following detection method works for all cards tested so far. - Note, checking AGP_ENABLE bit after drmAgpEnable call can also give the correct result. - However, calling drmAgpEnable on a PCI card can cause some strange lockup when the server - restarts next time. - */ + Following detection method works for all cards tested so far. + Note, checking AGP_ENABLE bit after drmAgpEnable call can also give the correct result. + However, calling drmAgpEnable on a PCI card can cause some strange lockup when the server + restarts next time. + */ pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &save); - pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, save | RADEON_AGP_ENABLE); + pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, + save | RADEON_AGP_ENABLE); pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &temp); if (temp & RADEON_AGP_ENABLE) dev_priv->flags |= CHIP_IS_AGP; - DRM_DEBUG("%s card detected\n", ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI")); + DRM_DEBUG("%s card detected\n", + ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI")); pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, save); - + /* Check if we need a reset */ - if (!(dev_priv->mmio = drm_core_findmap(dev , pci_resource_start( dev->pdev, 2 )))) + if (! + (dev_priv->mmio = + drm_core_findmap(dev, pci_resource_start(dev->pdev, 2)))) return DRM_ERR(ENOMEM); - + #if defined(__linux__) ret = radeon_create_i2c_busses(dev); #endif - return ret; + return ret; } -int radeon_postcleanup( struct drm_device *dev ) +int radeon_postcleanup(struct drm_device *dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - + DRM_DEBUG("\n"); #if defined(__linux__) radeon_delete_i2c_busses(dev); #endif - drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER ); + drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); dev->dev_private = NULL; return 0; diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h index 207a0c00..4b161cf1 100644 --- a/shared-core/radeon_drm.h +++ b/shared-core/radeon_drm.h @@ -57,78 +57,77 @@ #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 -#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ +#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ #define RADEON_REQUIRE_QUIESCENCE 0x00010000 -#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ +#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ #define RADEON_UPLOAD_ALL 0x003effff #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff - /* New style per-packet identifiers for use in cmd_buffer ioctl with * the RADEON_EMIT_PACKET command. Comments relate new packets to old * state bits and the packet size: */ -#define RADEON_EMIT_PP_MISC 0 /* context/7 */ -#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ -#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ -#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ -#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ -#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ -#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ -#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ -#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ -#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ -#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ -#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ -#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ -#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ -#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ -#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ -#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ -#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ -#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ -#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ -#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ -#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ -#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ -#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ -#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ -#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ -#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ -#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ -#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ -#define R200_EMIT_VAP_CTL 32 /* vap/1 */ -#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ -#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ -#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ -#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ -#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ -#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ -#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ -#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ -#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ -#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ -#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ -#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ -#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ -#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ -#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ -#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ -#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ -#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ -#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ -#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ -#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ -#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ -#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ -#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ -#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ -#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ +#define RADEON_EMIT_PP_MISC 0 /* context/7 */ +#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ +#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ +#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ +#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ +#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ +#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ +#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ +#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ +#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ +#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ +#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ +#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ +#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ +#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ +#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ +#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ +#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ +#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ +#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ +#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ +#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ +#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ +#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ +#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ +#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ +#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ +#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ +#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ +#define R200_EMIT_VAP_CTL 32 /* vap/1 */ +#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ +#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ +#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ +#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ +#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ +#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ +#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ +#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ +#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ +#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ +#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ +#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ +#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ +#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ +#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ +#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ +#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ +#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ +#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ +#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ +#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ +#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ +#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ +#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ +#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ +#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ +#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ +#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ #define R200_EMIT_PP_CUBIC_FACES_0 61 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 #define R200_EMIT_PP_CUBIC_FACES_1 63 @@ -147,48 +146,45 @@ #define R200_EMIT_RB3D_BLENDCOLOR 76 #define RADEON_MAX_STATE_PACKETS 77 - /* Commands understood by cmd_buffer ioctl. More can be added but * obviously these can't be removed or changed: */ -#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ -#define RADEON_CMD_SCALARS 2 /* emit scalar data */ -#define RADEON_CMD_VECTORS 3 /* emit vector data */ -#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ -#define RADEON_CMD_PACKET3 5 /* emit hw packet */ -#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ -#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ -#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: - * doesn't make the cpu wait, just - * the graphics hardware */ - +#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ +#define RADEON_CMD_SCALARS 2 /* emit scalar data */ +#define RADEON_CMD_VECTORS 3 /* emit vector data */ +#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ +#define RADEON_CMD_PACKET3 5 /* emit hw packet */ +#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ +#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ +#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: + * doesn't make the cpu wait, just + * the graphics hardware */ typedef union { int i; - struct { + struct { unsigned char cmd_type, pad0, pad1, pad2; } header; - struct { + struct { unsigned char cmd_type, packet_id, pad0, pad1; } packet; - struct { - unsigned char cmd_type, offset, stride, count; + struct { + unsigned char cmd_type, offset, stride, count; } scalars; - struct { - unsigned char cmd_type, offset, stride, count; + struct { + unsigned char cmd_type, offset, stride, count; } vectors; - struct { - unsigned char cmd_type, buf_idx, pad0, pad1; + struct { + unsigned char cmd_type, buf_idx, pad0, pad1; } dma; - struct { - unsigned char cmd_type, flags, pad0, pad1; + struct { + unsigned char cmd_type, flags, pad0, pad1; } wait; } drm_radeon_cmd_header_t; #define RADEON_WAIT_2D 0x1 #define RADEON_WAIT_3D 0x2 - #define RADEON_FRONT 0x1 #define RADEON_BACK 0x2 #define RADEON_DEPTH 0x4 @@ -234,7 +230,7 @@ typedef union { #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) -#endif /* __RADEON_SAREA_DEFINES__ */ +#endif /* __RADEON_SAREA_DEFINES__ */ typedef struct { unsigned int red; @@ -245,7 +241,7 @@ typedef struct { typedef struct { /* Context state */ - unsigned int pp_misc; /* 0x1c14 */ + unsigned int pp_misc; /* 0x1c14 */ unsigned int pp_fog_color; unsigned int re_solid_color; unsigned int rb3d_blendcntl; @@ -253,7 +249,7 @@ typedef struct { unsigned int rb3d_depthpitch; unsigned int rb3d_zstencilcntl; - unsigned int pp_cntl; /* 0x1c38 */ + unsigned int pp_cntl; /* 0x1c38 */ unsigned int rb3d_cntl; unsigned int rb3d_coloroffset; unsigned int re_width_height; @@ -261,27 +257,27 @@ typedef struct { unsigned int se_cntl; /* Vertex format state */ - unsigned int se_coord_fmt; /* 0x1c50 */ + unsigned int se_coord_fmt; /* 0x1c50 */ /* Line state */ - unsigned int re_line_pattern; /* 0x1cd0 */ + unsigned int re_line_pattern; /* 0x1cd0 */ unsigned int re_line_state; - unsigned int se_line_width; /* 0x1db8 */ + unsigned int se_line_width; /* 0x1db8 */ /* Bumpmap state */ - unsigned int pp_lum_matrix; /* 0x1d00 */ + unsigned int pp_lum_matrix; /* 0x1d00 */ - unsigned int pp_rot_matrix_0; /* 0x1d58 */ + unsigned int pp_rot_matrix_0; /* 0x1d58 */ unsigned int pp_rot_matrix_1; /* Mask state */ - unsigned int rb3d_stencilrefmask; /* 0x1d7c */ + unsigned int rb3d_stencilrefmask; /* 0x1d7c */ unsigned int rb3d_ropcntl; unsigned int rb3d_planemask; /* Viewport state */ - unsigned int se_vport_xscale; /* 0x1d98 */ + unsigned int se_vport_xscale; /* 0x1d98 */ unsigned int se_vport_xoffset; unsigned int se_vport_yscale; unsigned int se_vport_yoffset; @@ -289,20 +285,19 @@ typedef struct { unsigned int se_vport_zoffset; /* Setup state */ - unsigned int se_cntl_status; /* 0x2140 */ + unsigned int se_cntl_status; /* 0x2140 */ /* Misc state */ - unsigned int re_top_left; /* 0x26c0 */ + unsigned int re_top_left; /* 0x26c0 */ unsigned int re_misc; } drm_radeon_context_regs_t; typedef struct { /* Zbias state */ - unsigned int se_zbias_factor; /* 0x1dac */ + unsigned int se_zbias_factor; /* 0x1dac */ unsigned int se_zbias_constant; } drm_radeon_context2_regs_t; - /* Setup registers for each texture unit */ typedef struct { @@ -320,11 +315,10 @@ typedef struct { unsigned int finish; unsigned int prim:8; unsigned int stateidx:8; - unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ - unsigned int vc_format; /* vertex format */ + unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ + unsigned int vc_format; /* vertex format */ } drm_radeon_prim_t; - typedef struct { drm_radeon_context_regs_t context; drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; @@ -332,7 +326,6 @@ typedef struct { unsigned int dirty; } drm_radeon_state_t; - typedef struct { /* The channel for communication of state information to the * kernel on firing a vertex buffer with either of the @@ -355,15 +348,15 @@ typedef struct { unsigned int last_dispatch; unsigned int last_clear; - drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; + drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + + 1]; unsigned int tex_age[RADEON_NR_TEX_HEAPS]; int ctx_owner; - int pfState; /* number of 3d windows (0,1,2ormore) */ - int pfCurrentPage; /* which buffer is being displayed? */ - int crtc2_base; /* CRTC2 frame offset */ + int pfState; /* number of 3d windows (0,1,2ormore) */ + int pfCurrentPage; /* which buffer is being displayed? */ + int crtc2_base; /* CRTC2 frame offset */ } drm_radeon_sarea_t; - /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmRadeon.h) * @@ -373,15 +366,15 @@ typedef struct { /* Radeon specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ -#define DRM_RADEON_CP_INIT 0x00 -#define DRM_RADEON_CP_START 0x01 +#define DRM_RADEON_CP_INIT 0x00 +#define DRM_RADEON_CP_START 0x01 #define DRM_RADEON_CP_STOP 0x02 #define DRM_RADEON_CP_RESET 0x03 #define DRM_RADEON_CP_IDLE 0x04 -#define DRM_RADEON_RESET 0x05 +#define DRM_RADEON_RESET 0x05 #define DRM_RADEON_FULLSCREEN 0x06 -#define DRM_RADEON_SWAP 0x07 -#define DRM_RADEON_CLEAR 0x08 +#define DRM_RADEON_SWAP 0x07 +#define DRM_RADEON_CLEAR 0x08 #define DRM_RADEON_VERTEX 0x09 #define DRM_RADEON_INDICES 0x0A #define DRM_RADEON_NOT_USED @@ -428,12 +421,12 @@ typedef struct { typedef struct drm_radeon_init { enum { - RADEON_INIT_CP = 0x01, + RADEON_INIT_CP = 0x01, RADEON_CLEANUP_CP = 0x02, RADEON_INIT_R200_CP = 0x03 } func; unsigned long sarea_priv_offset; - int is_pci; /* not used, driver asks hardware */ + int is_pci; /* not used, driver asks hardware */ int cp_mode; int gart_size; int ring_size; @@ -460,7 +453,7 @@ typedef struct drm_radeon_cp_stop { typedef struct drm_radeon_fullscreen { enum { - RADEON_INIT_FULLSCREEN = 0x01, + RADEON_INIT_FULLSCREEN = 0x01, RADEON_CLEANUP_FULLSCREEN = 0x02 } func; } drm_radeon_fullscreen_t; @@ -481,15 +474,15 @@ typedef struct drm_radeon_clear { unsigned int clear_color; unsigned int clear_depth; unsigned int color_mask; - unsigned int depth_mask; /* misnamed field: should be stencil */ + unsigned int depth_mask; /* misnamed field: should be stencil */ drm_radeon_clear_rect_t __user *depth_boxes; } drm_radeon_clear_t; typedef struct drm_radeon_vertex { int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ + int idx; /* Index of vertex buffer */ + int count; /* Number of vertices in buffer */ + int discard; /* Client finished with buffer? */ } drm_radeon_vertex_t; typedef struct drm_radeon_indices { @@ -497,7 +490,7 @@ typedef struct drm_radeon_indices { int idx; int start; int end; - int discard; /* Client finished with buffer? */ + int discard; /* Client finished with buffer? */ } drm_radeon_indices_t; /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices @@ -505,8 +498,8 @@ typedef struct drm_radeon_indices { * - supports driver change to emit native primitives */ typedef struct drm_radeon_vertex2 { - int idx; /* Index of vertex buffer */ - int discard; /* Client finished with buffer? */ + int idx; /* Index of vertex buffer */ + int discard; /* Client finished with buffer? */ int nr_states; drm_radeon_state_t __user *state; int nr_prims; @@ -514,10 +507,10 @@ typedef struct drm_radeon_vertex2 { } drm_radeon_vertex2_t; /* v1.3 - obsoletes drm_radeon_vertex2 - * - allows arbitarily large cliprect list + * - allows arbitarily large cliprect list * - allows updating of tcl packet, vector and scalar state * - allows memory-efficient description of state updates - * - allows state to be emitted without a primitive + * - allows state to be emitted without a primitive * (for clears, ctx switches) * - allows more than one dma buffer to be referenced per ioctl * - supports tcl driver @@ -531,7 +524,7 @@ typedef struct drm_radeon_cmd_buffer { } drm_radeon_cmd_buffer_t; typedef struct drm_radeon_tex_image { - unsigned int x, y; /* Blit coordinates */ + unsigned int x, y; /* Blit coordinates */ unsigned int width, height; const void __user *data; } drm_radeon_tex_image_t; @@ -540,7 +533,7 @@ typedef struct drm_radeon_texture { unsigned int offset; int pitch; int format; - int width; /* Texture image coordinates */ + int width; /* Texture image coordinates */ int height; drm_radeon_tex_image_t __user *image; } drm_radeon_texture_t; @@ -556,19 +549,18 @@ typedef struct drm_radeon_indirect { int discard; } drm_radeon_indirect_t; - /* 1.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. + * client any other way. */ -#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ +#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ #define RADEON_PARAM_LAST_FRAME 2 #define RADEON_PARAM_LAST_DISPATCH 3 #define RADEON_PARAM_LAST_CLEAR 4 /* Added with DRM version 1.6. */ #define RADEON_PARAM_IRQ_NR 5 -#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ +#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ /* Added with DRM version 1.8. */ -#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ +#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ #define RADEON_PARAM_STATUS_HANDLE 8 #define RADEON_PARAM_SAREA_HANDLE 9 #define RADEON_PARAM_GART_TEX_HANDLE 10 @@ -599,10 +591,9 @@ typedef struct drm_radeon_mem_free { typedef struct drm_radeon_mem_init_heap { int region; int size; - int start; + int start; } drm_radeon_mem_init_heap_t; - /* 1.6: Userspace can request & wait on irq's: */ typedef struct drm_radeon_irq_emit { @@ -613,17 +604,15 @@ typedef struct drm_radeon_irq_wait { int irq_seq; } drm_radeon_irq_wait_t; - /* 1.10: Clients tell the DRM where they think the framebuffer is located in * the card's address space, via a new generic ioctl to set parameters */ typedef struct drm_radeon_setparam { unsigned int param; - int64_t value; + int64_t value; } drm_radeon_setparam_t; -#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ - +#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ #endif diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 75c02e7a..6d96cf59 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -44,7 +44,6 @@ #define DRIVER_MINOR 11 #define DRIVER_PATCHLEVEL 0 - enum radeon_family { CHIP_R100, CHIP_RS100, @@ -69,22 +68,22 @@ enum radeon_family { * Chip flags */ enum radeon_chip_flags { - CHIP_FAMILY_MASK = 0x0000ffffUL, - CHIP_FLAGS_MASK = 0xffff0000UL, - CHIP_IS_MOBILITY = 0x00010000UL, - CHIP_IS_IGP = 0x00020000UL, - CHIP_SINGLE_CRTC = 0x00040000UL, - CHIP_IS_AGP = 0x00080000UL, + CHIP_FAMILY_MASK = 0x0000ffffUL, + CHIP_FLAGS_MASK = 0xffff0000UL, + CHIP_IS_MOBILITY = 0x00010000UL, + CHIP_IS_IGP = 0x00020000UL, + CHIP_SINGLE_CRTC = 0x00040000UL, + CHIP_IS_AGP = 0x00080000UL, }; #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) typedef struct drm_radeon_freelist { - unsigned int age; - drm_buf_t *buf; - struct drm_radeon_freelist *next; - struct drm_radeon_freelist *prev; + unsigned int age; + drm_buf_t *buf; + struct drm_radeon_freelist *next; + struct drm_radeon_freelist *prev; } drm_radeon_freelist_t; typedef struct drm_radeon_ring_buffer { @@ -132,8 +131,8 @@ typedef struct drm_radeon_private { int cp_mode; int cp_running; - drm_radeon_freelist_t *head; - drm_radeon_freelist_t *tail; + drm_radeon_freelist_t *head; + drm_radeon_freelist_t *tail; int last_buf; volatile u32 *scratch; int writeback_works; @@ -175,7 +174,7 @@ typedef struct drm_radeon_private { u32 depth_pitch_offset; drm_radeon_depth_clear_t depth_clear; - + unsigned long fb_offset; unsigned long mmio_offset; unsigned long ring_offset; @@ -193,13 +192,13 @@ typedef struct drm_radeon_private { struct mem_block *fb_heap; /* SW interrupt */ - wait_queue_head_t swi_queue; - atomic_t swi_emitted; + wait_queue_head_t swi_queue; + atomic_t swi_emitted; /* starting from here on, data is preserved accross an open */ uint32_t flags; /* see radeon_chip_flags */ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) - struct radeon_i2c_chan i2c[4]; + struct radeon_i2c_chan i2c[4]; #endif } drm_radeon_private_t; @@ -208,63 +207,66 @@ typedef struct drm_radeon_buf_priv { } drm_radeon_buf_priv_t; /* radeon_cp.c */ -extern int radeon_cp_init( DRM_IOCTL_ARGS ); -extern int radeon_cp_start( DRM_IOCTL_ARGS ); -extern int radeon_cp_stop( DRM_IOCTL_ARGS ); -extern int radeon_cp_reset( DRM_IOCTL_ARGS ); -extern int radeon_cp_idle( DRM_IOCTL_ARGS ); -extern int radeon_cp_resume( DRM_IOCTL_ARGS ); -extern int radeon_engine_reset( DRM_IOCTL_ARGS ); -extern int radeon_fullscreen( DRM_IOCTL_ARGS ); -extern int radeon_cp_buffers( DRM_IOCTL_ARGS ); +extern int radeon_cp_init(DRM_IOCTL_ARGS); +extern int radeon_cp_start(DRM_IOCTL_ARGS); +extern int radeon_cp_stop(DRM_IOCTL_ARGS); +extern int radeon_cp_reset(DRM_IOCTL_ARGS); +extern int radeon_cp_idle(DRM_IOCTL_ARGS); +extern int radeon_cp_resume(DRM_IOCTL_ARGS); +extern int radeon_engine_reset(DRM_IOCTL_ARGS); +extern int radeon_fullscreen(DRM_IOCTL_ARGS); +extern int radeon_cp_buffers(DRM_IOCTL_ARGS); -extern void radeon_freelist_reset( drm_device_t *dev ); -extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); +extern void radeon_freelist_reset(drm_device_t * dev); +extern drm_buf_t *radeon_freelist_get(drm_device_t * dev); -extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); +extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); -extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); -extern int radeon_do_cleanup_cp( drm_device_t *dev ); -extern int radeon_do_cleanup_pageflip( drm_device_t *dev ); +extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); +extern int radeon_do_cleanup_cp(drm_device_t * dev); +extern int radeon_do_cleanup_pageflip(drm_device_t * dev); /* radeon_state.c */ -extern int radeon_cp_clear( DRM_IOCTL_ARGS ); -extern int radeon_cp_swap( DRM_IOCTL_ARGS ); -extern int radeon_cp_vertex( DRM_IOCTL_ARGS ); -extern int radeon_cp_indices( DRM_IOCTL_ARGS ); -extern int radeon_cp_texture( DRM_IOCTL_ARGS ); -extern int radeon_cp_stipple( DRM_IOCTL_ARGS ); -extern int radeon_cp_indirect( DRM_IOCTL_ARGS ); -extern int radeon_cp_vertex2( DRM_IOCTL_ARGS ); -extern int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ); -extern int radeon_cp_getparam( DRM_IOCTL_ARGS ); -extern int radeon_cp_setparam( DRM_IOCTL_ARGS ); -extern int radeon_cp_flip( DRM_IOCTL_ARGS ); - -extern int radeon_mem_alloc( DRM_IOCTL_ARGS ); -extern int radeon_mem_free( DRM_IOCTL_ARGS ); -extern int radeon_mem_init_heap( DRM_IOCTL_ARGS ); -extern void radeon_mem_takedown( struct mem_block **heap ); -extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap ); +extern int radeon_cp_clear(DRM_IOCTL_ARGS); +extern int radeon_cp_swap(DRM_IOCTL_ARGS); +extern int radeon_cp_vertex(DRM_IOCTL_ARGS); +extern int radeon_cp_indices(DRM_IOCTL_ARGS); +extern int radeon_cp_texture(DRM_IOCTL_ARGS); +extern int radeon_cp_stipple(DRM_IOCTL_ARGS); +extern int radeon_cp_indirect(DRM_IOCTL_ARGS); +extern int radeon_cp_vertex2(DRM_IOCTL_ARGS); +extern int radeon_cp_cmdbuf(DRM_IOCTL_ARGS); +extern int radeon_cp_getparam(DRM_IOCTL_ARGS); +extern int radeon_cp_setparam(DRM_IOCTL_ARGS); +extern int radeon_cp_flip(DRM_IOCTL_ARGS); + +extern int radeon_mem_alloc(DRM_IOCTL_ARGS); +extern int radeon_mem_free(DRM_IOCTL_ARGS); +extern int radeon_mem_init_heap(DRM_IOCTL_ARGS); +extern void radeon_mem_takedown(struct mem_block **heap); +extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap); /* radeon_irq.c */ -extern int radeon_irq_emit( DRM_IOCTL_ARGS ); -extern int radeon_irq_wait( DRM_IOCTL_ARGS ); - -extern int radeon_emit_and_wait_irq(drm_device_t *dev); -extern int radeon_wait_irq(drm_device_t *dev, int swi_nr); -extern int radeon_emit_irq(drm_device_t *dev); - -extern void radeon_do_release(drm_device_t *dev); -extern int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); -extern irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS ); -extern void radeon_driver_irq_preinstall( drm_device_t *dev ); -extern void radeon_driver_irq_postinstall( drm_device_t *dev ); -extern void radeon_driver_irq_uninstall( drm_device_t *dev ); -extern void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp); -extern void radeon_driver_pretakedown(drm_device_t *dev); -extern int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv); -extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv); +extern int radeon_irq_emit(DRM_IOCTL_ARGS); +extern int radeon_irq_wait(DRM_IOCTL_ARGS); + +extern int radeon_emit_and_wait_irq(drm_device_t * dev); +extern int radeon_wait_irq(drm_device_t * dev, int swi_nr); +extern int radeon_emit_irq(drm_device_t * dev); + +extern void radeon_do_release(drm_device_t * dev); +extern int radeon_driver_vblank_wait(drm_device_t * dev, + unsigned int *sequence); +extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); +extern void radeon_driver_irq_preinstall(drm_device_t * dev); +extern void radeon_driver_irq_postinstall(drm_device_t * dev); +extern void radeon_driver_irq_uninstall(drm_device_t * dev); +extern void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp); +extern void radeon_driver_pretakedown(drm_device_t * dev); +extern int radeon_driver_open_helper(drm_device_t * dev, + drm_file_t * filp_priv); +extern void radeon_driver_free_filp_priv(drm_device_t * dev, + drm_file_t * filp_priv); /* Flags for stats.boxes */ @@ -278,7 +280,7 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri * for Radeon kernel driver. */ #define RADEON_AGP_COMMAND 0x0f60 -#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ +#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ # define RADEON_AGP_ENABLE (1<<8) #define RADEON_AUX_SCISSOR_CNTL 0x26f0 @@ -350,7 +352,6 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) - #define RADEON_GEN_INT_CNTL 0x0040 # define RADEON_CRTC_VBLANK_MASK (1 << 0) # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) @@ -551,7 +552,6 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) - /* CP registers */ #define RADEON_CP_ME_RAM_ADDR 0x07d4 #define RADEON_CP_ME_RAM_RADDR 0x07d8 @@ -668,19 +668,19 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri #define R200_PP_TXCBLEND_5 0x2f50 #define R200_PP_TXCBLEND_6 0x2f60 #define R200_PP_TXCBLEND_7 0x2f70 -#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 +#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 #define R200_PP_TFACTOR_0 0x2ee0 #define R200_SE_VTX_FMT_0 0x2088 #define R200_SE_VAP_CNTL 0x2080 #define R200_SE_TCL_MATRIX_SEL_0 0x2230 -#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 -#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 -#define R200_PP_TXFILTER_5 0x2ca0 -#define R200_PP_TXFILTER_4 0x2c80 -#define R200_PP_TXFILTER_3 0x2c60 -#define R200_PP_TXFILTER_2 0x2c40 -#define R200_PP_TXFILTER_1 0x2c20 -#define R200_PP_TXFILTER_0 0x2c00 +#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 +#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 +#define R200_PP_TXFILTER_5 0x2ca0 +#define R200_PP_TXFILTER_4 0x2c80 +#define R200_PP_TXFILTER_3 0x2c60 +#define R200_PP_TXFILTER_2 0x2c40 +#define R200_PP_TXFILTER_1 0x2c20 +#define R200_PP_TXFILTER_0 0x2c00 #define R200_PP_TXOFFSET_5 0x2d78 #define R200_PP_TXOFFSET_4 0x2d60 #define R200_PP_TXOFFSET_3 0x2d48 @@ -734,17 +734,16 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri #define R200_RE_SCISSOR_TL_0 0x1cd8 #define R200_RE_SCISSOR_TL_1 0x1ce0 #define R200_RE_SCISSOR_TL_2 0x1ce8 -#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 +#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 #define R200_SE_VTX_STATE_CNTL 0x2180 #define R200_RE_POINTSIZE 0x2648 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 -#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ +#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ #define RADEON_PP_TEX_SIZE_1 0x1d0c #define RADEON_PP_TEX_SIZE_2 0x1d14 - #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 @@ -755,7 +754,7 @@ extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_pri #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b #define R200_3D_DRAW_IMMD_2 0xC0003500 #define R200_SE_VTX_FMT_1 0x208c -#define R200_RE_CNTL 0x1c50 +#define R200_RE_CNTL 0x1c50 #define R200_RB3D_BLENDCOLOR 0x3218 @@ -785,10 +784,10 @@ do { \ RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ } while (0) -extern int RADEON_READ_PLL( drm_device_t *dev, int addr ); -extern int radeon_preinit( struct drm_device *dev, unsigned long flags ); -extern int radeon_postinit( struct drm_device *dev, unsigned long flags ); -extern int radeon_postcleanup( struct drm_device *dev ); +extern int RADEON_READ_PLL(drm_device_t * dev, int addr); +extern int radeon_preinit(struct drm_device *dev, unsigned long flags); +extern int radeon_postinit(struct drm_device *dev, unsigned long flags); +extern int radeon_postcleanup(struct drm_device *dev); #define CP_PACKET0( reg, n ) \ (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) @@ -801,7 +800,6 @@ extern int radeon_postcleanup( struct drm_device *dev ); #define CP_PACKET3( pkt, n ) \ (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) - /* ================================================================ * Engine control helper macros */ @@ -850,12 +848,11 @@ extern int radeon_postcleanup( struct drm_device *dev ); OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ } while (0) - /* ================================================================ * Misc helper macros */ -/* Perfbox functionality only. +/* Perfbox functionality only. */ #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ do { \ @@ -892,7 +889,6 @@ do { \ OUT_RING( age ); \ } while (0) - /* ================================================================ * Ring control */ @@ -953,7 +949,6 @@ do { \ OUT_RING( val ); \ } while (0) - #define OUT_RING_USER_TABLE( tab, sz ) do { \ int _size = (sz); \ int __user *_tab = (tab); \ @@ -976,5 +971,4 @@ do { \ write &= mask; \ } while (0) - -#endif /* __RADEON_DRV_H__ */ +#endif /* __RADEON_DRV_H__ */ diff --git a/shared-core/radeon_irq.c b/shared-core/radeon_irq.c index b7deca73..b48a7552 100644 --- a/shared-core/radeon_irq.c +++ b/shared-core/radeon_irq.c @@ -1,7 +1,7 @@ /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- * * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * + * * The Weather Channel (TM) funded Tungsten Graphics to develop the * initial release of the Radeon 8500 driver under the XFree86 license. * This notice must be preserved. @@ -53,31 +53,31 @@ * tied to dma at all, this is just a hangover from dri prehistory. */ -irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS ) +irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS) { drm_device_t *dev = (drm_device_t *) arg; - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; - u32 stat; + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *) dev->dev_private; + u32 stat; /* Only consider the bits we're interested in - others could be used * outside the DRM */ stat = RADEON_READ(RADEON_GEN_INT_STATUS) - & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT); + & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT); if (!stat) return IRQ_NONE; /* SW interrupt */ if (stat & RADEON_SW_INT_TEST) { - DRM_WAKEUP( &dev_priv->swi_queue ); + DRM_WAKEUP(&dev_priv->swi_queue); } /* VBLANK interrupt */ if (stat & RADEON_CRTC_VBLANK_STAT) { atomic_inc(&dev->vbl_received); DRM_WAKEUP(&dev->vbl_queue); - drm_vbl_send_signals( dev ); + drm_vbl_send_signals(dev); } /* Acknowledge interrupts we handle */ @@ -85,15 +85,15 @@ irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS ) return IRQ_HANDLED; } -static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv) +static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv) { - u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS ) - & (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT); + u32 tmp = RADEON_READ(RADEON_GEN_INT_STATUS) + & (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT); if (tmp) - RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp ); + RADEON_WRITE(RADEON_GEN_INT_STATUS, tmp); } -int radeon_emit_irq(drm_device_t *dev) +int radeon_emit_irq(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; unsigned int ret; @@ -102,156 +102,153 @@ int radeon_emit_irq(drm_device_t *dev) atomic_inc(&dev_priv->swi_emitted); ret = atomic_read(&dev_priv->swi_emitted); - BEGIN_RING( 4 ); - OUT_RING_REG( RADEON_LAST_SWI_REG, ret ); - OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE ); - ADVANCE_RING(); - COMMIT_RING(); + BEGIN_RING(4); + OUT_RING_REG(RADEON_LAST_SWI_REG, ret); + OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE); + ADVANCE_RING(); + COMMIT_RING(); return ret; } - -int radeon_wait_irq(drm_device_t *dev, int swi_nr) +int radeon_wait_irq(drm_device_t * dev, int swi_nr) { - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *) dev->dev_private; int ret = 0; - if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr) - return 0; + if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr) + return 0; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; /* This is a hack to work around mysterious freezes on certain * systems: - */ - radeon_acknowledge_irqs( dev_priv ); + */ + radeon_acknowledge_irqs(dev_priv); - DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ, - RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr ); + DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ, + RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr); return ret; } -int radeon_emit_and_wait_irq(drm_device_t *dev) +int radeon_emit_and_wait_irq(drm_device_t * dev) { - return radeon_wait_irq( dev, radeon_emit_irq(dev) ); + return radeon_wait_irq(dev, radeon_emit_irq(dev)); } - -int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) { - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *) dev->dev_private; unsigned int cur_vblank; int ret = 0; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - radeon_acknowledge_irqs( dev_priv ); + radeon_acknowledge_irqs(dev_priv); dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; /* Assume that the user has missed the current sequence number * by about a day rather than she wants to wait for years - * using vertical blanks... + * using vertical blanks... */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, - ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - - *sequence ) <= (1<<23) ) ); + DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, + (((cur_vblank = atomic_read(&dev->vbl_received)) + - *sequence) <= (1 << 23))); *sequence = cur_vblank; return ret; } - /* Needs the lock as it touches the ring. */ -int radeon_irq_emit( DRM_IOCTL_ARGS ) +int radeon_irq_emit(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_irq_emit_t emit; int result; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t __user *)data, - sizeof(emit) ); + DRM_COPY_FROM_USER_IOCTL(emit, (drm_radeon_irq_emit_t __user *) data, + sizeof(emit)); - result = radeon_emit_irq( dev ); + result = radeon_emit_irq(dev); - if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } return 0; } - /* Doesn't need the hardware lock. */ -int radeon_irq_wait( DRM_IOCTL_ARGS ) +int radeon_irq_wait(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_irq_wait_t irqwait; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t __user*)data, - sizeof(irqwait) ); + DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_radeon_irq_wait_t __user *) data, + sizeof(irqwait)); - return radeon_wait_irq( dev, irqwait.irq_seq ); + return radeon_wait_irq(dev, irqwait.irq_seq); } - /* drm_dma.h hooks */ -void radeon_driver_irq_preinstall( drm_device_t *dev ) { +void radeon_driver_irq_preinstall(drm_device_t * dev) +{ drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; + (drm_radeon_private_t *) dev->dev_private; - /* Disable *all* interrupts */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); + /* Disable *all* interrupts */ + RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); /* Clear bits if they're already high */ - radeon_acknowledge_irqs( dev_priv ); + radeon_acknowledge_irqs(dev_priv); } -void radeon_driver_irq_postinstall( drm_device_t *dev ) { +void radeon_driver_irq_postinstall(drm_device_t * dev) +{ drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; + (drm_radeon_private_t *) dev->dev_private; - atomic_set(&dev_priv->swi_emitted, 0); - DRM_INIT_WAITQUEUE( &dev_priv->swi_queue ); + atomic_set(&dev_priv->swi_emitted, 0); + DRM_INIT_WAITQUEUE(&dev_priv->swi_queue); /* Turn on SW and VBL ints */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, - RADEON_CRTC_VBLANK_MASK | - RADEON_SW_INT_ENABLE ); + RADEON_WRITE(RADEON_GEN_INT_CNTL, + RADEON_CRTC_VBLANK_MASK | RADEON_SW_INT_ENABLE); } -void radeon_driver_irq_uninstall( drm_device_t *dev ) { +void radeon_driver_irq_uninstall(drm_device_t * dev) +{ drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; + (drm_radeon_private_t *) dev->dev_private; if (!dev_priv) return; /* Disable *all* interrupts */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); + RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); } diff --git a/shared-core/radeon_mem.c b/shared-core/radeon_mem.c index 17483dd1..7cecd7ee 100644 --- a/shared-core/radeon_mem.c +++ b/shared-core/radeon_mem.c @@ -1,7 +1,7 @@ /* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*- * * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * + * * The Weather Channel (TM) funded Tungsten Graphics to develop the * initial release of the Radeon 8500 driver under the XFree86 license. * This notice must be preserved. @@ -35,16 +35,17 @@ #include "radeon_drv.h" /* Very simple allocator for GART memory, working on a static range - * already mapped into each client's address space. + * already mapped into each client's address space. */ static struct mem_block *split_block(struct mem_block *p, int start, int size, - DRMFILE filp ) + DRMFILE filp) { /* Maybe cut off the start of an existing block */ if (start > p->start) { - struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFS ); - if (!newblock) + struct mem_block *newblock = + drm_alloc(sizeof(*newblock), DRM_MEM_BUFS); + if (!newblock) goto out; newblock->start = start; newblock->size = p->size - (start - p->start); @@ -56,10 +57,11 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, p->size -= newblock->size; p = newblock; } - + /* Maybe cut off the end of an existing block */ if (size < p->size) { - struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFS ); + struct mem_block *newblock = + drm_alloc(sizeof(*newblock), DRM_MEM_BUFS); if (!newblock) goto out; newblock->start = start + size; @@ -72,40 +74,39 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, p->size = size; } - out: + out: /* Our block is in the middle */ p->filp = filp; return p; } -static struct mem_block *alloc_block( struct mem_block *heap, int size, - int align2, DRMFILE filp ) +static struct mem_block *alloc_block(struct mem_block *heap, int size, + int align2, DRMFILE filp) { struct mem_block *p; - int mask = (1 << align2)-1; + int mask = (1 << align2) - 1; - for (p = heap->next ; p != heap ; p = p->next) { + for (p = heap->next; p != heap; p = p->next) { int start = (p->start + mask) & ~mask; if (p->filp == 0 && start + size <= p->start + p->size) - return split_block( p, start, size, filp ); + return split_block(p, start, size, filp); } return NULL; } -static struct mem_block *find_block( struct mem_block *heap, int start ) +static struct mem_block *find_block(struct mem_block *heap, int start) { struct mem_block *p; - for (p = heap->next ; p != heap ; p = p->next) + for (p = heap->next; p != heap; p = p->next) if (p->start == start) return p; return NULL; } - -static void free_block( struct mem_block *p ) +static void free_block(struct mem_block *p) { p->filp = NULL; @@ -117,7 +118,7 @@ static void free_block( struct mem_block *p ) p->size += q->size; p->next = q->next; p->next->prev = p; - drm_free(q, sizeof(*q), DRM_MEM_BUFS ); + drm_free(q, sizeof(*q), DRM_MEM_BUFS); } if (p->prev->filp == 0) { @@ -125,7 +126,7 @@ static void free_block( struct mem_block *p ) q->size += p->size; q->next = p->next; q->next->prev = q; - drm_free(p, sizeof(*q), DRM_MEM_BUFS ); + drm_free(p, sizeof(*q), DRM_MEM_BUFS); } } @@ -133,14 +134,14 @@ static void free_block( struct mem_block *p ) */ static int init_heap(struct mem_block **heap, int start, int size) { - struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS ); + struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS); - if (!blocks) + if (!blocks) return DRM_ERR(ENOMEM); - - *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS ); + + *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS); if (!*heap) { - drm_free( blocks, sizeof(*blocks), DRM_MEM_BUFS ); + drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } @@ -149,70 +150,66 @@ static int init_heap(struct mem_block **heap, int start, int size) blocks->filp = NULL; blocks->next = blocks->prev = *heap; - memset( *heap, 0, sizeof(**heap) ); - (*heap)->filp = (DRMFILE) -1; + memset(*heap, 0, sizeof(**heap)); + (*heap)->filp = (DRMFILE) - 1; (*heap)->next = (*heap)->prev = blocks; return 0; } - /* Free all blocks associated with the releasing file. */ -void radeon_mem_release( DRMFILE filp, struct mem_block *heap ) +void radeon_mem_release(DRMFILE filp, struct mem_block *heap) { struct mem_block *p; if (!heap || !heap->next) return; - for (p = heap->next ; p != heap ; p = p->next) { - if (p->filp == filp) + for (p = heap->next; p != heap; p = p->next) { + if (p->filp == filp) p->filp = NULL; } /* Assumes a single contiguous range. Needs a special filp in * 'heap' to stop it being subsumed. */ - for (p = heap->next ; p != heap ; p = p->next) { + for (p = heap->next; p != heap; p = p->next) { while (p->filp == 0 && p->next->filp == 0) { struct mem_block *q = p->next; p->size += q->size; p->next = q->next; p->next->prev = p; - drm_free(q, sizeof(*q),DRM_MEM_DRIVER); + drm_free(q, sizeof(*q), DRM_MEM_DRIVER); } } } /* Shutdown. */ -void radeon_mem_takedown( struct mem_block **heap ) +void radeon_mem_takedown(struct mem_block **heap) { struct mem_block *p; - + if (!*heap) return; - for (p = (*heap)->next ; p != *heap ; ) { + for (p = (*heap)->next; p != *heap;) { struct mem_block *q = p; p = p->next; - drm_free(q, sizeof(*q),DRM_MEM_DRIVER); + drm_free(q, sizeof(*q), DRM_MEM_DRIVER); } - drm_free( *heap, sizeof(**heap),DRM_MEM_DRIVER ); + drm_free(*heap, sizeof(**heap), DRM_MEM_DRIVER); *heap = NULL; } - - /* IOCTL HANDLERS */ -static struct mem_block **get_heap( drm_radeon_private_t *dev_priv, - int region ) +static struct mem_block **get_heap(drm_radeon_private_t * dev_priv, int region) { - switch( region ) { + switch (region) { case RADEON_MEM_REGION_GART: - return &dev_priv->gart_heap; + return &dev_priv->gart_heap; case RADEON_MEM_REGION_FB: return &dev_priv->fb_heap; default: @@ -220,103 +217,98 @@ static struct mem_block **get_heap( drm_radeon_private_t *dev_priv, } } -int radeon_mem_alloc( DRM_IOCTL_ARGS ) +int radeon_mem_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_mem_alloc_t alloc; struct mem_block *block, **heap; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( alloc, (drm_radeon_mem_alloc_t __user *)data, - sizeof(alloc) ); + DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_mem_alloc_t __user *) data, + sizeof(alloc)); - heap = get_heap( dev_priv, alloc.region ); + heap = get_heap(dev_priv, alloc.region); if (!heap || !*heap) return DRM_ERR(EFAULT); - + /* Make things easier on ourselves: all allocations at least * 4k aligned. */ if (alloc.alignment < 12) alloc.alignment = 12; - block = alloc_block( *heap, alloc.size, alloc.alignment, - filp ); + block = alloc_block(*heap, alloc.size, alloc.alignment, filp); - if (!block) + if (!block) return DRM_ERR(ENOMEM); - if ( DRM_COPY_TO_USER( alloc.region_offset, &block->start, - sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (DRM_COPY_TO_USER(alloc.region_offset, &block->start, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } - + return 0; } - - -int radeon_mem_free( DRM_IOCTL_ARGS ) +int radeon_mem_free(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_mem_free_t memfree; struct mem_block *block, **heap; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( memfree, (drm_radeon_mem_free_t __user *)data, - sizeof(memfree) ); + DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *) data, + sizeof(memfree)); - heap = get_heap( dev_priv, memfree.region ); + heap = get_heap(dev_priv, memfree.region); if (!heap || !*heap) return DRM_ERR(EFAULT); - - block = find_block( *heap, memfree.region_offset ); + + block = find_block(*heap, memfree.region_offset); if (!block) return DRM_ERR(EFAULT); if (block->filp != filp) return DRM_ERR(EPERM); - free_block( block ); + free_block(block); return 0; } -int radeon_mem_init_heap( DRM_IOCTL_ARGS ) +int radeon_mem_init_heap(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_mem_init_heap_t initheap; struct mem_block **heap; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( initheap, (drm_radeon_mem_init_heap_t __user *)data, - sizeof(initheap) ); + DRM_COPY_FROM_USER_IOCTL(initheap, + (drm_radeon_mem_init_heap_t __user *) data, + sizeof(initheap)); - heap = get_heap( dev_priv, initheap.region ); - if (!heap) + heap = get_heap(dev_priv, initheap.region); + if (!heap) return DRM_ERR(EFAULT); - + if (*heap) { DRM_ERROR("heap already initialized?"); return DRM_ERR(EFAULT); } - - return init_heap( heap, initheap.start, initheap.size ); -} - + return init_heap(heap, initheap.start, initheap.size); +} diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index 35fb16e9..325ce070 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -33,72 +33,74 @@ #include "radeon_drm.h" #include "radeon_drv.h" - /* ================================================================ * Helper functions for client state checking and fixup */ -static __inline__ int radeon_check_and_fixup_offset( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - u32 *offset ) { +static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * + dev_priv, + drm_file_t * filp_priv, + u32 * offset) +{ u32 off = *offset; struct drm_radeon_driver_file_fields *radeon_priv; - if ( off >= dev_priv->fb_location && - off < ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) + if (off >= dev_priv->fb_location && + off < (dev_priv->gart_vm_start + dev_priv->gart_size)) return 0; radeon_priv = filp_priv->driver_priv; off += radeon_priv->radeon_fb_delta; - DRM_DEBUG( "offset fixed up to 0x%x\n", off ); + DRM_DEBUG("offset fixed up to 0x%x\n", off); - if ( off < dev_priv->fb_location || - off >= ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) - return DRM_ERR( EINVAL ); + if (off < dev_priv->fb_location || + off >= (dev_priv->gart_vm_start + dev_priv->gart_size)) + return DRM_ERR(EINVAL); *offset = off; return 0; } -static __inline__ int radeon_check_and_fixup_offset_user( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - u32 __user *offset ) { +static __inline__ int radeon_check_and_fixup_offset_user(drm_radeon_private_t * + dev_priv, + drm_file_t * filp_priv, + u32 __user * offset) +{ u32 off; - DRM_GET_USER_UNCHECKED( off, offset ); + DRM_GET_USER_UNCHECKED(off, offset); - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &off ) ) - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &off)) + return DRM_ERR(EINVAL); - DRM_PUT_USER_UNCHECKED( offset, off ); + DRM_PUT_USER_UNCHECKED(offset, off); return 0; } -static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - int id, - u32 __user *data ) { - switch ( id ) { +static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * + dev_priv, + drm_file_t * filp_priv, + int id, u32 __user * data) +{ + switch (id) { case RADEON_EMIT_PP_MISC: - if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv, - &data[( RADEON_RB3D_DEPTHOFFSET - - RADEON_PP_MISC ) / 4] ) ) { - DRM_ERROR( "Invalid depth buffer offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset_user(dev_priv, filp_priv, + &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) { + DRM_ERROR("Invalid depth buffer offset\n"); + return DRM_ERR(EINVAL); } break; case RADEON_EMIT_PP_CNTL: - if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv, - &data[( RADEON_RB3D_COLOROFFSET - - RADEON_PP_CNTL ) / 4] ) ) { - DRM_ERROR( "Invalid colour buffer offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset_user(dev_priv, filp_priv, + &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) { + DRM_ERROR("Invalid colour buffer offset\n"); + return DRM_ERR(EINVAL); } break; @@ -108,21 +110,20 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_ case R200_EMIT_PP_TXOFFSET_3: case R200_EMIT_PP_TXOFFSET_4: case R200_EMIT_PP_TXOFFSET_5: - if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv, - &data[0] ) ) { - DRM_ERROR( "Invalid R200 texture offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset_user(dev_priv, filp_priv, + &data[0])) { + DRM_ERROR("Invalid R200 texture offset\n"); + return DRM_ERR(EINVAL); } break; case RADEON_EMIT_PP_TXFILTER_0: case RADEON_EMIT_PP_TXFILTER_1: case RADEON_EMIT_PP_TXFILTER_2: - if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv, - &data[( RADEON_PP_TXOFFSET_0 - - RADEON_PP_TXFILTER_0 ) / 4] ) ) { - DRM_ERROR( "Invalid R100 texture offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset_user(dev_priv, filp_priv, + &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) { + DRM_ERROR("Invalid R100 texture offset\n"); + return DRM_ERR(EINVAL); } break; @@ -131,18 +132,20 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_ case R200_EMIT_PP_CUBIC_OFFSETS_2: case R200_EMIT_PP_CUBIC_OFFSETS_3: case R200_EMIT_PP_CUBIC_OFFSETS_4: - case R200_EMIT_PP_CUBIC_OFFSETS_5: { - int i; - for ( i = 0; i < 5; i++ ) { - if ( radeon_check_and_fixup_offset_user( dev_priv, - filp_priv, - &data[i] ) ) { - DRM_ERROR( "Invalid R200 cubic texture offset\n" ); - return DRM_ERR( EINVAL ); + case R200_EMIT_PP_CUBIC_OFFSETS_5:{ + int i; + for (i = 0; i < 5; i++) { + if (radeon_check_and_fixup_offset_user(dev_priv, + filp_priv, + &data + [i])) { + DRM_ERROR + ("Invalid R200 cubic texture offset\n"); + return DRM_ERR(EINVAL); + } } + break; } - break; - } case RADEON_EMIT_RB3D_COLORPITCH: case RADEON_EMIT_RE_LINE_PATTERN: @@ -208,254 +211,258 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_ break; default: - DRM_ERROR( "Unknown state packet ID %d\n", id ); - return DRM_ERR( EINVAL ); + DRM_ERROR("Unknown state packet ID %d\n", id); + return DRM_ERR(EINVAL); } return 0; } -static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_cmd_buffer_t *cmdbuf, - unsigned int *cmdsz ) { +static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * + dev_priv, + drm_file_t * filp_priv, + drm_radeon_cmd_buffer_t * + cmdbuf, + unsigned int *cmdsz) +{ u32 tmp[4]; - u32 __user *cmd = (u32 __user *)cmdbuf->buf; + u32 __user *cmd = (u32 __user *) cmdbuf->buf; - if ( DRM_COPY_FROM_USER_UNCHECKED( tmp, cmd, sizeof( tmp ) ) ) { - DRM_ERROR( "Failed to copy data from user space\n" ); - return DRM_ERR( EFAULT ); + if (DRM_COPY_FROM_USER_UNCHECKED(tmp, cmd, sizeof(tmp))) { + DRM_ERROR("Failed to copy data from user space\n"); + return DRM_ERR(EFAULT); } - *cmdsz = 2 + ( ( tmp[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 ); + *cmdsz = 2 + ((tmp[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16); - if ( ( tmp[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) { - DRM_ERROR( "Not a type 3 packet\n" ); - return DRM_ERR( EINVAL ); + if ((tmp[0] & 0xc0000000) != RADEON_CP_PACKET3) { + DRM_ERROR("Not a type 3 packet\n"); + return DRM_ERR(EINVAL); } - if ( 4 * *cmdsz > cmdbuf->bufsz ) { - DRM_ERROR( "Packet size larger than size of data provided\n" ); - return DRM_ERR( EINVAL ); + if (4 * *cmdsz > cmdbuf->bufsz) { + DRM_ERROR("Packet size larger than size of data provided\n"); + return DRM_ERR(EINVAL); } /* Check client state and fix it up if necessary */ - if ( tmp[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */ + if (tmp[0] & 0x8000) { /* MSB of opcode: next DWORD GUI_CNTL */ u32 offset; - if ( tmp[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL - | RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { + if (tmp[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL + | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { offset = tmp[2] << 10; - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { - DRM_ERROR( "Invalid first packet offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset + (dev_priv, filp_priv, &offset)) { + DRM_ERROR("Invalid first packet offset\n"); + return DRM_ERR(EINVAL); } - tmp[2] = ( tmp[2] & 0xffc00000 ) | offset >> 10; + tmp[2] = (tmp[2] & 0xffc00000) | offset >> 10; } - if ( ( tmp[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) && - ( tmp[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { + if ((tmp[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && + (tmp[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { offset = tmp[3] << 10; - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { - DRM_ERROR( "Invalid second packet offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset + (dev_priv, filp_priv, &offset)) { + DRM_ERROR("Invalid second packet offset\n"); + return DRM_ERR(EINVAL); } - tmp[3] = ( tmp[3] & 0xffc00000 ) | offset >> 10; + tmp[3] = (tmp[3] & 0xffc00000) | offset >> 10; } - if ( DRM_COPY_TO_USER_UNCHECKED( cmd, tmp, sizeof( tmp ) ) ) { - DRM_ERROR( "Failed to copy data to user space\n" ); - return DRM_ERR( EFAULT ); + if (DRM_COPY_TO_USER_UNCHECKED(cmd, tmp, sizeof(tmp))) { + DRM_ERROR("Failed to copy data to user space\n"); + return DRM_ERR(EFAULT); } } return 0; } - /* ================================================================ * CP hardware state programming functions */ -static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, - drm_clip_rect_t *box ) +static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv, + drm_clip_rect_t * box) { RING_LOCALS; - DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", - box->x1, box->y1, box->x2, box->y2 ); + DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n", + box->x1, box->y1, box->x2, box->y2); - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) ); - OUT_RING( (box->y1 << 16) | box->x1 ); - OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) ); - OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) ); + BEGIN_RING(4); + OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); + OUT_RING((box->y1 << 16) | box->x1); + OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); + OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); ADVANCE_RING(); } /* Emit 1.1 state */ -static int radeon_emit_state( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_context_regs_t *ctx, - drm_radeon_texture_regs_t *tex, - unsigned int dirty ) +static int radeon_emit_state(drm_radeon_private_t * dev_priv, + drm_file_t * filp_priv, + drm_radeon_context_regs_t * ctx, + drm_radeon_texture_regs_t * tex, + unsigned int dirty) { RING_LOCALS; - DRM_DEBUG( "dirty=0x%08x\n", dirty ); + DRM_DEBUG("dirty=0x%08x\n", dirty); - if ( dirty & RADEON_UPLOAD_CONTEXT ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &ctx->rb3d_depthoffset ) ) { - DRM_ERROR( "Invalid depth buffer offset\n" ); - return DRM_ERR( EINVAL ); + if (dirty & RADEON_UPLOAD_CONTEXT) { + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &ctx->rb3d_depthoffset)) { + DRM_ERROR("Invalid depth buffer offset\n"); + return DRM_ERR(EINVAL); } - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &ctx->rb3d_coloroffset ) ) { - DRM_ERROR( "Invalid depth buffer offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &ctx->rb3d_coloroffset)) { + DRM_ERROR("Invalid depth buffer offset\n"); + return DRM_ERR(EINVAL); } - BEGIN_RING( 14 ); - OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) ); - OUT_RING( ctx->pp_misc ); - OUT_RING( ctx->pp_fog_color ); - OUT_RING( ctx->re_solid_color ); - OUT_RING( ctx->rb3d_blendcntl ); - OUT_RING( ctx->rb3d_depthoffset ); - OUT_RING( ctx->rb3d_depthpitch ); - OUT_RING( ctx->rb3d_zstencilcntl ); - OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) ); - OUT_RING( ctx->pp_cntl ); - OUT_RING( ctx->rb3d_cntl ); - OUT_RING( ctx->rb3d_coloroffset ); - OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) ); - OUT_RING( ctx->rb3d_colorpitch ); + BEGIN_RING(14); + OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); + OUT_RING(ctx->pp_misc); + OUT_RING(ctx->pp_fog_color); + OUT_RING(ctx->re_solid_color); + OUT_RING(ctx->rb3d_blendcntl); + OUT_RING(ctx->rb3d_depthoffset); + OUT_RING(ctx->rb3d_depthpitch); + OUT_RING(ctx->rb3d_zstencilcntl); + OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2)); + OUT_RING(ctx->pp_cntl); + OUT_RING(ctx->rb3d_cntl); + OUT_RING(ctx->rb3d_coloroffset); + OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); + OUT_RING(ctx->rb3d_colorpitch); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_VERTFMT ) { - BEGIN_RING( 2 ); - OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) ); - OUT_RING( ctx->se_coord_fmt ); + if (dirty & RADEON_UPLOAD_VERTFMT) { + BEGIN_RING(2); + OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0)); + OUT_RING(ctx->se_coord_fmt); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_LINE ) { - BEGIN_RING( 5 ); - OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) ); - OUT_RING( ctx->re_line_pattern ); - OUT_RING( ctx->re_line_state ); - OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) ); - OUT_RING( ctx->se_line_width ); + if (dirty & RADEON_UPLOAD_LINE) { + BEGIN_RING(5); + OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1)); + OUT_RING(ctx->re_line_pattern); + OUT_RING(ctx->re_line_state); + OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0)); + OUT_RING(ctx->se_line_width); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_BUMPMAP ) { - BEGIN_RING( 5 ); - OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) ); - OUT_RING( ctx->pp_lum_matrix ); - OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) ); - OUT_RING( ctx->pp_rot_matrix_0 ); - OUT_RING( ctx->pp_rot_matrix_1 ); + if (dirty & RADEON_UPLOAD_BUMPMAP) { + BEGIN_RING(5); + OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0)); + OUT_RING(ctx->pp_lum_matrix); + OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1)); + OUT_RING(ctx->pp_rot_matrix_0); + OUT_RING(ctx->pp_rot_matrix_1); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_MASKS ) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) ); - OUT_RING( ctx->rb3d_stencilrefmask ); - OUT_RING( ctx->rb3d_ropcntl ); - OUT_RING( ctx->rb3d_planemask ); + if (dirty & RADEON_UPLOAD_MASKS) { + BEGIN_RING(4); + OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2)); + OUT_RING(ctx->rb3d_stencilrefmask); + OUT_RING(ctx->rb3d_ropcntl); + OUT_RING(ctx->rb3d_planemask); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_VIEWPORT ) { - BEGIN_RING( 7 ); - OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) ); - OUT_RING( ctx->se_vport_xscale ); - OUT_RING( ctx->se_vport_xoffset ); - OUT_RING( ctx->se_vport_yscale ); - OUT_RING( ctx->se_vport_yoffset ); - OUT_RING( ctx->se_vport_zscale ); - OUT_RING( ctx->se_vport_zoffset ); + if (dirty & RADEON_UPLOAD_VIEWPORT) { + BEGIN_RING(7); + OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5)); + OUT_RING(ctx->se_vport_xscale); + OUT_RING(ctx->se_vport_xoffset); + OUT_RING(ctx->se_vport_yscale); + OUT_RING(ctx->se_vport_yoffset); + OUT_RING(ctx->se_vport_zscale); + OUT_RING(ctx->se_vport_zoffset); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_SETUP ) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); - OUT_RING( ctx->se_cntl ); - OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) ); - OUT_RING( ctx->se_cntl_status ); + if (dirty & RADEON_UPLOAD_SETUP) { + BEGIN_RING(4); + OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0)); + OUT_RING(ctx->se_cntl); + OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0)); + OUT_RING(ctx->se_cntl_status); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_MISC ) { - BEGIN_RING( 2 ); - OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) ); - OUT_RING( ctx->re_misc ); + if (dirty & RADEON_UPLOAD_MISC) { + BEGIN_RING(2); + OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0)); + OUT_RING(ctx->re_misc); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_TEX0 ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &tex[0].pp_txoffset ) ) { - DRM_ERROR( "Invalid texture offset for unit 0\n" ); - return DRM_ERR( EINVAL ); + if (dirty & RADEON_UPLOAD_TEX0) { + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &tex[0].pp_txoffset)) { + DRM_ERROR("Invalid texture offset for unit 0\n"); + return DRM_ERR(EINVAL); } - BEGIN_RING( 9 ); - OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) ); - OUT_RING( tex[0].pp_txfilter ); - OUT_RING( tex[0].pp_txformat ); - OUT_RING( tex[0].pp_txoffset ); - OUT_RING( tex[0].pp_txcblend ); - OUT_RING( tex[0].pp_txablend ); - OUT_RING( tex[0].pp_tfactor ); - OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) ); - OUT_RING( tex[0].pp_border_color ); + BEGIN_RING(9); + OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5)); + OUT_RING(tex[0].pp_txfilter); + OUT_RING(tex[0].pp_txformat); + OUT_RING(tex[0].pp_txoffset); + OUT_RING(tex[0].pp_txcblend); + OUT_RING(tex[0].pp_txablend); + OUT_RING(tex[0].pp_tfactor); + OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0)); + OUT_RING(tex[0].pp_border_color); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_TEX1 ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &tex[1].pp_txoffset ) ) { - DRM_ERROR( "Invalid texture offset for unit 1\n" ); - return DRM_ERR( EINVAL ); + if (dirty & RADEON_UPLOAD_TEX1) { + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &tex[1].pp_txoffset)) { + DRM_ERROR("Invalid texture offset for unit 1\n"); + return DRM_ERR(EINVAL); } - BEGIN_RING( 9 ); - OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) ); - OUT_RING( tex[1].pp_txfilter ); - OUT_RING( tex[1].pp_txformat ); - OUT_RING( tex[1].pp_txoffset ); - OUT_RING( tex[1].pp_txcblend ); - OUT_RING( tex[1].pp_txablend ); - OUT_RING( tex[1].pp_tfactor ); - OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) ); - OUT_RING( tex[1].pp_border_color ); + BEGIN_RING(9); + OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5)); + OUT_RING(tex[1].pp_txfilter); + OUT_RING(tex[1].pp_txformat); + OUT_RING(tex[1].pp_txoffset); + OUT_RING(tex[1].pp_txcblend); + OUT_RING(tex[1].pp_txablend); + OUT_RING(tex[1].pp_tfactor); + OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0)); + OUT_RING(tex[1].pp_border_color); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_TEX2 ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &tex[2].pp_txoffset ) ) { - DRM_ERROR( "Invalid texture offset for unit 2\n" ); - return DRM_ERR( EINVAL ); + if (dirty & RADEON_UPLOAD_TEX2) { + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &tex[2].pp_txoffset)) { + DRM_ERROR("Invalid texture offset for unit 2\n"); + return DRM_ERR(EINVAL); } - BEGIN_RING( 9 ); - OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) ); - OUT_RING( tex[2].pp_txfilter ); - OUT_RING( tex[2].pp_txformat ); - OUT_RING( tex[2].pp_txoffset ); - OUT_RING( tex[2].pp_txcblend ); - OUT_RING( tex[2].pp_txablend ); - OUT_RING( tex[2].pp_tfactor ); - OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) ); - OUT_RING( tex[2].pp_border_color ); + BEGIN_RING(9); + OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5)); + OUT_RING(tex[2].pp_txfilter); + OUT_RING(tex[2].pp_txformat); + OUT_RING(tex[2].pp_txoffset); + OUT_RING(tex[2].pp_txcblend); + OUT_RING(tex[2].pp_txablend); + OUT_RING(tex[2].pp_tfactor); + OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0)); + OUT_RING(tex[2].pp_border_color); ADVANCE_RING(); } @@ -464,121 +471,125 @@ static int radeon_emit_state( drm_radeon_private_t *dev_priv, /* Emit 1.2 state */ -static int radeon_emit_state2( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_state_t *state ) +static int radeon_emit_state2(drm_radeon_private_t * dev_priv, + drm_file_t * filp_priv, + drm_radeon_state_t * state) { RING_LOCALS; if (state->dirty & RADEON_UPLOAD_ZBIAS) { - BEGIN_RING( 3 ); - OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) ); - OUT_RING( state->context2.se_zbias_factor ); - OUT_RING( state->context2.se_zbias_constant ); + BEGIN_RING(3); + OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1)); + OUT_RING(state->context2.se_zbias_factor); + OUT_RING(state->context2.se_zbias_constant); ADVANCE_RING(); } - return radeon_emit_state( dev_priv, filp_priv, &state->context, - state->tex, state->dirty ); + return radeon_emit_state(dev_priv, filp_priv, &state->context, + state->tex, state->dirty); } /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in * 1.3 cmdbuffers allow all previous state to be updated as well as - * the tcl scalar and vector areas. + * the tcl scalar and vector areas. */ -static struct { - int start; - int len; +static struct { + int start; + int len; const char *name; } packet[RADEON_MAX_STATE_PACKETS] = { - { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, - { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, - { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, - { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, - { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, - { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, - { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, - { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, - { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, - { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, - { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, - { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, - { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, - { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, - { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, - { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, - { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, - { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, - { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, - { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, - { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, - { R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" }, - { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" }, - { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" }, - { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" }, - { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" }, - { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" }, - { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" }, - { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" }, - { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, - { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" }, - { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" }, - { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" }, - { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" }, - { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" }, - { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, - { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" }, - { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" }, - { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" }, - { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" }, - { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" }, - { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" }, - { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" }, - { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" }, - { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" }, - { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" }, - { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" }, - { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" }, - { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, - { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, - { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, - { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, - { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, - { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, - { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, - { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, - { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, - { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, - { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, - { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, - { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, - { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ - { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ - { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" }, - { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" }, - { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" }, - { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" }, - { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" }, - { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" }, - { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" }, - { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" }, - { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" }, - { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, - { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, - { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, - { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, - { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, -}; - - + { + RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, { + RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, { + RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, { + RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, { + RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, { + RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, { + RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, { + RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, { + RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, { + RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, { + RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, { + RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, { + RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, { + RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, { + RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, { + RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, { + RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, { + RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, { + RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, { + RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, { + RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, + "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, { + R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, { + R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, { + R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, { + R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, { + R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, { + R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, { + R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, { + R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, { + R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, + { + R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, { + R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, { + R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, { + R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, { + R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, { + R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, + { + R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, { + R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, { + R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, { + R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, { + R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, { + R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, { + R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, { + R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, { + R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, { + R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, { + R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, { + R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, { + R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, { + R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, + { + R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, { + R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, { + R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, { + R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, { + R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, { + R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, { + R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, { + R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, { + R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, { + R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, { + R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, + "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, { + R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ + { + R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ + { + R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, { + R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, { + R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, { + R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, { + R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, { + R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, { + R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, { + R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, { + R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, { + R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, { + RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, { + RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, { + RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, { +R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},}; /* ================================================================ * Performance monitoring functions */ -static void radeon_clear_box( drm_radeon_private_t *dev_priv, - int x, int y, int w, int h, - int r, int g, int b ) +static void radeon_clear_box(drm_radeon_private_t * dev_priv, + int x, int y, int w, int h, int r, int g, int b) { u32 color; RING_LOCALS; @@ -586,49 +597,47 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv, x += dev_priv->sarea_priv->boxes[0].x1; y += dev_priv->sarea_priv->boxes[0].y1; - switch ( dev_priv->color_fmt ) { + switch (dev_priv->color_fmt) { case RADEON_COLOR_FORMAT_RGB565: color = (((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | - ((b & 0xf8) >> 3)); + ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); break; case RADEON_COLOR_FORMAT_ARGB8888: default: - color = (((0xff) << 24) | (r << 16) | (g << 8) | b); + color = (((0xff) << 24) | (r << 16) | (g << 8) | b); break; } - BEGIN_RING( 4 ); - RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); - OUT_RING( 0xffffffff ); + BEGIN_RING(4); + RADEON_WAIT_UNTIL_3D_IDLE(); + OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); + OUT_RING(0xffffffff); ADVANCE_RING(); - BEGIN_RING( 6 ); + BEGIN_RING(6); - OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS ); + OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); + OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS); - if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { - OUT_RING( dev_priv->front_pitch_offset ); - } else { - OUT_RING( dev_priv->back_pitch_offset ); - } + if (dev_priv->page_flipping && dev_priv->current_page == 1) { + OUT_RING(dev_priv->front_pitch_offset); + } else { + OUT_RING(dev_priv->back_pitch_offset); + } - OUT_RING( color ); + OUT_RING(color); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } -static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) +static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv) { /* Collapse various things into a wait flag -- trying to * guess if userspase slept -- better just to have them tell us. @@ -644,50 +653,50 @@ static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) /* Purple box for page flipping */ - if ( dev_priv->stats.boxes & RADEON_BOX_FLIP ) - radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 ); + if (dev_priv->stats.boxes & RADEON_BOX_FLIP) + radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255); /* Red box if we have to wait for idle at any point */ - if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE ) - radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 ); + if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE) + radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0); /* Blue box: lost context? */ /* Yellow box for texture swaps */ - if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD ) - radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 ); + if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD) + radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0); /* Green box if hardware never idles (as far as we can tell) */ - if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) ) - radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); + if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) + radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); - - /* Draw bars indicating number of buffers allocated + /* Draw bars indicating number of buffers allocated * (not a great measure, easily confused) */ if (dev_priv->stats.requested_bufs) { if (dev_priv->stats.requested_bufs > 100) dev_priv->stats.requested_bufs = 100; - radeon_clear_box( dev_priv, 4, 16, - dev_priv->stats.requested_bufs, 4, - 196, 128, 128 ); + radeon_clear_box(dev_priv, 4, 16, + dev_priv->stats.requested_bufs, 4, + 196, 128, 128); } - memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) ); + memset(&dev_priv->stats, 0, sizeof(dev_priv->stats)); } + /* ================================================================ * CP command dispatch functions */ -static void radeon_cp_dispatch_clear( drm_device_t *dev, - drm_radeon_clear_t *clear, - drm_radeon_clear_rect_t *depth_boxes ) +static void radeon_cp_dispatch_clear(drm_device_t * dev, + drm_radeon_clear_t * clear, + drm_radeon_clear_rect_t * depth_boxes) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -695,32 +704,34 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; unsigned int flags = clear->flags; - u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0; + u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0; int i; RING_LOCALS; - DRM_DEBUG( "flags = 0x%x\n", flags ); + DRM_DEBUG("flags = 0x%x\n", flags); dev_priv->stats.clears++; - if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { + if (dev_priv->page_flipping && dev_priv->current_page == 1) { unsigned int tmp = flags; flags &= ~(RADEON_FRONT | RADEON_BACK); - if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK; - if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT; + if (tmp & RADEON_FRONT) + flags |= RADEON_BACK; + if (tmp & RADEON_BACK) + flags |= RADEON_FRONT; } - if ( flags & (RADEON_FRONT | RADEON_BACK) ) { + if (flags & (RADEON_FRONT | RADEON_BACK)) { - BEGIN_RING( 4 ); + BEGIN_RING(4); /* Ensure the 3D stream is idle before doing a * 2D fill to clear the front or back buffer. */ RADEON_WAIT_UNTIL_3D_IDLE(); - - OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); - OUT_RING( clear->color_mask ); + + OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); + OUT_RING(clear->color_mask); ADVANCE_RING(); @@ -728,51 +739,55 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, */ dev_priv->sarea_priv->ctx_owner = 0; - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; - DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", - x, y, w, h, flags ); - - if ( flags & RADEON_FRONT ) { - BEGIN_RING( 6 ); - - OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS ); - - OUT_RING( dev_priv->front_pitch_offset ); - OUT_RING( clear->clear_color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - + DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n", + x, y, w, h, flags); + + if (flags & RADEON_FRONT) { + BEGIN_RING(6); + + OUT_RING(CP_PACKET3 + (RADEON_CNTL_PAINT_MULTI, 4)); + OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv-> + color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | + RADEON_GMC_CLR_CMP_CNTL_DIS); + + OUT_RING(dev_priv->front_pitch_offset); + OUT_RING(clear->clear_color); + + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); + ADVANCE_RING(); } - - if ( flags & RADEON_BACK ) { - BEGIN_RING( 6 ); - - OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS ); - - OUT_RING( dev_priv->back_pitch_offset ); - OUT_RING( clear->clear_color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + + if (flags & RADEON_BACK) { + BEGIN_RING(6); + + OUT_RING(CP_PACKET3 + (RADEON_CNTL_PAINT_MULTI, 4)); + OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv-> + color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | + RADEON_GMC_CLR_CMP_CNTL_DIS); + + OUT_RING(dev_priv->back_pitch_offset); + OUT_RING(clear->clear_color); + + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } @@ -783,8 +798,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, * rendering a quad into just those buffers. Thus, we have to * make sure the 3D engine is configured correctly. */ - if ( dev_priv->is_r200 && - (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) { + if (dev_priv->is_r200 && (flags & (RADEON_DEPTH | RADEON_STENCIL))) { int tempPP_CNTL; int tempRE_CNTL; @@ -803,37 +817,34 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, tempRE_CNTL = 0; tempRB3D_CNTL = depth_clear->rb3d_cntl; - tempRB3D_CNTL &= ~(1<<15); /* unset radeon magic flag */ + tempRB3D_CNTL &= ~(1 << 15); /* unset radeon magic flag */ tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; tempRB3D_STENCILREFMASK = 0x0; tempSE_CNTL = depth_clear->se_cntl; - - /* Disable TCL */ - tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ - (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); + tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ + (0x9 << + SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); tempRB3D_PLANEMASK = 0x0; tempRE_AUX_SCISSOR_CNTL = 0x0; tempSE_VTE_CNTL = - SE_VTE_CNTL__VTX_XY_FMT_MASK | - SE_VTE_CNTL__VTX_Z_FMT_MASK; + SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK; - /* Vertex format (X, Y, Z, W)*/ + /* Vertex format (X, Y, Z, W) */ tempSE_VTX_FMT_0 = - SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | - SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; + SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | + SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; tempSE_VTX_FMT_1 = 0x0; - - /* - * Depth buffer specific enables + /* + * Depth buffer specific enables */ if (flags & RADEON_DEPTH) { /* Enable depth buffer */ @@ -843,142 +854,133 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, tempRB3D_CNTL &= ~RADEON_Z_ENABLE; } - /* + /* * Stencil buffer specific enables */ - if ( flags & RADEON_STENCIL ) { - tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; - tempRB3D_STENCILREFMASK = clear->depth_mask; + if (flags & RADEON_STENCIL) { + tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; + tempRB3D_STENCILREFMASK = clear->depth_mask; } else { tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE; tempRB3D_STENCILREFMASK = 0x00000000; } - BEGIN_RING( 26 ); + BEGIN_RING(26); RADEON_WAIT_UNTIL_2D_IDLE(); - OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL ); - OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL ); - OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL ); - OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, - tempRB3D_ZSTENCILCNTL ); - OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, - tempRB3D_STENCILREFMASK ); - OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK ); - OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL ); - OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL ); - OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 ); - OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 ); - OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL ); - OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL, - tempRE_AUX_SCISSOR_CNTL ); + OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL); + OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL); + OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL); + OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL); + OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, + tempRB3D_STENCILREFMASK); + OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK); + OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL); + OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL); + OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0); + OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1); + OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL); + OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL); ADVANCE_RING(); /* Make sure we restore the 3D state next time. */ dev_priv->sarea_priv->ctx_owner = 0; - for ( i = 0 ; i < nbox ; i++ ) { - - /* Funny that this should be required -- + for (i = 0; i < nbox; i++) { + + /* Funny that this should be required -- * sets top-left? */ - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); - - BEGIN_RING( 14 ); - OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) ); - OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | - RADEON_PRIM_WALK_RING | - (3 << RADEON_NUM_VERTICES_SHIFT)) ); - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x3f800000 ); - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x3f800000 ); - OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x3f800000 ); + radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); + + BEGIN_RING(14); + OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12)); + OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | + RADEON_PRIM_WALK_RING | + (3 << RADEON_NUM_VERTICES_SHIFT))); + OUT_RING(depth_boxes[i].ui[CLEAR_X1]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x3f800000); + OUT_RING(depth_boxes[i].ui[CLEAR_X1]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x3f800000); + OUT_RING(depth_boxes[i].ui[CLEAR_X2]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x3f800000); ADVANCE_RING(); } - } - else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) { + } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) { rb3d_cntl = depth_clear->rb3d_cntl; - if ( flags & RADEON_DEPTH ) { - rb3d_cntl |= RADEON_Z_ENABLE; + if (flags & RADEON_DEPTH) { + rb3d_cntl |= RADEON_Z_ENABLE; } else { rb3d_cntl &= ~RADEON_Z_ENABLE; } - if ( flags & RADEON_STENCIL ) { - rb3d_cntl |= RADEON_STENCIL_ENABLE; - rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ + if (flags & RADEON_STENCIL) { + rb3d_cntl |= RADEON_STENCIL_ENABLE; + rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ } else { rb3d_cntl &= ~RADEON_STENCIL_ENABLE; rb3d_stencilrefmask = 0x00000000; } - BEGIN_RING( 13 ); + BEGIN_RING(13); RADEON_WAIT_UNTIL_2D_IDLE(); - OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) ); - OUT_RING( 0x00000000 ); - OUT_RING( rb3d_cntl ); - - OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, - depth_clear->rb3d_zstencilcntl ); - OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, - rb3d_stencilrefmask ); - OUT_RING_REG( RADEON_RB3D_PLANEMASK, - 0x00000000 ); - OUT_RING_REG( RADEON_SE_CNTL, - depth_clear->se_cntl ); + OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1)); + OUT_RING(0x00000000); + OUT_RING(rb3d_cntl); + + OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, + depth_clear->rb3d_zstencilcntl); + OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask); + OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000); + OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl); ADVANCE_RING(); /* Make sure we restore the 3D state next time. */ dev_priv->sarea_priv->ctx_owner = 0; - for ( i = 0 ; i < nbox ; i++ ) { - - /* Funny that this should be required -- + for (i = 0; i < nbox; i++) { + + /* Funny that this should be required -- * sets top-left? */ - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); - - BEGIN_RING( 15 ); - - OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) ); - OUT_RING( RADEON_VTX_Z_PRESENT | - RADEON_VTX_PKCOLOR_PRESENT); - OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | - RADEON_PRIM_WALK_RING | - RADEON_MAOS_ENABLE | - RADEON_VTX_FMT_RADEON_MODE | - (3 << RADEON_NUM_VERTICES_SHIFT)) ); - - - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x0 ); - - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x0 ); - - OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x0 ); + radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); + + BEGIN_RING(15); + + OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13)); + OUT_RING(RADEON_VTX_Z_PRESENT | + RADEON_VTX_PKCOLOR_PRESENT); + OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | + RADEON_PRIM_WALK_RING | + RADEON_MAOS_ENABLE | + RADEON_VTX_FMT_RADEON_MODE | + (3 << RADEON_NUM_VERTICES_SHIFT))); + + OUT_RING(depth_boxes[i].ui[CLEAR_X1]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x0); + + OUT_RING(depth_boxes[i].ui[CLEAR_X1]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x0); + + OUT_RING(depth_boxes[i].ui[CLEAR_X2]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x0); ADVANCE_RING(); } @@ -990,15 +992,15 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, */ dev_priv->sarea_priv->last_clear++; - BEGIN_RING( 4 ); + BEGIN_RING(4); - RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear ); + RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear); RADEON_WAIT_UNTIL_IDLE(); ADVANCE_RING(); } -static void radeon_cp_dispatch_swap( drm_device_t *dev ) +static void radeon_cp_dispatch_swap(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -1006,59 +1008,55 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev ) drm_clip_rect_t *pbox = sarea_priv->boxes; int i; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* Do some trivial performance monitoring... */ if (dev_priv->do_boxes) - radeon_cp_performance_boxes( dev_priv ); - + radeon_cp_performance_boxes(dev_priv); /* Wait for the 3D stream to idle before dispatching the bitblt. * This will prevent data corruption between the two streams. */ - BEGIN_RING( 2 ); + BEGIN_RING(2); RADEON_WAIT_UNTIL_3D_IDLE(); ADVANCE_RING(); - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; - DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n", - x, y, w, h ); - - BEGIN_RING( 7 ); - - OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL | - RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_NONE | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_S | - RADEON_DP_SRC_SOURCE_MEMORY | - RADEON_GMC_CLR_CMP_CNTL_DIS | - RADEON_GMC_WR_MSK_DIS ); - + DRM_DEBUG("dispatch swap %d,%d-%d,%d\n", x, y, w, h); + + BEGIN_RING(7); + + OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5)); + OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | + RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_NONE | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_S | + RADEON_DP_SRC_SOURCE_MEMORY | + RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); + /* Make this work even if front & back are flipped: */ if (dev_priv->current_page == 0) { - OUT_RING( dev_priv->back_pitch_offset ); - OUT_RING( dev_priv->front_pitch_offset ); - } - else { - OUT_RING( dev_priv->front_pitch_offset ); - OUT_RING( dev_priv->back_pitch_offset ); + OUT_RING(dev_priv->back_pitch_offset); + OUT_RING(dev_priv->front_pitch_offset); + } else { + OUT_RING(dev_priv->front_pitch_offset); + OUT_RING(dev_priv->back_pitch_offset); } - OUT_RING( (x << 16) | y ); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } @@ -1069,44 +1067,43 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev ) */ dev_priv->sarea_priv->last_frame++; - BEGIN_RING( 4 ); + BEGIN_RING(4); - RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); + RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame); RADEON_WAIT_UNTIL_2D_IDLE(); ADVANCE_RING(); } -static void radeon_cp_dispatch_flip( drm_device_t *dev ) +static void radeon_cp_dispatch_flip(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle; + drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle; int offset = (dev_priv->current_page == 1) - ? dev_priv->front_offset : dev_priv->back_offset; + ? dev_priv->front_offset : dev_priv->back_offset; RING_LOCALS; - DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", - __FUNCTION__, - dev_priv->current_page, - dev_priv->sarea_priv->pfCurrentPage); + DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage); /* Do some trivial performance monitoring... */ if (dev_priv->do_boxes) { dev_priv->stats.boxes |= RADEON_BOX_FLIP; - radeon_cp_performance_boxes( dev_priv ); + radeon_cp_performance_boxes(dev_priv); } /* Update the frame offsets for both CRTCs */ - BEGIN_RING( 6 ); + BEGIN_RING(6); RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch - + sarea->frame.x - * ( dev_priv->color_fmt - 2 ) ) & ~7 ) - + offset ); - OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base - + offset ); + OUT_RING_REG(RADEON_CRTC_OFFSET, + ((sarea->frame.y * dev_priv->front_pitch + + sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7) + + offset); + OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base + + offset); ADVANCE_RING(); @@ -1116,16 +1113,16 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev ) */ dev_priv->sarea_priv->last_frame++; dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = - 1 - dev_priv->current_page; + 1 - dev_priv->current_page; - BEGIN_RING( 2 ); + BEGIN_RING(2); - RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); + RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame); ADVANCE_RING(); } -static int bad_prim_vertex_nr( int primitive, int nr ) +static int bad_prim_vertex_nr(int primitive, int nr) { switch (primitive & RADEON_PRIM_TYPE_MASK) { case RADEON_PRIM_TYPE_NONE: @@ -1145,24 +1142,21 @@ static int bad_prim_vertex_nr( int primitive, int nr ) return nr < 3; default: return 1; - } + } } - - typedef struct { unsigned int start; unsigned int finish; unsigned int prim; unsigned int numverts; - unsigned int offset; - unsigned int vc_format; + unsigned int offset; + unsigned int vc_format; } drm_radeon_tcl_prim_t; -static void radeon_cp_dispatch_vertex( drm_device_t *dev, - drm_buf_t *buf, - drm_radeon_tcl_prim_t *prim ) - +static void radeon_cp_dispatch_vertex(drm_device_t * dev, + drm_buf_t * buf, + drm_radeon_tcl_prim_t * prim) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -1174,45 +1168,39 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev, DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n", prim->prim, - prim->vc_format, - prim->start, - prim->finish, - prim->numverts); + prim->vc_format, prim->start, prim->finish, prim->numverts); - if (bad_prim_vertex_nr( prim->prim, prim->numverts )) { - DRM_ERROR( "bad prim %x numverts %d\n", - prim->prim, prim->numverts ); + if (bad_prim_vertex_nr(prim->prim, prim->numverts)) { + DRM_ERROR("bad prim %x numverts %d\n", + prim->prim, prim->numverts); return; } do { /* Emit the next cliprect */ - if ( i < nbox ) { - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); + if (i < nbox) { + radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); } /* Emit the vertex buffer rendering commands */ - BEGIN_RING( 5 ); + BEGIN_RING(5); - OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) ); - OUT_RING( offset ); - OUT_RING( numverts ); - OUT_RING( prim->vc_format ); - OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST | - RADEON_COLOR_ORDER_RGBA | - RADEON_VTX_FMT_RADEON_MODE | - (numverts << RADEON_NUM_VERTICES_SHIFT) ); + OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3)); + OUT_RING(offset); + OUT_RING(numverts); + OUT_RING(prim->vc_format); + OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST | + RADEON_COLOR_ORDER_RGBA | + RADEON_VTX_FMT_RADEON_MODE | + (numverts << RADEON_NUM_VERTICES_SHIFT)); ADVANCE_RING(); i++; - } while ( i < nbox ); + } while (i < nbox); } - - -static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf ) +static void radeon_cp_discard_buffer(drm_device_t * dev, drm_buf_t * buf) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; @@ -1221,24 +1209,22 @@ static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf ) buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; /* Emit the vertex buffer age */ - BEGIN_RING( 2 ); - RADEON_DISPATCH_AGE( buf_priv->age ); + BEGIN_RING(2); + RADEON_DISPATCH_AGE(buf_priv->age); ADVANCE_RING(); buf->pending = 1; buf->used = 0; } -static void radeon_cp_dispatch_indirect( drm_device_t *dev, - drm_buf_t *buf, - int start, int end ) +static void radeon_cp_dispatch_indirect(drm_device_t * dev, + drm_buf_t * buf, int start, int end) { drm_radeon_private_t *dev_priv = dev->dev_private; RING_LOCALS; - DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", - buf->idx, start, end ); + DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); - if ( start != end ) { + if (start != end) { int offset = (dev_priv->gart_buffers_offset + buf->offset + start); int dwords = (end - start + 3) / sizeof(u32); @@ -1247,28 +1233,27 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev, * dwords, so if we've been given an odd number we must * pad the data with a Type-2 CP packet. */ - if ( dwords & 1 ) { + if (dwords & 1) { u32 *data = (u32 *) - ((char *)dev->agp_buffer_map->handle - + buf->offset + start); + ((char *)dev->agp_buffer_map->handle + + buf->offset + start); data[dwords++] = RADEON_CP_PACKET2; } /* Fire off the indirect buffer */ - BEGIN_RING( 3 ); + BEGIN_RING(3); - OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) ); - OUT_RING( offset ); - OUT_RING( dwords ); + OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1)); + OUT_RING(offset); + OUT_RING(dwords); ADVANCE_RING(); } } - -static void radeon_cp_dispatch_indices( drm_device_t *dev, - drm_buf_t *elt_buf, - drm_radeon_tcl_prim_t *prim ) +static void radeon_cp_dispatch_indices(drm_device_t * dev, + drm_buf_t * elt_buf, + drm_radeon_tcl_prim_t * prim) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -1283,30 +1268,24 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev, DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", prim->prim, prim->vc_format, - prim->start, - prim->finish, - prim->offset, - prim->numverts); - - if (bad_prim_vertex_nr( prim->prim, count )) { - DRM_ERROR( "bad prim %x count %d\n", - prim->prim, count ); + prim->start, prim->finish, prim->offset, prim->numverts); + + if (bad_prim_vertex_nr(prim->prim, count)) { + DRM_ERROR("bad prim %x count %d\n", prim->prim, count); return; } - - if ( start >= prim->finish || - (prim->start & 0x7) ) { - DRM_ERROR( "buffer prim %d\n", prim->prim ); + if (start >= prim->finish || (prim->start & 0x7)) { + DRM_ERROR("buffer prim %d\n", prim->prim); return; } dwords = (prim->finish - prim->start + 3) / sizeof(u32); - data = (u32 *)((char *)dev->agp_buffer_map->handle + - elt_buf->offset + prim->start); + data = (u32 *) ((char *)dev->agp_buffer_map->handle + + elt_buf->offset + prim->start); - data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); + data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2); data[1] = offset; data[2] = prim->numverts; data[3] = prim->vc_format; @@ -1314,28 +1293,26 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev, RADEON_PRIM_WALK_IND | RADEON_COLOR_ORDER_RGBA | RADEON_VTX_FMT_RADEON_MODE | - (count << RADEON_NUM_VERTICES_SHIFT) ); + (count << RADEON_NUM_VERTICES_SHIFT)); do { - if ( i < nbox ) - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); + if (i < nbox) + radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); - radeon_cp_dispatch_indirect( dev, elt_buf, - prim->start, - prim->finish ); + radeon_cp_dispatch_indirect(dev, elt_buf, + prim->start, prim->finish); i++; - } while ( i < nbox ); + } while (i < nbox); } #define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32)) -static int radeon_cp_dispatch_texture( DRMFILE filp, - drm_device_t *dev, - drm_radeon_texture_t *tex, - drm_radeon_tex_image_t *image ) +static int radeon_cp_dispatch_texture(DRMFILE filp, + drm_device_t * dev, + drm_radeon_texture_t * tex, + drm_radeon_tex_image_t * image) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_file_t *filp_priv; @@ -1348,11 +1325,11 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, int i; RING_LOCALS; - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &tex->offset ) ) { - DRM_ERROR( "Invalid destination offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) { + DRM_ERROR("Invalid destination offset\n"); + return DRM_ERR(EINVAL); } dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; @@ -1361,7 +1338,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, * up with the texture data from the host data blit, otherwise * part of the texture image may be corrupted. */ - BEGIN_RING( 4 ); + BEGIN_RING(4); RADEON_FLUSH_CACHE(); RADEON_WAIT_UNTIL_IDLE(); ADVANCE_RING(); @@ -1371,17 +1348,16 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, * chip wants it, but we need to compensate for the fact that the CP * ring gets byte-swapped */ - BEGIN_RING( 2 ); - OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT ); + BEGIN_RING(2); + OUT_RING_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT); ADVANCE_RING(); #endif - /* The compiler won't optimize away a division by a variable, * even if the only legal values are powers of two. Thus, we'll * use a shift instead. */ - switch ( tex->format ) { + switch (tex->format) { case RADEON_TXFORMAT_ARGB8888: case RADEON_TXFORMAT_RGBA8888: format = RADEON_COLOR_FORMAT_ARGB8888; @@ -1405,52 +1381,52 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, blit_width = image->width * 1; break; default: - DRM_ERROR( "invalid texture format %d\n", tex->format ); + DRM_ERROR("invalid texture format %d\n", tex->format); return DRM_ERR(EINVAL); } - DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width ); + DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); do { - DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", - tex->offset >> 10, tex->pitch, tex->format, - image->x, image->y, image->width, image->height ); + DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", + tex->offset >> 10, tex->pitch, tex->format, + image->x, image->y, image->width, image->height); /* Make a copy of some parameters in case we have to * update them for a multi-pass texture blit. */ height = image->height; data = (const u8 __user *)image->data; - + size = height * blit_width; - if ( size > RADEON_MAX_TEXTURE_SIZE ) { + if (size > RADEON_MAX_TEXTURE_SIZE) { height = RADEON_MAX_TEXTURE_SIZE / blit_width; size = height * blit_width; - } else if ( size < 4 && size > 0 ) { + } else if (size < 4 && size > 0) { size = 4; - } else if ( size == 0 ) { + } else if (size == 0) { return 0; } - buf = radeon_freelist_get( dev ); - if ( 0 && !buf ) { - radeon_do_cp_idle( dev_priv ); - buf = radeon_freelist_get( dev ); + buf = radeon_freelist_get(dev); + if (0 && !buf) { + radeon_do_cp_idle(dev_priv); + buf = radeon_freelist_get(dev); } - if ( !buf ) { + if (!buf) { DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); - if (DRM_COPY_TO_USER( tex->image, image, sizeof(*image) )) + if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) return DRM_ERR(EFAULT); return DRM_ERR(EAGAIN); } - /* Dispatch the indirect buffer. */ - buffer = (u32*)((char*)dev->agp_buffer_map->handle + buf->offset); + buffer = + (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); dwords = size / 4; - buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 ); + buffer[0] = CP_PACKET3(RADEON_CNTL_HOSTDATA_BLT, dwords + 6); buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL | RADEON_GMC_BRUSH_NONE | (format << 8) | @@ -1459,7 +1435,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, RADEON_DP_SRC_SOURCE_HOST_DATA | RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); - + buffer[2] = (tex->pitch << 22) | (tex->offset >> 10); buffer[3] = 0xffffffff; buffer[4] = 0xffffffff; @@ -1468,14 +1444,14 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, buffer[7] = dwords; buffer += 8; - if ( tex_width >= 32 ) { + if (tex_width >= 32) { /* Texture image width is larger than the minimum, so we * can upload it directly. */ - if ( DRM_COPY_FROM_USER( buffer, data, - dwords * sizeof(u32) ) ) { - DRM_ERROR( "EFAULT on data, %d dwords\n", - dwords ); + if (DRM_COPY_FROM_USER(buffer, data, + dwords * sizeof(u32))) { + DRM_ERROR("EFAULT on data, %d dwords\n", + dwords); return DRM_ERR(EFAULT); } } else { @@ -1483,11 +1459,10 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, * need to pad out each image scanline to the minimum * width. */ - for ( i = 0 ; i < tex->height ; i++ ) { - if ( DRM_COPY_FROM_USER( buffer, data, - tex_width ) ) { - DRM_ERROR( "EFAULT on pad, %d bytes\n", - tex_width ); + for (i = 0; i < tex->height; i++) { + if (DRM_COPY_FROM_USER(buffer, data, tex_width)) { + DRM_ERROR("EFAULT on pad, %d bytes\n", + tex_width); return DRM_ERR(EFAULT); } buffer += 8; @@ -1497,8 +1472,8 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, buf->filp = filp; buf->used = (dwords + 8) * sizeof(u32); - radeon_cp_dispatch_indirect( dev, buf, 0, buf->used ); - radeon_cp_discard_buffer( dev, buf ); + radeon_cp_dispatch_indirect(dev, buf, 0, buf->used); + radeon_cp_discard_buffer(dev, buf); /* Update the input parameters for next time */ image->y += height; @@ -1510,84 +1485,83 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, * the texture data is written out to memory before rendering * continues. */ - BEGIN_RING( 4 ); + BEGIN_RING(4); RADEON_FLUSH_CACHE(); RADEON_WAIT_UNTIL_2D_IDLE(); ADVANCE_RING(); return 0; } - -static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple ) +static void radeon_cp_dispatch_stipple(drm_device_t * dev, u32 * stipple) { drm_radeon_private_t *dev_priv = dev->dev_private; int i; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - BEGIN_RING( 35 ); + BEGIN_RING(35); - OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) ); - OUT_RING( 0x00000000 ); + OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0)); + OUT_RING(0x00000000); - OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) ); - for ( i = 0 ; i < 32 ; i++ ) { - OUT_RING( stipple[i] ); + OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31)); + for (i = 0; i < 32; i++) { + OUT_RING(stipple[i]); } ADVANCE_RING(); } - /* ================================================================ * IOCTL functions */ -int radeon_cp_clear( DRM_IOCTL_ARGS ) +int radeon_cp_clear(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_radeon_clear_t clear; drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t __user *)data, - sizeof(clear) ); + DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data, + sizeof(clear)); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes, - sarea_priv->nbox * sizeof(depth_boxes[0]) ) ) + if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes, + sarea_priv->nbox * sizeof(depth_boxes[0]))) return DRM_ERR(EFAULT); - radeon_cp_dispatch_clear( dev, &clear, depth_boxes ); + radeon_cp_dispatch_clear(dev, &clear, depth_boxes); COMMIT_RING(); return 0; } - /* Not sure why this isn't set all the time: - */ -static int radeon_do_init_pageflip( drm_device_t *dev ) + */ +static int radeon_do_init_pageflip(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - BEGIN_RING( 6 ); + BEGIN_RING(6); RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) ); - OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); - OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) ); - OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); + OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0)); + OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) | + RADEON_CRTC_OFFSET_FLIP_CNTL); + OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0)); + OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) | + RADEON_CRTC_OFFSET_FLIP_CNTL); ADVANCE_RING(); dev_priv->page_flipping = 1; @@ -1600,62 +1574,62 @@ static int radeon_do_init_pageflip( drm_device_t *dev ) /* Called whenever a client dies, from drm_release. * NOTE: Lock isn't necessarily held when this is called! */ -int radeon_do_cleanup_pageflip( drm_device_t *dev ) +int radeon_do_cleanup_pageflip(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); if (dev_priv->current_page != 0) - radeon_cp_dispatch_flip( dev ); + radeon_cp_dispatch_flip(dev); dev_priv->page_flipping = 0; return 0; } /* Swapping and flipping are different operations, need different ioctls. - * They can & should be intermixed to support multiple 3d windows. + * They can & should be intermixed to support multiple 3d windows. */ -int radeon_cp_flip( DRM_IOCTL_ARGS ) +int radeon_cp_flip(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - if (!dev_priv->page_flipping) - radeon_do_init_pageflip( dev ); - - radeon_cp_dispatch_flip( dev ); + if (!dev_priv->page_flipping) + radeon_do_init_pageflip(dev); + + radeon_cp_dispatch_flip(dev); COMMIT_RING(); return 0; } -int radeon_cp_swap( DRM_IOCTL_ARGS ) +int radeon_cp_swap(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - radeon_cp_dispatch_swap( dev ); + radeon_cp_dispatch_swap(dev); dev_priv->sarea_priv->ctx_owner = 0; COMMIT_RING(); return 0; } -int radeon_cp_vertex( DRM_IOCTL_ARGS ) +int radeon_cp_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1666,60 +1640,58 @@ int radeon_cp_vertex( DRM_IOCTL_ARGS ) drm_radeon_vertex_t vertex; drm_radeon_tcl_prim_t prim; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t __user *)data, - sizeof(vertex) ); + DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data, + sizeof(vertex)); - DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", - DRM_CURRENTPID, - vertex.idx, vertex.count, vertex.discard ); + DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", + DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard); - if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1 ); + if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + vertex.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - if ( vertex.prim < 0 || - vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { - DRM_ERROR( "buffer prim %d\n", vertex.prim ); + if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { + DRM_ERROR("buffer prim %d\n", vertex.prim); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[vertex.idx]; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", vertex.idx); return DRM_ERR(EINVAL); } /* Build up a prim_t record: */ if (vertex.count) { - buf->used = vertex.count; /* not used? */ - - if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { - if ( radeon_emit_state( dev_priv, filp_priv, - &sarea_priv->context_state, - sarea_priv->tex_state, - sarea_priv->dirty ) ) { - DRM_ERROR( "radeon_emit_state failed\n" ); - return DRM_ERR( EINVAL ); + buf->used = vertex.count; /* not used? */ + + if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { + if (radeon_emit_state(dev_priv, filp_priv, + &sarea_priv->context_state, + sarea_priv->tex_state, + sarea_priv->dirty)) { + DRM_ERROR("radeon_emit_state failed\n"); + return DRM_ERR(EINVAL); } sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | @@ -1729,23 +1701,23 @@ int radeon_cp_vertex( DRM_IOCTL_ARGS ) } prim.start = 0; - prim.finish = vertex.count; /* unused */ + prim.finish = vertex.count; /* unused */ prim.prim = vertex.prim; prim.numverts = vertex.count; prim.vc_format = dev_priv->sarea_priv->vc_format; - - radeon_cp_dispatch_vertex( dev, buf, &prim ); + + radeon_cp_dispatch_vertex(dev, buf, &prim); } if (vertex.discard) { - radeon_cp_discard_buffer( dev, buf ); + radeon_cp_discard_buffer(dev, buf); } COMMIT_RING(); return 0; } -int radeon_cp_indices( DRM_IOCTL_ARGS ) +int radeon_cp_indices(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1757,69 +1729,67 @@ int radeon_cp_indices( DRM_IOCTL_ARGS ) drm_radeon_tcl_prim_t prim; int count; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t __user *)data, - sizeof(elts) ); + DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data, + sizeof(elts)); - DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n", - DRM_CURRENTPID, - elts.idx, elts.start, elts.end, elts.discard ); + DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n", + DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard); - if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - elts.idx, dma->buf_count - 1 ); + if (elts.idx < 0 || elts.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + elts.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - if ( elts.prim < 0 || - elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { - DRM_ERROR( "buffer prim %d\n", elts.prim ); + if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { + DRM_ERROR("buffer prim %d\n", elts.prim); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[elts.idx]; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", elts.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", elts.idx); return DRM_ERR(EINVAL); } count = (elts.end - elts.start) / sizeof(u16); elts.start -= RADEON_INDEX_PRIM_OFFSET; - if ( elts.start & 0x7 ) { - DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); + if (elts.start & 0x7) { + DRM_ERROR("misaligned buffer 0x%x\n", elts.start); return DRM_ERR(EINVAL); } - if ( elts.start < buf->used ) { - DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); + if (elts.start < buf->used) { + DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); return DRM_ERR(EINVAL); } buf->used = elts.end; - if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { - if ( radeon_emit_state( dev_priv, filp_priv, - &sarea_priv->context_state, - sarea_priv->tex_state, - sarea_priv->dirty ) ) { - DRM_ERROR( "radeon_emit_state failed\n" ); - return DRM_ERR( EINVAL ); + if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { + if (radeon_emit_state(dev_priv, filp_priv, + &sarea_priv->context_state, + sarea_priv->tex_state, + sarea_priv->dirty)) { + DRM_ERROR("radeon_emit_state failed\n"); + return DRM_ERR(EINVAL); } sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | @@ -1828,26 +1798,25 @@ int radeon_cp_indices( DRM_IOCTL_ARGS ) RADEON_REQUIRE_QUIESCENCE); } - /* Build up a prim_t record: */ prim.start = elts.start; - prim.finish = elts.end; + prim.finish = elts.end; prim.prim = elts.prim; prim.offset = 0; /* offset from start of dma buffers */ - prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ + prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ prim.vc_format = dev_priv->sarea_priv->vc_format; - - radeon_cp_dispatch_indices( dev, buf, &prim ); + + radeon_cp_dispatch_indices(dev, buf, &prim); if (elts.discard) { - radeon_cp_discard_buffer( dev, buf ); + radeon_cp_discard_buffer(dev, buf); } COMMIT_RING(); return 0; } -int radeon_cp_texture( DRM_IOCTL_ARGS ) +int radeon_cp_texture(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1855,53 +1824,54 @@ int radeon_cp_texture( DRM_IOCTL_ARGS ) drm_radeon_tex_image_t image; int ret; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t __user *)data, sizeof(tex) ); + DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data, + sizeof(tex)); - if ( tex.image == NULL ) { - DRM_ERROR( "null texture image!\n" ); + if (tex.image == NULL) { + DRM_ERROR("null texture image!\n"); return DRM_ERR(EINVAL); } - if ( DRM_COPY_FROM_USER( &image, - (drm_radeon_tex_image_t __user *)tex.image, - sizeof(image) ) ) + if (DRM_COPY_FROM_USER(&image, + (drm_radeon_tex_image_t __user *) tex.image, + sizeof(image))) return DRM_ERR(EFAULT); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); - ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image ); + ret = radeon_cp_dispatch_texture(filp, dev, &tex, &image); COMMIT_RING(); return ret; } -int radeon_cp_stipple( DRM_IOCTL_ARGS ) +int radeon_cp_stipple(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_stipple_t stipple; u32 mask[32]; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t __user *)data, - sizeof(stipple) ); + DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data, + sizeof(stipple)); - if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) ) + if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) return DRM_ERR(EFAULT); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - radeon_cp_dispatch_stipple( dev, mask ); + radeon_cp_dispatch_stipple(dev, mask); COMMIT_RING(); return 0; } -int radeon_cp_indirect( DRM_IOCTL_ARGS ) +int radeon_cp_indirect(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1910,53 +1880,53 @@ int radeon_cp_indirect( DRM_IOCTL_ARGS ) drm_radeon_indirect_t indirect; RING_LOCALS; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t __user *)data, - sizeof(indirect) ); + DRM_COPY_FROM_USER_IOCTL(indirect, + (drm_radeon_indirect_t __user *) data, + sizeof(indirect)); - DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", - indirect.idx, indirect.start, - indirect.end, indirect.discard ); + DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n", + indirect.idx, indirect.start, indirect.end, indirect.discard); - if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - indirect.idx, dma->buf_count - 1 ); + if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + indirect.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } buf = dma->buflist[indirect.idx]; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", indirect.idx); return DRM_ERR(EINVAL); } - if ( indirect.start < buf->used ) { - DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", - indirect.start, buf->used ); + if (indirect.start < buf->used) { + DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", + indirect.start, buf->used); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf->used = indirect.end; /* Wait for the 3D stream to idle before the indirect buffer * containing 2D acceleration commands is processed. */ - BEGIN_RING( 2 ); + BEGIN_RING(2); RADEON_WAIT_UNTIL_3D_IDLE(); @@ -1966,17 +1936,16 @@ int radeon_cp_indirect( DRM_IOCTL_ARGS ) * X server. This is insecure and is thus only available to * privileged clients. */ - radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end ); + radeon_cp_dispatch_indirect(dev, buf, indirect.start, indirect.end); if (indirect.discard) { - radeon_cp_discard_buffer( dev, buf ); + radeon_cp_discard_buffer(dev, buf); } - COMMIT_RING(); return 0; } -int radeon_cp_vertex2( DRM_IOCTL_ARGS ) +int radeon_cp_vertex2(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1988,65 +1957,64 @@ int radeon_cp_vertex2( DRM_IOCTL_ARGS ) int i; unsigned char laststate; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t __user *)data, - sizeof(vertex) ); + DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data, + sizeof(vertex)); - DRM_DEBUG( "pid=%d index=%d discard=%d\n", - DRM_CURRENTPID, - vertex.idx, vertex.discard ); + DRM_DEBUG("pid=%d index=%d discard=%d\n", + DRM_CURRENTPID, vertex.idx, vertex.discard); - if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1 ); + if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + vertex.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[vertex.idx]; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", vertex.idx); return DRM_ERR(EINVAL); } - + if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) return DRM_ERR(EINVAL); - for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) { + for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) { drm_radeon_prim_t prim; drm_radeon_tcl_prim_t tclprim; - - if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) ) + + if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim))) return DRM_ERR(EFAULT); - - if ( prim.stateidx != laststate ) { - drm_radeon_state_t state; - - if ( DRM_COPY_FROM_USER( &state, - &vertex.state[prim.stateidx], - sizeof(state) ) ) + + if (prim.stateidx != laststate) { + drm_radeon_state_t state; + + if (DRM_COPY_FROM_USER(&state, + &vertex.state[prim.stateidx], + sizeof(state))) return DRM_ERR(EFAULT); - if ( radeon_emit_state2( dev_priv, filp_priv, &state ) ) { - DRM_ERROR( "radeon_emit_state2 failed\n" ); - return DRM_ERR( EINVAL ); + if (radeon_emit_state2(dev_priv, filp_priv, &state)) { + DRM_ERROR("radeon_emit_state2 failed\n"); + return DRM_ERR(EINVAL); } laststate = prim.stateidx; @@ -2057,42 +2025,40 @@ int radeon_cp_vertex2( DRM_IOCTL_ARGS ) tclprim.prim = prim.prim; tclprim.vc_format = prim.vc_format; - if ( prim.prim & RADEON_PRIM_WALK_IND ) { + if (prim.prim & RADEON_PRIM_WALK_IND) { tclprim.offset = prim.numverts * 64; - tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ + tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ - radeon_cp_dispatch_indices( dev, buf, &tclprim ); + radeon_cp_dispatch_indices(dev, buf, &tclprim); } else { tclprim.numverts = prim.numverts; - tclprim.offset = 0; /* not used */ + tclprim.offset = 0; /* not used */ - radeon_cp_dispatch_vertex( dev, buf, &tclprim ); + radeon_cp_dispatch_vertex(dev, buf, &tclprim); } - + if (sarea_priv->nbox == 1) sarea_priv->nbox = 0; } - if ( vertex.discard ) { - radeon_cp_discard_buffer( dev, buf ); + if (vertex.discard) { + radeon_cp_discard_buffer(dev, buf); } COMMIT_RING(); return 0; } - -static int radeon_emit_packets( - drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) +static int radeon_emit_packets(drm_radeon_private_t * dev_priv, + drm_file_t * filp_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t * cmdbuf) { int id = (int)header.packet.packet_id; int sz, reg; int __user *data = (int __user *)cmdbuf->buf; RING_LOCALS; - + if (id >= RADEON_MAX_STATE_PACKETS) return DRM_ERR(EINVAL); @@ -2100,18 +2066,18 @@ static int radeon_emit_packets( reg = packet[id].start; if (sz * sizeof(int) > cmdbuf->bufsz) { - DRM_ERROR( "Packet size provided larger than data provided\n" ); + DRM_ERROR("Packet size provided larger than data provided\n"); return DRM_ERR(EINVAL); } - if ( radeon_check_and_fixup_packets( dev_priv, filp_priv, id, data ) ) { - DRM_ERROR( "Packet verification failed\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) { + DRM_ERROR("Packet verification failed\n"); + return DRM_ERR(EINVAL); } - BEGIN_RING(sz+1); - OUT_RING( CP_PACKET0( reg, (sz-1) ) ); - OUT_RING_USER_TABLE( data, sz ); + BEGIN_RING(sz + 1); + OUT_RING(CP_PACKET0(reg, (sz - 1))); + OUT_RING_USER_TABLE(data, sz); ADVANCE_RING(); cmdbuf->buf += sz * sizeof(int); @@ -2119,10 +2085,9 @@ static int radeon_emit_packets( return 0; } -static __inline__ int radeon_emit_scalars( - drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) +static __inline__ int radeon_emit_scalars(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t * cmdbuf) { int sz = header.scalars.count; int __user *data = (int __user *)cmdbuf->buf; @@ -2130,11 +2095,11 @@ static __inline__ int radeon_emit_scalars( int stride = header.scalars.stride; RING_LOCALS; - BEGIN_RING( 3+sz ); - OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); - OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); - OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); - OUT_RING_USER_TABLE( data, sz ); + BEGIN_RING(3 + sz); + OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); + OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); + OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); + OUT_RING_USER_TABLE(data, sz); ADVANCE_RING(); cmdbuf->buf += sz * sizeof(int); cmdbuf->bufsz -= sz * sizeof(int); @@ -2143,10 +2108,9 @@ static __inline__ int radeon_emit_scalars( /* God this is ugly */ -static __inline__ int radeon_emit_scalars2( - drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) +static __inline__ int radeon_emit_scalars2(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t * cmdbuf) { int sz = header.scalars.count; int __user *data = (int __user *)cmdbuf->buf; @@ -2154,21 +2118,20 @@ static __inline__ int radeon_emit_scalars2( int stride = header.scalars.stride; RING_LOCALS; - BEGIN_RING( 3+sz ); - OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); - OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); - OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); - OUT_RING_USER_TABLE( data, sz ); + BEGIN_RING(3 + sz); + OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); + OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); + OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); + OUT_RING_USER_TABLE(data, sz); ADVANCE_RING(); cmdbuf->buf += sz * sizeof(int); cmdbuf->bufsz -= sz * sizeof(int); return 0; } -static __inline__ int radeon_emit_vectors( - drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) +static __inline__ int radeon_emit_vectors(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t * cmdbuf) { int sz = header.vectors.count; int __user *data = (int __user *)cmdbuf->buf; @@ -2176,11 +2139,11 @@ static __inline__ int radeon_emit_vectors( int stride = header.vectors.stride; RING_LOCALS; - BEGIN_RING( 3+sz ); - OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) ); - OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); - OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) ); - OUT_RING_USER_TABLE( data, sz ); + BEGIN_RING(3 + sz); + OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); + OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); + OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); + OUT_RING_USER_TABLE(data, sz); ADVANCE_RING(); cmdbuf->buf += sz * sizeof(int); @@ -2188,10 +2151,9 @@ static __inline__ int radeon_emit_vectors( return 0; } - -static int radeon_emit_packet3( drm_device_t *dev, - drm_file_t *filp_priv, - drm_radeon_cmd_buffer_t *cmdbuf ) +static int radeon_emit_packet3(drm_device_t * dev, + drm_file_t * filp_priv, + drm_radeon_cmd_buffer_t * cmdbuf) { drm_radeon_private_t *dev_priv = dev->dev_private; unsigned int cmdsz; @@ -2201,14 +2163,14 @@ static int radeon_emit_packet3( drm_device_t *dev, DRM_DEBUG("\n"); - if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, - cmdbuf, &cmdsz ) ) ) { - DRM_ERROR( "Packet verification failed\n" ); + if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv, + cmdbuf, &cmdsz))) { + DRM_ERROR("Packet verification failed\n"); return ret; } - BEGIN_RING( cmdsz ); - OUT_RING_USER_TABLE( cmd, cmdsz ); + BEGIN_RING(cmdsz); + OUT_RING_USER_TABLE(cmd, cmdsz); ADVANCE_RING(); cmdbuf->buf += cmdsz * 4; @@ -2216,11 +2178,10 @@ static int radeon_emit_packet3( drm_device_t *dev, return 0; } - -static int radeon_emit_packet3_cliprect( drm_device_t *dev, - drm_file_t *filp_priv, - drm_radeon_cmd_buffer_t *cmdbuf, - int orig_nbox ) +static int radeon_emit_packet3_cliprect(drm_device_t * dev, + drm_file_t * filp_priv, + drm_radeon_cmd_buffer_t * cmdbuf, + int orig_nbox) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_clip_rect_t box; @@ -2233,9 +2194,9 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev, DRM_DEBUG("\n"); - if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, - cmdbuf, &cmdsz ) ) ) { - DRM_ERROR( "Packet verification failed\n" ); + if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv, + cmdbuf, &cmdsz))) { + DRM_ERROR("Packet verification failed\n"); return ret; } @@ -2243,8 +2204,9 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev, goto out; do { - if ( i < cmdbuf->nbox ) { - if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) )) + if (i < cmdbuf->nbox) { + if (DRM_COPY_FROM_USER_UNCHECKED + (&box, &boxes[i], sizeof(box))) return DRM_ERR(EFAULT); /* FIXME The second and subsequent times round * this loop, send a WAIT_UNTIL_3D_IDLE before @@ -2258,30 +2220,29 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev, * the correct place to fix it but this works * around it until I can figure that out - Tim * Smith */ - if ( i ) { - BEGIN_RING( 2 ); + if (i) { + BEGIN_RING(2); RADEON_WAIT_UNTIL_3D_IDLE(); ADVANCE_RING(); } - radeon_emit_clip_rect( dev_priv, &box ); + radeon_emit_clip_rect(dev_priv, &box); } - - BEGIN_RING( cmdsz ); - OUT_RING_USER_TABLE( cmd, cmdsz ); + + BEGIN_RING(cmdsz); + OUT_RING_USER_TABLE(cmd, cmdsz); ADVANCE_RING(); - } while ( ++i < cmdbuf->nbox ); - if (cmdbuf->nbox == 1) + } while (++i < cmdbuf->nbox); + if (cmdbuf->nbox == 1) cmdbuf->nbox = 0; - out: + out: cmdbuf->buf += cmdsz * 4; cmdbuf->bufsz -= cmdsz * 4; return 0; } - -static int radeon_emit_wait( drm_device_t *dev, int flags ) +static int radeon_emit_wait(drm_device_t * dev, int flags) { drm_radeon_private_t *dev_priv = dev->dev_private; RING_LOCALS; @@ -2289,18 +2250,18 @@ static int radeon_emit_wait( drm_device_t *dev, int flags ) DRM_DEBUG("%s: %x\n", __FUNCTION__, flags); switch (flags) { case RADEON_WAIT_2D: - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_2D_IDLE(); + BEGIN_RING(2); + RADEON_WAIT_UNTIL_2D_IDLE(); ADVANCE_RING(); break; case RADEON_WAIT_3D: - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_3D_IDLE(); + BEGIN_RING(2); + RADEON_WAIT_UNTIL_3D_IDLE(); ADVANCE_RING(); break; - case RADEON_WAIT_2D|RADEON_WAIT_3D: - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_IDLE(); + case RADEON_WAIT_2D | RADEON_WAIT_3D: + BEGIN_RING(2); + RADEON_WAIT_UNTIL_IDLE(); ADVANCE_RING(); break; default: @@ -2310,7 +2271,7 @@ static int radeon_emit_wait( drm_device_t *dev, int flags ) return 0; } -int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) +int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2322,35 +2283,35 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) drm_radeon_cmd_header_t header; int orig_nbox; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t __user *)data, - sizeof(cmdbuf) ); + DRM_COPY_FROM_USER_IOCTL(cmdbuf, + (drm_radeon_cmd_buffer_t __user *) data, + sizeof(cmdbuf)); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); - - if (DRM_VERIFYAREA_READ( cmdbuf.buf, cmdbuf.bufsz )) + if (DRM_VERIFYAREA_READ(cmdbuf.buf, cmdbuf.bufsz)) return DRM_ERR(EFAULT); if (cmdbuf.nbox && - DRM_VERIFYAREA_READ(cmdbuf.boxes, - cmdbuf.nbox * sizeof(drm_clip_rect_t))) + DRM_VERIFYAREA_READ(cmdbuf.boxes, + cmdbuf.nbox * sizeof(drm_clip_rect_t))) return DRM_ERR(EFAULT); orig_nbox = cmdbuf.nbox; - while ( cmdbuf.bufsz >= sizeof(header) ) { - - if (DRM_GET_USER_UNCHECKED( header.i, (int __user *)cmdbuf.buf )) { + while (cmdbuf.bufsz >= sizeof(header)) { + + if (DRM_GET_USER_UNCHECKED(header.i, (int __user *)cmdbuf.buf)) { DRM_ERROR("__get_user %p\n", cmdbuf.buf); return DRM_ERR(EFAULT); } @@ -2359,9 +2320,10 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) cmdbuf.bufsz -= sizeof(header); switch (header.header.cmd_type) { - case RADEON_CMD_PACKET: + case RADEON_CMD_PACKET: DRM_DEBUG("RADEON_CMD_PACKET\n"); - if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) { + if (radeon_emit_packets + (dev_priv, filp_priv, header, &cmdbuf)) { DRM_ERROR("radeon_emit_packets failed\n"); return DRM_ERR(EINVAL); } @@ -2369,7 +2331,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_SCALARS: DRM_DEBUG("RADEON_CMD_SCALARS\n"); - if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) { + if (radeon_emit_scalars(dev_priv, header, &cmdbuf)) { DRM_ERROR("radeon_emit_scalars failed\n"); return DRM_ERR(EINVAL); } @@ -2377,7 +2339,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_VECTORS: DRM_DEBUG("RADEON_CMD_VECTORS\n"); - if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) { + if (radeon_emit_vectors(dev_priv, header, &cmdbuf)) { DRM_ERROR("radeon_emit_vectors failed\n"); return DRM_ERR(EINVAL); } @@ -2386,25 +2348,25 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_DMA_DISCARD: DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); idx = header.dma.buf_idx; - if ( idx < 0 || idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - idx, dma->buf_count - 1 ); + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } buf = dma->buflist[idx]; - if ( buf->filp != filp || buf->pending ) { - DRM_ERROR( "bad buffer %p %p %d\n", - buf->filp, filp, buf->pending); + if (buf->filp != filp || buf->pending) { + DRM_ERROR("bad buffer %p %p %d\n", + buf->filp, filp, buf->pending); return DRM_ERR(EINVAL); } - radeon_cp_discard_buffer( dev, buf ); + radeon_cp_discard_buffer(dev, buf); break; case RADEON_CMD_PACKET3: DRM_DEBUG("RADEON_CMD_PACKET3\n"); - if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) { + if (radeon_emit_packet3(dev, filp_priv, &cmdbuf)) { DRM_ERROR("radeon_emit_packet3 failed\n"); return DRM_ERR(EINVAL); } @@ -2412,7 +2374,8 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_PACKET3_CLIP: DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); - if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) { + if (radeon_emit_packet3_cliprect + (dev, filp_priv, &cmdbuf, orig_nbox)) { DRM_ERROR("radeon_emit_packet3_clip failed\n"); return DRM_ERR(EINVAL); } @@ -2420,7 +2383,7 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_SCALARS2: DRM_DEBUG("RADEON_CMD_SCALARS2\n"); - if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) { + if (radeon_emit_scalars2(dev_priv, header, &cmdbuf)) { DRM_ERROR("radeon_emit_scalars2 failed\n"); return DRM_ERR(EINVAL); } @@ -2428,58 +2391,55 @@ int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_WAIT: DRM_DEBUG("RADEON_CMD_WAIT\n"); - if (radeon_emit_wait( dev, header.wait.flags )) { + if (radeon_emit_wait(dev, header.wait.flags)) { DRM_ERROR("radeon_emit_wait failed\n"); return DRM_ERR(EINVAL); } break; default: - DRM_ERROR("bad cmd_type %d at %p\n", + DRM_ERROR("bad cmd_type %d at %p\n", header.header.cmd_type, cmdbuf.buf - sizeof(header)); return DRM_ERR(EINVAL); } } - DRM_DEBUG("DONE\n"); COMMIT_RING(); return 0; } - - -int radeon_cp_getparam( DRM_IOCTL_ARGS ) +int radeon_cp_getparam(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_getparam_t param; int value; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t __user *)data, - sizeof(param) ); + DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data, + sizeof(param)); - DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); + DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - switch( param.param ) { + switch (param.param) { case RADEON_PARAM_GART_BUFFER_OFFSET: value = dev_priv->gart_buffers_offset; break; case RADEON_PARAM_LAST_FRAME: dev_priv->stats.last_frame_reads++; - value = GET_SCRATCH( 0 ); + value = GET_SCRATCH(0); break; case RADEON_PARAM_LAST_DISPATCH: - value = GET_SCRATCH( 1 ); + value = GET_SCRATCH(1); break; case RADEON_PARAM_LAST_CLEAR: dev_priv->stats.last_clear_reads++; - value = GET_SCRATCH( 2 ); + value = GET_SCRATCH(2); break; case RADEON_PARAM_IRQ_NR: value = dev->irq; @@ -2494,15 +2454,15 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS ) value = dev_priv->ring_rptr_offset; break; #if BITS_PER_LONG == 32 - /* - * This ioctl() doesn't work on 64-bit platforms because hw_lock is a - * pointer which can't fit into an int-sized variable. According to - * Michel Dänzer, the ioctl() is only used on embedded platforms, so - * not supporting it shouldn't be a problem. If the same functionality - * is needed on 64-bit platforms, a new ioctl() would have to be added, - * so backwards-compatibility for the embedded platforms can be - * maintained. --davidm 4-Feb-2004. - */ + /* + * This ioctl() doesn't work on 64-bit platforms because hw_lock is a + * pointer which can't fit into an int-sized variable. According to + * Michel Dänzer, the ioctl() is only used on embedded platforms, so + * not supporting it shouldn't be a problem. If the same functionality + * is needed on 64-bit platforms, a new ioctl() would have to be added, + * so backwards-compatibility for the embedded platforms can be + * maintained. --davidm 4-Feb-2004. + */ case RADEON_PARAM_SAREA_HANDLE: /* The lock is the first dword in the sarea. */ value = (long)dev->lock.hw_lock; @@ -2515,39 +2475,40 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS ) return DRM_ERR(EINVAL); } - if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } - + return 0; } -int radeon_cp_setparam( DRM_IOCTL_ARGS ) { +int radeon_cp_setparam(DRM_IOCTL_ARGS) +{ DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_file_t *filp_priv; drm_radeon_setparam_t sp; struct drm_radeon_driver_file_fields *radeon_priv; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR( EINVAL ); + + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); + return DRM_ERR(EINVAL); } - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL( sp, ( drm_radeon_setparam_t __user * )data, - sizeof( sp ) ); + DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data, + sizeof(sp)); - switch( sp.param ) { + switch (sp.param) { case RADEON_SETPARAM_FB_LOCATION: radeon_priv = filp_priv->driver_priv; radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; break; default: - DRM_DEBUG( "Invalid parameter %d\n", sp.param ); - return DRM_ERR( EINVAL ); + DRM_DEBUG("Invalid parameter %d\n", sp.param); + return DRM_ERR(EINVAL); } return 0; @@ -2559,46 +2520,48 @@ int radeon_cp_setparam( DRM_IOCTL_ARGS ) { * * DRM infrastructure takes care of reclaiming dma buffers. */ -void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp) +void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp) { - if ( dev->dev_private ) { - drm_radeon_private_t *dev_priv = dev->dev_private; - if ( dev_priv->page_flipping ) { - radeon_do_cleanup_pageflip( dev ); - } - radeon_mem_release( filp, dev_priv->gart_heap ); - radeon_mem_release( filp, dev_priv->fb_heap ); - } + if (dev->dev_private) { + drm_radeon_private_t *dev_priv = dev->dev_private; + if (dev_priv->page_flipping) { + radeon_do_cleanup_pageflip(dev); + } + radeon_mem_release(filp, dev_priv->gart_heap); + radeon_mem_release(filp, dev_priv->fb_heap); + } } -void radeon_driver_pretakedown(drm_device_t *dev) +void radeon_driver_pretakedown(drm_device_t * dev) { radeon_do_release(dev); } -int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv) +int radeon_driver_open_helper(drm_device_t * dev, drm_file_t * filp_priv) { drm_radeon_private_t *dev_priv = dev->dev_private; struct drm_radeon_driver_file_fields *radeon_priv; - - radeon_priv = (struct drm_radeon_driver_file_fields *)drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES); - + + radeon_priv = + (struct drm_radeon_driver_file_fields *) + drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES); + if (!radeon_priv) return -ENOMEM; - + filp_priv->driver_priv = radeon_priv; - - if ( dev_priv ) + + if (dev_priv) radeon_priv->radeon_fb_delta = dev_priv->fb_location; else radeon_priv->radeon_fb_delta = 0; return 0; } -void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv) +void radeon_driver_free_filp_priv(drm_device_t * dev, drm_file_t * filp_priv) { - struct drm_radeon_driver_file_fields *radeon_priv = filp_priv->driver_priv; - + struct drm_radeon_driver_file_fields *radeon_priv = + filp_priv->driver_priv; + drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); } - diff --git a/shared-core/sis_drm.h b/shared-core/sis_drm.h index e99c3a43..8f273da7 100644 --- a/shared-core/sis_drm.h +++ b/shared-core/sis_drm.h @@ -39,4 +39,4 @@ typedef struct { unsigned int offset, size; } drm_sis_fb_t; -#endif /* __SIS_DRM_H__ */ +#endif /* __SIS_DRM_H__ */ diff --git a/shared-core/sis_drv.h b/shared-core/sis_drv.h index 7232b8f3..2f0f2b84 100644 --- a/shared-core/sis_drv.h +++ b/shared-core/sis_drv.h @@ -10,11 +10,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -22,7 +22,7 @@ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. - * + * */ #ifndef _SIS_DRV_H_ @@ -46,14 +46,14 @@ typedef struct drm_sis_private { memHeap_t *FBHeap; } drm_sis_private_t; -extern int sis_fb_alloc( DRM_IOCTL_ARGS ); -extern int sis_fb_free( DRM_IOCTL_ARGS ); -extern int sis_ioctl_agp_init( DRM_IOCTL_ARGS ); -extern int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS ); -extern int sis_ioctl_agp_free( DRM_IOCTL_ARGS ); -extern int sis_fb_init( DRM_IOCTL_ARGS ); +extern int sis_fb_alloc(DRM_IOCTL_ARGS); +extern int sis_fb_free(DRM_IOCTL_ARGS); +extern int sis_ioctl_agp_init(DRM_IOCTL_ARGS); +extern int sis_ioctl_agp_alloc(DRM_IOCTL_ARGS); +extern int sis_ioctl_agp_free(DRM_IOCTL_ARGS); +extern int sis_fb_init(DRM_IOCTL_ARGS); -extern int sis_init_context(drm_device_t *dev, int context); -extern int sis_final_context(drm_device_t *dev, int context); +extern int sis_init_context(drm_device_t * dev, int context); +extern int sis_final_context(drm_device_t * dev, int context); #endif diff --git a/shared-core/sis_ds.c b/shared-core/sis_ds.c index 60bffa69..cc49c27d 100644 --- a/shared-core/sis_ds.c +++ b/shared-core/sis_ds.c @@ -10,11 +10,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -22,10 +22,10 @@ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. - * + * * Authors: * Sung-Ching Lin - * + * */ #include "drmP.h" @@ -41,13 +41,13 @@ set_t *setInit(void) int i; set_t *set; - set = (set_t *)drm_alloc(sizeof(set_t), DRM_MEM_DRIVER); + set = (set_t *) drm_alloc(sizeof(set_t), DRM_MEM_DRIVER); if (set != NULL) { for (i = 0; i < SET_SIZE; i++) { - set->list[i].free_next = i + 1; + set->list[i].free_next = i + 1; set->list[i].alloc_next = -1; } - set->list[SET_SIZE-1].free_next = -1; + set->list[SET_SIZE - 1].free_next = -1; set->free = 0; set->alloc = -1; set->trace = -1; @@ -55,10 +55,10 @@ set_t *setInit(void) return set; } -int setAdd(set_t *set, ITEM_TYPE item) +int setAdd(set_t * set, ITEM_TYPE item) { int free = set->free; - + if (free != -1) { set->list[free].val = item; set->free = set->list[free].free_next; @@ -67,16 +67,16 @@ int setAdd(set_t *set, ITEM_TYPE item) } set->list[free].alloc_next = set->alloc; - set->alloc = free; - set->list[free].free_next = -1; + set->alloc = free; + set->list[free].free_next = -1; return 1; } -int setDel(set_t *set, ITEM_TYPE item) +int setDel(set_t * set, ITEM_TYPE item) { int alloc = set->alloc; - int prev = -1; + int prev = -1; while (alloc != -1) { if (set->list[alloc].val == item) { @@ -103,7 +103,7 @@ int setDel(set_t *set, ITEM_TYPE item) /* setFirst -> setAdd -> setNext is wrong */ -int setFirst(set_t *set, ITEM_TYPE *item) +int setFirst(set_t * set, ITEM_TYPE * item) { if (set->alloc == -1) return 0; @@ -114,7 +114,7 @@ int setFirst(set_t *set, ITEM_TYPE *item) return 1; } -int setNext(set_t *set, ITEM_TYPE *item) +int setNext(set_t * set, ITEM_TYPE * item) { if (set->trace == -1) return 0; @@ -125,7 +125,7 @@ int setNext(set_t *set, ITEM_TYPE *item) return 1; } -int setDestroy(set_t *set) +int setDestroy(set_t * set) { drm_free(set, sizeof(set_t), DRM_MEM_DRIVER); @@ -149,35 +149,34 @@ int setDestroy(set_t *set) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #define ISFREE(bptr) ((bptr)->free) -memHeap_t *mmInit(int ofs, - int size) +memHeap_t *mmInit(int ofs, int size) { PMemBlock blocks; if (size <= 0) return NULL; - blocks = (TMemBlock *)drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER); + blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER); if (blocks != NULL) { blocks->ofs = ofs; blocks->size = size; blocks->free = 1; - return (memHeap_t *)blocks; + return (memHeap_t *) blocks; } else return NULL; } /* Checks if a pointer 'b' is part of the heap 'heap' */ -int mmBlockInHeap(memHeap_t *heap, PMemBlock b) +int mmBlockInHeap(memHeap_t * heap, PMemBlock b) { TMemBlock *p; @@ -196,12 +195,10 @@ int mmBlockInHeap(memHeap_t *heap, PMemBlock b) /* Kludgey workaround for existing i810 server. Remove soon. */ -memHeap_t *mmAddRange( memHeap_t *heap, - int ofs, - int size ) +memHeap_t *mmAddRange(memHeap_t * heap, int ofs, int size) { PMemBlock blocks; - blocks = (TMemBlock *)drm_calloc(2, sizeof(TMemBlock), DRM_MEM_DRIVER); + blocks = (TMemBlock *) drm_calloc(2, sizeof(TMemBlock), DRM_MEM_DRIVER); if (blocks != NULL) { blocks[0].size = size; blocks[0].free = 1; @@ -213,23 +210,23 @@ memHeap_t *mmAddRange( memHeap_t *heap, */ blocks[1].size = 0; blocks[1].free = 0; - blocks[1].ofs = ofs+size; - blocks[1].next = (PMemBlock)heap; - return (memHeap_t *)blocks; + blocks[1].ofs = ofs + size; + blocks[1].next = (PMemBlock) heap; + return (memHeap_t *) blocks; } else return heap; } -static TMemBlock* SliceBlock(TMemBlock *p, - int startofs, int size, +static TMemBlock *SliceBlock(TMemBlock * p, + int startofs, int size, int reserved, int alignment) { TMemBlock *newblock; /* break left */ if (startofs > p->ofs) { - newblock = (TMemBlock*) drm_calloc(1, sizeof(TMemBlock), - DRM_MEM_DRIVER); + newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), + DRM_MEM_DRIVER); newblock->ofs = startofs; newblock->size = p->size - (startofs - p->ofs); newblock->free = 1; @@ -241,8 +238,8 @@ static TMemBlock* SliceBlock(TMemBlock *p, /* break right */ if (size < p->size) { - newblock = (TMemBlock*) drm_calloc(1, sizeof(TMemBlock), - DRM_MEM_DRIVER); + newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), + DRM_MEM_DRIVER); newblock->ofs = startofs + size; newblock->size = p->size - size; newblock->free = 1; @@ -258,37 +255,37 @@ static TMemBlock* SliceBlock(TMemBlock *p, return p; } -PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch) +PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch) { - int mask,startofs, endofs; + int mask, startofs, endofs; TMemBlock *p; - + if (heap == NULL || align2 < 0 || size <= 0) return NULL; - mask = (1 << align2)-1; + mask = (1 << align2) - 1; startofs = 0; - p = (TMemBlock *)heap; + p = (TMemBlock *) heap; while (p != NULL) { if (ISFREE(p)) { startofs = (p->ofs + mask) & ~mask; - if ( startofs < startSearch ) { + if (startofs < startSearch) { startofs = startSearch; } - endofs = startofs+size; - if (endofs <= (p->ofs+p->size)) + endofs = startofs + size; + if (endofs <= (p->ofs + p->size)) break; } p = p->next; } if (p == NULL) return NULL; - p = SliceBlock(p,startofs,size,0,mask+1); + p = SliceBlock(p, startofs, size, 0, mask + 1); p->heap = heap; return p; } -static __inline__ int Join2Blocks(TMemBlock *p) +static __inline__ int Join2Blocks(TMemBlock * p) { if (p->free && p->next && p->next->free) { TMemBlock *q = p->next; @@ -321,11 +318,11 @@ int mmFreeMem(PMemBlock b) p->free = 1; Join2Blocks(p); if (prev) - Join2Blocks(prev); + Join2Blocks(prev); return 0; } -int mmReserveMem(memHeap_t *heap, int offset,int size) +int mmReserveMem(memHeap_t * heap, int offset, int size) { int endofs; TMemBlock *p; @@ -334,10 +331,10 @@ int mmReserveMem(memHeap_t *heap, int offset,int size) return -1; endofs = offset + size; - p = (TMemBlock *)heap; + p = (TMemBlock *) heap; while (p && p->ofs <= offset) { - if (ISFREE(p) && endofs <= (p->ofs+p->size)) { - SliceBlock(p,offset,size,1,1); + if (ISFREE(p) && endofs <= (p->ofs + p->size)) { + SliceBlock(p, offset, size, 1, 1); return 0; } p = p->next; @@ -345,14 +342,14 @@ int mmReserveMem(memHeap_t *heap, int offset,int size) return -1; } -int mmFreeReserved(memHeap_t *heap, int offset) +int mmFreeReserved(memHeap_t * heap, int offset) { - TMemBlock *p,*prev; + TMemBlock *p, *prev; if (heap == NULL) return -1; - p = (TMemBlock *)heap; + p = (TMemBlock *) heap; prev = NULL; while (p != NULL && p->ofs != offset) { prev = p; @@ -369,14 +366,14 @@ int mmFreeReserved(memHeap_t *heap, int offset) return 0; } -void mmDestroy(memHeap_t *heap) +void mmDestroy(memHeap_t * heap) { - TMemBlock *p,*q; + TMemBlock *p, *q; if (heap == NULL) return; - p = (TMemBlock *)heap; + p = (TMemBlock *) heap; while (p != NULL) { q = p->next; drm_free(p, sizeof(TMemBlock), DRM_MEM_DRIVER); diff --git a/shared-core/sis_ds.h b/shared-core/sis_ds.h index bbd3fe1b..13e94b23 100644 --- a/shared-core/sis_ds.h +++ b/shared-core/sis_ds.h @@ -10,11 +10,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -22,10 +22,10 @@ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. - * + * * Authors: * Sung-Ching Lin - * + * */ #ifndef __SIS_DS_H__ @@ -50,11 +50,11 @@ typedef struct { } set_t; set_t *setInit(void); -int setAdd(set_t *set, ITEM_TYPE item); -int setDel(set_t *set, ITEM_TYPE item); -int setFirst(set_t *set, ITEM_TYPE *item); -int setNext(set_t *set, ITEM_TYPE *item); -int setDestroy(set_t *set); +int setAdd(set_t * set, ITEM_TYPE item); +int setDel(set_t * set, ITEM_TYPE item); +int setFirst(set_t * set, ITEM_TYPE * item); +int setNext(set_t * set, ITEM_TYPE * item); +int setDestroy(set_t * set); /* * GLX Hardware Device Driver common code @@ -73,9 +73,9 @@ int setDestroy(set_t *set); * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ @@ -83,7 +83,7 @@ int setDestroy(set_t *set); struct mem_block_t { struct mem_block_t *next; struct mem_block_t *heap; - int ofs,size; + int ofs, size; int align; int free:1; int reserved:1; @@ -109,15 +109,13 @@ static __inline__ void mmMarkReserved(PMemBlock b) b->reserved = 1; } -/* +/* * input: total size in bytes * return: a heap pointer if OK, NULL if error */ -memHeap_t *mmInit( int ofs, int size ); +memHeap_t *mmInit(int ofs, int size); -memHeap_t *mmAddRange( memHeap_t *heap, - int ofs, - int size ); +memHeap_t *mmAddRange(memHeap_t * heap, int ofs, int size); /* * Allocate 'size' bytes with 2^align2 bytes alignment, @@ -129,19 +127,19 @@ memHeap_t *mmAddRange( memHeap_t *heap, * startSearch = linear offset from start of heap to begin search * return: pointer to the allocated block, 0 if error */ -PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch ); +PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch); /* * Returns 1 if the block 'b' is part of the heap 'heap' */ -int mmBlockInHeap( PMemBlock heap, PMemBlock b ); +int mmBlockInHeap(PMemBlock heap, PMemBlock b); /* * Free block starts at offset * input: pointer to a block * return: 0 if OK, -1 if error */ -int mmFreeMem( PMemBlock b ); +int mmFreeMem(PMemBlock b); /* * Reserve 'size' bytes block start at offset @@ -150,15 +148,15 @@ int mmFreeMem( PMemBlock b ); * input: size, offset * output: 0 if OK, -1 if error */ -int mmReserveMem( memHeap_t *heap, int offset,int size ); -int mmFreeReserved( memHeap_t *heap, int offset ); +int mmReserveMem(memHeap_t * heap, int offset, int size); +int mmFreeReserved(memHeap_t * heap, int offset); /* * destroy MM */ -void mmDestroy( memHeap_t *mmInit ); +void mmDestroy(memHeap_t * mmInit); /* For debuging purpose. */ -void mmDumpMemInfo( memHeap_t *mmInit ); +void mmDumpMemInfo(memHeap_t * mmInit); -#endif /* __SIS_DS_H__ */ +#endif /* __SIS_DS_H__ */ diff --git a/shared-core/sis_mm.c b/shared-core/sis_mm.c index a895e0b8..7b0a2a43 100644 --- a/shared-core/sis_mm.c +++ b/shared-core/sis_mm.c @@ -10,11 +10,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -22,16 +22,12 @@ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. - * + * * Authors: * Sung-Ching Lin - * + * */ -#include "drmP.h" -#include "sis_drm.h" -#include "sis_drv.h" -#include "sis_ds.h" #if defined(__linux__) && defined(CONFIG_FB_SIS) #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) #include