From 753d4c39ff87f6b73dac72db4444b7627f39d2a9 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 13 Nov 2008 13:04:21 +1100 Subject: nv04-nv40: correct RAMHT size --- shared-core/nouveau_object.c | 7 +------ shared-core/nv04_instmem.c | 3 ++- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 5a44d41e..19325f37 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -141,13 +141,8 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) ref->channel, co, INSTANCE_RD(ramht, co/4)); co += 8; - if (co >= dev_priv->ramht_size) { - DRM_INFO("no space left after collision\n"); + if (co >= dev_priv->ramht_size) co = 0; - /* exit as it seems to cause crash with nouveau_demo and - * 0xdead0001 object */ - break; - } } while (co != ho); DRM_ERROR("RAMHT space exhausted. ch=%d\n", ref->channel); diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c index 804f9a75..7b58aa41 100644 --- a/shared-core/nv04_instmem.c +++ b/shared-core/nv04_instmem.c @@ -41,7 +41,8 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev) */ dev_priv->ramht_offset = 0x10000; dev_priv->ramht_bits = 9; - dev_priv->ramht_size = (1 << dev_priv->ramht_bits); + dev_priv->ramht_size = (1 << dev_priv->ramht_bits); /* nr entries */ + dev_priv->ramht_size *= 8; /* 2 32-bit values per entry in RAMHT */ DRM_DEBUG("RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset, dev_priv->ramht_size); -- cgit v1.2.3