From 78a4f5c1bc37cbc581191f47b8b19250bfb86c1e Mon Sep 17 00:00:00 2001
From: Jeremy Kolb <jkolb@brandeis.edu>
Date: Wed, 17 Jan 2007 08:46:59 -0500
Subject: nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.

Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.

Thanks to Carlos Martin for the help.
---
 shared-core/nouveau_fifo.c  |  2 +-
 shared-core/nouveau_irq.c   |  1 +
 shared-core/nouveau_state.c |  4 +-
 shared-core/nv30_graph.c    | 98 ++++-----------------------------------------
 4 files changed, 11 insertions(+), 94 deletions(-)

diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index 1e2870f1..8ea0564d 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -373,7 +373,7 @@ static void nouveau_nv30_context_init(drm_device_t *dev,
         /*
          * TODO: We need to put this somewhere...
          */
-        /* INSTANCE_WR(dev_priv->ctx_table, init->channel, grctx_inst); */
+        /*INSTANCE_WR(dev_priv->ctx_table, init->channel, grctx_inst);*/
         RAMFC_WR(DMA_SUBROUTINE,        init->put_base);
 }
 
diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index a92b8168..eca90833 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -330,6 +330,7 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
 				nouveau_nv10_context_switch(dev);
 				break;
 			case NV_20:
+			case NV_30:
 				nouveau_nv20_context_switch(dev);
 				break;
 			default:
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index f324c5ff..fb35ba74 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -96,8 +96,8 @@ int nouveau_firstopen(struct drm_device *dev)
 	/* FIXME: doesn't belong here, and have no idea what it's for.. */
 	if (dev_priv->card_type >= NV_40)
 		nv40_graph_init(dev);
-	else if (dev_priv->card_type >= NV_30) {
-	}
+	else if (dev_priv->card_type >= NV_30)
+		nv30_graph_init(dev);
 	else if (dev_priv->card_type >= NV_20)
 		nv20_graph_init(dev);
 	else if (dev_priv->card_type >= NV_10)
diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c
index dbc39490..94f6b3e8 100644
--- a/shared-core/nv30_graph.c
+++ b/shared-core/nv30_graph.c
@@ -11,7 +11,7 @@
  *  TODO: In the dump start seems to be 7654b0 while end is 76ac28.
  *  This is obviously not the correct size. 
  */
-#define NV30_GRCTX_SIZE (22392)
+#define NV30_GRCTX_SIZE (23840)
 
 /*TODO: deciper what each offset in the context represents. The below
  *      contexts are taken from dumps just after the 3D object is
@@ -21,7 +21,7 @@ static void nv30_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
 {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
 	int i;
-
+        
         INSTANCE_WR(ctx, 0x28/4,  0x10000000);
         INSTANCE_WR(ctx, 0x40c/4, 0x00000101);
         INSTANCE_WR(ctx, 0x420/4, 0x00000111);
@@ -101,8 +101,7 @@ static void nv30_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
 }
 
 
-int
-nv30_graph_context_create(drm_device_t *dev, int channel)
+int nv30_graph_context_create(drm_device_t *dev, int channel)
 {
 	drm_nouveau_private_t *dev_priv =
 		(drm_nouveau_private_t *)dev->dev_private;
@@ -128,97 +127,14 @@ nv30_graph_context_create(drm_device_t *dev, int channel)
 
 	/* Initialise default context values */
 	ctx_init(dev, chan->ramin_grctx);
+        
+        INSTANCE_WR(chan->ramin_grctx, 10, channel << 24); /* CTX_USER */
+        INSTANCE_WR(dev_priv->ctx_table, channel, nouveau_chip_instance_get(dev, chan->ramin_grctx));
 
 	return 0;
 }
-#if 0
-/* Save current context (from PGRAPH) into the channel's context
- *XXX: fails sometimes, not sure why..
- */
-void
-nv40_graph_context_save_current(drm_device_t *dev)
-{
-	drm_nouveau_private_t *dev_priv =
-		(drm_nouveau_private_t *)dev->dev_private;
-	uint32_t instance;
-	int i;
-
-	NV_WRITE(NV_PGRAPH_FIFO, 0);
-
-	instance = NV_READ(0x40032C) & 0xFFFFF;
-	if (!instance) {
-		NV_WRITE(NV_PGRAPH_FIFO, 1);
-		return;
-	}
-
-	NV_WRITE(0x400784, instance);
-	NV_WRITE(0x400310, NV_READ(0x400310) | 0x20);
-	NV_WRITE(0x400304, 1);
-	/* just in case, we don't want to spin in-kernel forever */
-	for (i=0; i<1000; i++) {
-		if (NV_READ(0x40030C) == 0)
-			break;
-	}
-	if (i==1000) {
-		DRM_ERROR("failed to save current grctx to ramin\n");
-		DRM_ERROR("instance = 0x%08x\n", NV_READ(0x40032C));
-		DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
-		NV_WRITE(NV_PGRAPH_FIFO, 1);
-		return;
-	}
-
-	NV_WRITE(NV_PGRAPH_FIFO, 1);
-}
 
-/* Restore the context for a specific channel into PGRAPH
- * XXX: fails sometimes.. not sure why
- */
-void
-nv40_graph_context_restore(drm_device_t *dev, int channel)
-{
-	drm_nouveau_private_t *dev_priv =
-		(drm_nouveau_private_t *)dev->dev_private;
-	struct nouveau_fifo *chan = &dev_priv->fifos[channel];
-	uint32_t instance;
-	int i;
-
-	instance = nouveau_chip_instance_get(dev, chan->ramin_grctx);
-
-	NV_WRITE(NV_PGRAPH_FIFO, 0);
-	NV_WRITE(0x400784, instance);
-	NV_WRITE(0x400310, NV_READ(0x400310) | 0x40);
-	NV_WRITE(0x400304, 1);
-	/* just in case, we don't want to spin in-kernel forever */
-	for (i=0; i<1000; i++) {
-		if (NV_READ(0x40030C) == 0)
-			break;
-	}
-	if (i==1000) {
-		DRM_ERROR("failed to restore grctx for ch%d to PGRAPH\n",
-				channel);
-		DRM_ERROR("instance = 0x%08x\n", instance);
-		DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
-		NV_WRITE(NV_PGRAPH_FIFO, 1);
-		return;
-	}
-
-
-	/* 0x40032C, no idea of it's exact function.  Could simply be a
-	 * record of the currently active PGRAPH context.  It's currently
-	 * unknown as to what bit 24 does.  The nv ddx has it set, so we will
-	 * set it here too.
-	 */
-	NV_WRITE(0x40032C, instance | 0x01000000);
-	/* 0x32E0 records the instance address of the active FIFO's PGRAPH
-	 * context.  If at any time this doesn't match 0x40032C, you will
-	 * recieve PGRAPH_INTR_CONTEXT_SWITCH
-	 */
-	NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, instance);
-	NV_WRITE(NV_PGRAPH_FIFO, 1);
-}
-#endif
-int
-nv30_graph_init(drm_device_t *dev)
+int nv30_graph_init(drm_device_t *dev)
 {
 	drm_nouveau_private_t *dev_priv =
 		(drm_nouveau_private_t *)dev->dev_private;
-- 
cgit v1.2.3


From bd0418cb01232d7529ecb0f515aa9b6d6804a3ac Mon Sep 17 00:00:00 2001
From: Dave Jones <davej@redhat.com>
Date: Thu, 18 Jan 2007 01:28:49 -0500
Subject: add missing quadro id

---
 shared-core/drm_pciids.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index 0b95fe76..54831576 100644
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -586,6 +586,7 @@
 0x10de 0x01d7 NV_44 "Quadro NVS 110M / GeForce Go 7300"
 0x10de 0x01d8 NV_44 "GeForce Go 7400"
 0x10de 0x01da NV_44 "Quadro NVS 110M"
+0x10de 0x01dc NV_44 "Quadro FX 350M"
 0x10de 0x01df NV_44 "GeForce 7300 GS"
 0x10de 0x01f0 NV_17|NV_NFORCE2 "GeForce4 MX - nForce GPU"
 0x10de 0x0200 NV_20 "GeForce3"
-- 
cgit v1.2.3


From ab72a7714e4e9b87cc93887d1978f1c533255566 Mon Sep 17 00:00:00 2001
From: Jeremy Kolb <jkolb@brandeis.edu>
Date: Thu, 18 Jan 2007 21:39:09 -0500
Subject: nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH
 switching.

---
 shared-core/nouveau_fifo.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index 8ea0564d..e80ba766 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -368,12 +368,7 @@ static void nouveau_nv30_context_init(drm_device_t *dev,
         RAMFC_WR(ACQUIRE_TIMESTAMP,     NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
         RAMFC_WR(ACQUIRE_TIMEOUT,       NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
         RAMFC_WR(SEMAPHORE,             NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
-        NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, grctx_inst); /* Misnomer.  Really a ptr to the grctx */
 
-        /*
-         * TODO: We need to put this somewhere...
-         */
-        /*INSTANCE_WR(dev_priv->ctx_table, init->channel, grctx_inst);*/
         RAMFC_WR(DMA_SUBROUTINE,        init->put_base);
 }
 
-- 
cgit v1.2.3


From a40de938fa5cf98f01d569e39fe3931d545c357a Mon Sep 17 00:00:00 2001
From: Jeremy Kolb <jkolb@brandeis.edu>
Date: Thu, 18 Jan 2007 21:39:36 -0500
Subject: nouveau: cleanup nv30_graph.c

---
 shared-core/nv30_graph.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c
index 94f6b3e8..a5f01ea5 100644
--- a/shared-core/nv30_graph.c
+++ b/shared-core/nv30_graph.c
@@ -8,7 +8,6 @@
 #include "nouveau_drm.h"
 
 /*
- *  TODO: In the dump start seems to be 7654b0 while end is 76ac28.
  *  This is obviously not the correct size. 
  */
 #define NV30_GRCTX_SIZE (23840)
-- 
cgit v1.2.3


From 4291df69bd03f71cbbe91b7b1ad82b580e1d362a Mon Sep 17 00:00:00 2001
From: Ben Skeggs <darktama@iinet.net.au>
Date: Sun, 14 Jan 2007 10:42:58 +1100
Subject: nouveau: re-add 6150 Go pciid (0x0244)

---
 shared-core/drm_pciids.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index 54831576..0d2639e1 100644
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -600,6 +600,7 @@
 0x10de 0x0221 NV_44 "GeForce 6200"
 0x10de 0x0240 NV_44 "GeForce 6150"
 0x10de 0x0242 NV_44 "GeForce 6100"
+0x10de 0x0244 NV_44 "GeForce 6150 Go"
 0x10de 0x0250 NV_25 "GeForce4 Ti 4600"
 0x10de 0x0251 NV_25 "GeForce4 Ti 4400"
 0x10de 0x0252 NV_25 "GeForce4 Ti"
-- 
cgit v1.2.3


From 19ba0749384994662e0d6167c70cc6fbd78eb0ff Mon Sep 17 00:00:00 2001
From: Ben Skeggs <darktama@iinet.net.au>
Date: Fri, 19 Jan 2007 15:41:51 +1100
Subject: nouveau: fix getparam from 32-bit client on 64-bit kernel

---
 shared-core/nouveau_drm.h | 1 +
 shared-core/nouveau_drv.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h
index 3f363192..0f11c43a 100644
--- a/shared-core/nouveau_drm.h
+++ b/shared-core/nouveau_drm.h
@@ -93,6 +93,7 @@ drm_nouveau_mem_free_t;
 #define NOUVEAU_GETPARAM_AGP_PHYSICAL    7
 typedef struct drm_nouveau_getparam {
 	unsigned int param;
+	unsigned int dummy;
 	uint64_t value;
 }
 drm_nouveau_getparam_t;
diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h
index 4978c476..522a8cf9 100644
--- a/shared-core/nouveau_drv.h
+++ b/shared-core/nouveau_drv.h
@@ -34,7 +34,7 @@
 
 #define DRIVER_MAJOR		0
 #define DRIVER_MINOR		0
-#define DRIVER_PATCHLEVEL	2
+#define DRIVER_PATCHLEVEL	3
 
 #define NOUVEAU_FAMILY   0x0000FFFF
 #define NOUVEAU_FLAGS    0xFFFF0000
-- 
cgit v1.2.3


From 7d4e6b1445d4c734f1dd6070ffa041c42e649e91 Mon Sep 17 00:00:00 2001
From: Zou Nan hai <nanhai.zou@intel.com>
Date: Wed, 24 Jan 2007 16:33:21 +0800
Subject: vblank interrupt fix

---
 shared-core/i915_drv.h |  6 ++++++
 shared-core/i915_irq.c | 11 ++++++++++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
index 98f58940..ef9f3638 100644
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@ -254,6 +254,12 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 #define I915REG_INT_ENABLE_R	0x020a0
 #define I915REG_INSTPM	        0x020c0
 
+#define I915REG_PIPEASTAT	0x70024
+#define I915REG_PIPEBSTAT	0x71024
+
+#define I915_VBLANK_INTERRUPT_ENABLE	(1UL<<17)
+#define I915_VBLANK_CLEAR		(1UL<<1)
+
 #define SRX_INDEX		0x3c4
 #define SRX_DATA		0x3c5
 #define SR01			1
diff --git a/shared-core/i915_irq.c b/shared-core/i915_irq.c
index 97723653..5ff87880 100644
--- a/shared-core/i915_irq.c
+++ b/shared-core/i915_irq.c
@@ -214,9 +214,12 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 	drm_device_t *dev = (drm_device_t *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	u16 temp;
+	u32 pipea_stats, pipeb_stats;
 
+	pipea_stats = I915_READ(I915REG_PIPEASTAT);
+	pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
+		
 	temp = I915_READ16(I915REG_INT_IDENTITY_R);
-
 	temp &= (dev_priv->irq_enable_reg | USER_INT_FLAG);
 
 #if 0
@@ -257,6 +260,12 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 
 		if (dev_priv->swaps_pending > 0)
 			drm_locked_tasklet(dev, i915_vblank_tasklet);
+		I915_WRITE(I915REG_PIPEASTAT, 
+			pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
+			I915_VBLANK_CLEAR);
+		I915_WRITE(I915REG_PIPEBSTAT,
+			pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
+			I915_VBLANK_CLEAR);
 	}
 
 	return IRQ_HANDLED;
-- 
cgit v1.2.3


From aa7266385e0af26b9225f7dba0643867ac4e231a Mon Sep 17 00:00:00 2001
From: Ben Skeggs <darktama@iinet.net.au>
Date: Thu, 25 Jan 2007 08:16:23 +1100
Subject: nouveau: always print nsource/nstatus regs on PGRAPH errors

---
 shared-core/nouveau_irq.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index eca90833..ac88b684 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -295,10 +295,10 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
 
 		nstatus = NV_READ(0x00400104);
 		nsource = NV_READ(0x00400108);
-		DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
+		DRM_ERROR("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
 
 		instance = NV_READ(0x00400158);
-		DRM_DEBUG("instance:0x%08x\n", instance);
+		DRM_ERROR("instance:0x%08x\n", instance);
 
 		address = NV_READ(0x400704);
 		data    = NV_READ(0x400708);
-- 
cgit v1.2.3


From 90ae39d2f07058dd128d2fb19ffad712ee75c9a0 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <darktama@iinet.net.au>
Date: Thu, 25 Jan 2007 11:11:01 +1100
Subject: nouveau: nv4c default context

---
 shared-core/nv40_graph.c | 112 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c
index 3e1b2f6f..00583cdc 100644
--- a/shared-core/nv40_graph.c
+++ b/shared-core/nv40_graph.c
@@ -11,6 +11,7 @@
 #define NV40_GRCTX_SIZE (175*1024)
 #define NV43_GRCTX_SIZE (70*1024)
 #define NV4A_GRCTX_SIZE (64*1024)
+#define NV4C_GRCTX_SIZE (25*1024)
 #define NV4E_GRCTX_SIZE (25*1024)
 
 /*TODO: deciper what each offset in the context represents. The below
@@ -389,6 +390,113 @@ static void nv4a_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
 		INSTANCE_WR(ctx, i/4, 0x3f800000);
 }
 
+
+static void nv4c_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
+{
+	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	int i;
+
+	INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx));
+	INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);
+	INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);
+	INSTANCE_WR(ctx, 0x00030/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);
+	INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);
+	INSTANCE_WR(ctx, 0x00128/4, 0x02008821);
+	INSTANCE_WR(ctx, 0x00158/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x0015c/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00160/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00164/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00168/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x0016c/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00170/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00174/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00178/4, 0x00000040);
+	INSTANCE_WR(ctx, 0x0017c/4, 0x00000040);
+	INSTANCE_WR(ctx, 0x00180/4, 0x00000040);
+	INSTANCE_WR(ctx, 0x00188/4, 0x00000040);
+	INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);
+	INSTANCE_WR(ctx, 0x00340/4, 0x00040000);
+	INSTANCE_WR(ctx, 0x00350/4, 0x55555555);
+	INSTANCE_WR(ctx, 0x00354/4, 0x55555555);
+	INSTANCE_WR(ctx, 0x00358/4, 0x55555555);
+	INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);
+	INSTANCE_WR(ctx, 0x00388/4, 0x00000008);
+	INSTANCE_WR(ctx, 0x0039c/4, 0x00001010);
+	INSTANCE_WR(ctx, 0x003d0/4, 0x00000111);
+	INSTANCE_WR(ctx, 0x003d4/4, 0x00080060);
+	INSTANCE_WR(ctx, 0x003f0/4, 0x00000080);
+	INSTANCE_WR(ctx, 0x003f4/4, 0xffff0000);
+	INSTANCE_WR(ctx, 0x003f8/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x0040c/4, 0x46400000);
+	INSTANCE_WR(ctx, 0x0041c/4, 0xffff0000);
+	INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000);
+	INSTANCE_WR(ctx, 0x0042c/4, 0x0fff0000);
+	INSTANCE_WR(ctx, 0x00434/4, 0x00011100);
+	for (i=0x00450; i<0x0048c; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x07ff0000);
+	INSTANCE_WR(ctx, 0x00498/4, 0x4b7fffff);
+	INSTANCE_WR(ctx, 0x004c0/4, 0x30201000);
+	INSTANCE_WR(ctx, 0x004c4/4, 0x70605040);
+	INSTANCE_WR(ctx, 0x004c8/4, 0xb8a89888);
+	INSTANCE_WR(ctx, 0x004cc/4, 0xf8e8d8c8);
+	INSTANCE_WR(ctx, 0x004e0/4, 0x40100000);
+	INSTANCE_WR(ctx, 0x004fc/4, 0x0000ffff);
+	INSTANCE_WR(ctx, 0x00530/4, 0x435185d6);
+	INSTANCE_WR(ctx, 0x00534/4, 0x2155b699);
+	INSTANCE_WR(ctx, 0x00538/4, 0xfedcba98);
+	INSTANCE_WR(ctx, 0x0053c/4, 0x00000098);
+	INSTANCE_WR(ctx, 0x0054c/4, 0xffffffff);
+	INSTANCE_WR(ctx, 0x00550/4, 0x00ff7000);
+	INSTANCE_WR(ctx, 0x00554/4, 0x0000ffff);
+	INSTANCE_WR(ctx, 0x00564/4, 0x00ff0000);
+	INSTANCE_WR(ctx, 0x0059c/4, 0x00ffff00);
+	for (i=0x005e0; i<=0x0061c; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00018488);
+	for (i=0x00620; i<=0x0065c; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00028202);
+	for (i=0x006a0; i<=0x006dc; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x0000aae4);
+	for (i=0x006e0; i<=0x0071c; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x01012000);
+	for (i=0x00720; i<=0x0075c; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00080008);
+	for (i=0x007a0; i<=0x007dc; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00100008);
+	for (i=0x00830; i<=0x0083c; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x0001bc80);
+	for (i=0x00840; i<=0x0084c; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00000202);
+	for (i=0x00860; i<=0x0086c; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00000008);
+	for (i=0x00880; i<=0x0088c; i+=4)
+		INSTANCE_WR(ctx, i/4, 0x00080008);
+	INSTANCE_WR(ctx, 0x008a0/4, 0x00000002);
+	INSTANCE_WR(ctx, 0x008d4/4, 0x00000020);
+	INSTANCE_WR(ctx, 0x008d8/4, 0x030c30c3);
+	INSTANCE_WR(ctx, 0x008dc/4, 0x00011001);
+	INSTANCE_WR(ctx, 0x008e8/4, 0x3e020200);
+	INSTANCE_WR(ctx, 0x008ec/4, 0x00ffffff);
+	INSTANCE_WR(ctx, 0x008f0/4, 0x0c103f00);
+	INSTANCE_WR(ctx, 0x008fc/4, 0x00040000);
+	INSTANCE_WR(ctx, 0x00934/4, 0x00008100);
+	INSTANCE_WR(ctx, 0x009c0/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00a04/4, 0x00001001);
+	INSTANCE_WR(ctx, 0x00a0c/4, 0x00000003);
+	INSTANCE_WR(ctx, 0x00a10/4, 0x00888001);
+	INSTANCE_WR(ctx, 0x00a74/4, 0x00000005);
+	INSTANCE_WR(ctx, 0x00a80/4, 0x0000ffff);
+	INSTANCE_WR(ctx, 0x00a9c/4, 0x00005555);
+	INSTANCE_WR(ctx, 0x00aa0/4, 0x00000001);
+	INSTANCE_WR(ctx, 0x00ad8/4, 0x00000001);
+	for (i=0x016a0; i<0x01718; i+=8)
+		INSTANCE_WR(ctx, i/4, 0x3f800000);
+	for (i=0x03460; i<0x05650; i+=24)
+		INSTANCE_WR(ctx, i/4, 0x00000001);
+	for (i=0x05660; i<0x05a50; i+=16)
+		INSTANCE_WR(ctx, i/4, 0x3f800000);
+}
+
 static void nv4e_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
 {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
@@ -519,6 +627,10 @@ nv40_graph_context_create(drm_device_t *dev, int channel)
 		ctx_size = NV4A_GRCTX_SIZE;
 		ctx_init = nv4a_graph_context_init;
 		break;
+	case 0x4c:
+		ctx_size = NV4C_GRCTX_SIZE;
+		ctx_init = nv4c_graph_context_init;
+		break;
 	case 0x4e:
 		ctx_size = NV4E_GRCTX_SIZE;
 		ctx_init = nv4e_graph_context_init;
-- 
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