| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2004-12-08 | (Stephane Marchesin, me) add hyperz support to radeon drm. Only fast z | Roland Scheidegger | |
| clear and z buffer compression are working correctly, hierarchical-z is not. | |||
| 2004-10-23 | Apply radeon r300 microcode patch to non-core | Dave Airlie | |
| 2004-08-17 | preparation patch for radeon permanent mapping registers/framebuffer makes | Dave Airlie | |
| dev_priv live always, and add AGP detection in kernel patch: radeon-pre-2.patch From: Jon Smirl | |||
| 2004-07-25 | sync up with current 2.6 kernel bk tree - mostly __user annotations | Dave Airlie | |
| 2004-05-18 | add R200_EMIT_RB3D_BLENDCOLOR state packet to support GL_EXT_blend_color, | Roland Scheidegger | |
| GL_EXT_blend_func_separate and GL_EXT_blend_equation_separate on r200 | |||
| 2004-04-10 | white space changes to align with kernel | Dave Airlie | |
| 2004-03-12 | Fixes need to clean up the mess I made with the mesa merge. This code | Jon Smirl | |
| allows the mesa drivers to use a single definition of the DRM sarea/IOCTLS located in the drm driver directory. Adjustments were made to the 2D drivers to not include these changes. Changes to the mesa copy of DRM were copied to the DRI copy. XFree86 bug: Reported by: Submitted by: Reviewed by: Obtained from: | |||
| 2003-11-04 | Memory layout transition: | Michel Daenzer | |
| the 2D driver initializes MC_FB_LOCATION and related registers sanely the DRM deduces the layout from these registers clients use the new SETPARAM ioctl to tell the DRM where they think the framebuffer is located in the card's address space the DRM uses all this information to check client state and fix it up if necessary This is a prerequisite for things like direct rendering with IGP chips and video capturing. | |||
| 2003-08-26 | Remove artificial PCI GART limitations, rename AGP to GART where | Michel Daenzer | |
| appropriate | |||
| 2003-08-08 | Added some information as to when (which DRM version) various queries were | Ian Romanick | |
| added. | |||
| 2003-06-10 | Texture rectangle support for r100 | Keith Whitwell | |
| 2003-05-20 | DRM part of Radeon DRI suspend/resume support (Charl Botha). | David Dawes | |
| 2003-04-30 | Merged texmem-0-0-1 | Ian Romanick | |
| 2003-04-22 | add more get_param queries for embedded project | Keith Whitwell | |
| 2003-02-21 | Merge from bsd-4-0-0-branch. | Eric Anholt | |
| 2003-02-03 | Fix size of VERTEX2 ioctl struct (Egbert Eich) | Keith Whitwell | |
| 2002-10-29 | updated e-mail addresses for Keith, Alan and Jens | Jens Owen | |
| 2002-10-29 | preserve CRTC{,2}_OFFSET_CNTL in 2D driver to avoid bad effects when | Michel Daenzer | |
| pageflipping after a mode switch take current page into account in AdjustFrame(); writing the CRTC offset via the CP was probably a bad idea as this can happen asynchronously, reverted take frame offset into account when flipping pages handle CRTC2 as well for pageflipping (untested) preserve GEN_INT_CNTL on mode switches to prevent interrupts from getting disabled | |||
| 2002-10-28 | merge from mesa-4-1-branch to get cube-map registers. bumped version to 1.7 | Brian Paul | |
| 2002-09-25 | change RADEON_PARAM_IRQ_ACTIVE to RADEON_PARAM_IRQ_NR | Michel Daenzer | |
| 2002-09-23 | merged r200-0-2-branch to trunk | Keith Whitwell | |
| 2002-08-26 | merged r200-0-1-branch | Keith Whitwell | |
| 2002-07-11 | Don't read scratch registers directly, obtain the values via the GET_PARAM | Michel Daenzer | |
| ioctl. The DRM reads them from memory addresses the chip writes to on updates. Fall back to reading the registers directly with an old DRM. (Tim Smith, cleanups by myself) | |||
| 2002-07-05 | merged bsd-3-0-0-branch | Alan Hourihane | |
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index : renesas/drm.git | |
| libdrm, cloned from git://anongit.freedesktop.org/mesa/drm | Laurent Pinchart |
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