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2008-07-15This is a modified version of Hong's patch from last month, with a fewHong Liu
modifications to make it work correctly on my test hardware (altered the backlight write function, made it enable the legacy backlight controller interrupts on mobile hardware, sorted the interrupt function so we don't get an excessive number of vblank interrupts). This lets the backlight keys on my T61 work properly, though there's a 750msec or so delay between the request and the brightness actually changing - this sounds awfully like the hardware spinning waiting for a status flag to become ready, but as far as I can tell they're all set correctly. If anyone can figure out what's wrong here, it'd be nice to know. Some of the functions are still stubs and just tell the hardware that the request was successful. These can be filled in as kernel modesetting gets integrated. I think it's worth getting this in anyway, since it's required for backlight control to work properly on some new platforms. Signed-off-by: Matthew Garrett <mjg@redhat.com>
2008-07-15drm: add fix for PAT on radeon with 2.6.26Dave Airlie
2008-07-11intel-gem: Add two new ioctls for managing tiling on objects.Eric Anholt
Various chips have exciting interactions between the CPU and the GPU's different ways of accessing interleaved memory, so we need some kernel assistance in determining how it works. Only fully tested on GM965 so far.
2008-07-08nouveau: interface changes for nv5x 3dBen Skeggs
2008-07-03i915: official name for GM45 chipsetZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
2008-07-01i915: only use tiled blits on 965+Jesse Barnes
When scheduled swaps occur, we need to blit between front & back buffers. I the buffers are tiled, we need to set the appropriate XY_SRC_COPY tile bit, only on 965 chips, since it will cause corruption on pre-965 (e.g. 945). Bug reported by and fix tested by Tomas Janousek <tomi@nomi.cz>. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-06-25nv50: when destroying a channel make sure it's not still current on PFIFOBen Skeggs
We won't get a PFIFO context switch when the same channel ID is recreated if the hw still thinks the channel is already active, which causes fun issues. Should allow X to be stopped and started without tearing down the entire card state in lastclose().
2008-06-24[intel] Get vblank pipe from irq_mask_reg instead of hardware enable regKeith Packard
With the interrupt enable/disable using only the mask register, it was wrong to use the enable register to detect which pipes had vblank detection turned on. Also, as we keep a local copy of the mask register around, and MSI machines smack the hardware during the interrupt handler, it is more efficient and more correct to use the local copy.
2008-06-24[intel] Create functions to enable/disable interruptsKeith Packard
This shares common code sequences for managing the interrupt register bits
2008-06-24i915: register definition & header file cleanupJesse Barnes
It would be nice if one day the DRM driver was the canonical source for register definitions and core macros. To that end, this patch cleans things up quite a bit, removing redundant definitions (some with different names referring to the same register) and generally tidying up the header file.
2008-06-24[intel-gem] Recover resources from wedged hardware.Keith Packard
Clean up queues, free objects. On the next entervt, unmark the hardware to let the user try again (presumably after resetting the chip). Someday we'll automatically recover...
2008-06-23nv50: oops, keep VRAM allocations aligned at 64KiB - that's our page size..Ben Skeggs
2008-06-23nv50: use same dma object for fb/tt accessBen Skeggs
We depend on the VM fully now for memory protection, separate DMA objects for VRAM and GART are unneccesary. However, until the next interface break (soon) a client can't depend on the objects being the same and must still call NV_OBJ_SET_DMA_* methods appropriately.
2008-06-23nouveau: allocate drm-use vram buffers from end of vram.Ben Skeggs
This avoids seeing garbage from engine setup etc before X gets around to pointing the CRTCs at a new scanout buffer. Not actually a noticable problem before G80 as PRAMIN is forced to the end of VRAM by the hardware already.
2008-06-21RADEON: 0x1002 0x5657 is actually an RV410Alex Deucher
See bug 14289
2008-06-21[intel] Use IMR instead of IER to pend interrupts during ISRKeith Packard
Noting that the interrupt mask register was more reliable than the interrupt enable register for managing interrupts in user_irq_on/user_irq_off, this patch replaces the remaining IER frobbing with IMR instead. The test which exposes IER related failures is: $ glxgears & glxgears & glxgears (reposition the glxgears windows away from the upper left corner) $ while :; do x11perf -rect100 -reps 800 -repeat 1; sleep 1; done & $ while :; do runoa; runet; done &
2008-06-21[intel] Count received interruptsKeith Packard
Another patch adds this to a /proc/dri file for debugging and monitoring.
2008-06-20[intel-gem] Add intel-specific /proc entries to help monitor gem operationKeith Packard
This adds gem_active, gem_flushing, gem_inactive, gem_request and gem_seqno entries to monitor gem operation and help debug issues.
2008-06-20[intel-gem] Use shmem_getpage instead of find_or_create_pageKeith Packard
find_or_create_page doesn't quite set up pages correctly; any newly created pages aren't hooked into the shmem object quite right; user space mmaps of those pages end up mapping pages full of zeros which then get written to the real pages inappropriately. This patch requires that the kernel export shmem_getpage.
2008-06-20[intel-gem] Add DRM_IOCTL_I915_GEM_SW_FINISH to flag CPU writesKeith Packard
When a software fallback has completed, usermode must notify the kernel so that any scanout buffers can be synchronized. This ioctl should be called whenever a fallback completes to flush CPU and chipset caches.
2008-06-20r300: fix warningDave Airlie
2008-06-18i915: Add support for Intel 4 series chipsetsZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
2008-06-16[linux] Use the device's irq for handler setup instead of stale dev->irq.Eric Anholt
This fixes registration when MSI is set up after the stub function fills in dev->irq. Otherwise /proc/interrupts would report attachment to the fasteoi interrupt. dev->irq is still exposed (and updated at IRQ setup) for the drivers that use it for whatever reason.
2008-06-15radeon: *really* fix screen corruption thanks to Lukasz KrotowskiJerome Glisse
2008-06-15radeon: actualy try to fix the corruptionJerome Glisse
2008-06-15radeon: fix screen corruption introduced by last patchJerome Glisse
2008-06-13[intel-gem] throttle based on frames rather than time. Reduces jitter.Keith Packard
Record the last execbuffer sequence for each client. Record that sequence in the throttle ioctl as the 'throttle sequence'. Wait for the last throttle sequence in the throttle ioctl.
2008-06-13[intel] Enable MSI for i915 IRQKeith Packard
2008-06-13[intel] Restructure irq to pend all work until after iir write.Keith Packard
The interrupt identity register must be writen before any work occurs lest we drop an interrupt on the floor. This patch just shuffles code around to make sure that IIR is written as early as possible.
2008-06-13[intel-gem] Use a delayed_work instead of a timer + work_structKeith Packard
We want request retirement to occur about once a second when the request queue is non-empty. This was done with a timer that queued a work_struct, using a delayed_work instead makes a lot more sense.
2008-06-13Fix i915_wait_irq in the presence of interrupt masking.Eric Anholt
In the short-circuit code for the breadcrumb already being new enough, we need to update the sarea_priv copy of the breadcrumb just as if we had waited. Otherwise userland error checking will notice that we returned too early based on its wrong information, and call wait_irq again (leading to spinning until someone else comes along and updates the sarea_priv). This bug was hidden when we had interrupt masking disabled, such as in master, since the interrupt handler would update sarea_priv.
2008-06-13[gem] Remove the interrupt handler for retiring requests.Eric Anholt
This was insufficient once we started masking interrupts to only when someone was waiting for them (and would thus retire requests themselves). It was replaced by the retire_timer.
2008-06-13radeon: bump driver date to know if lockup fix is inJerome Glisse
2008-06-13radeon: r345xx fixe hard lockupJerome Glisse
This patch should fixe hard lockup and convert them in softlockup (ie you can ssh the box but the gpu is busted and we are waiting in loop for it to come back to reason).
2008-06-12Don't clear USER_INTERRUPT if we're not handling it.Eric Anholt
This fixes a regression from commit d434b64f6a760d85295e32298a9a1f3624ee1b69 which could cause us to fail to wake up for user interrupts if we lost a race.
2008-06-11[gem] Another round of cleanups from checkpatch.plEric Anholt
2008-06-11RADEON: use DSTCACHE_CTLSTAT rather than RB2D_DSTCACHE_CTLSTATAlex Deucher
According to the hw guys, you should use DSTCACHE_CTLSTAT to flush the 2D dst cache rather than RB2D_DSTCACHE_CTLSTAT.
2008-06-11[gem] Move potentially device-specific ioctls to the intel driver.Eric Anholt
This is the create (may want location flags), pread/pwrite/mmap (performance tuning hints), and set_domain (will 32 bits be enough for everyone?) ioctls. Left in the generic set are just flink/open/close. The 2D driver must be updated for this change, and API but not ABI is broken for 3D. The driver version is bumped to mark this.
2008-06-10[intel] Fix BUG_ON trigger in irq masking if you did on/off with irqs disabled.Eric Anholt
2008-06-10[gem] Manage the ringbuffer from the kernel in the GEM case.Eric Anholt
This requires that the X Server use the execbuf interface for buffer submission, as it no longer has direct access to the ring. This is therefore a flag day for the gem interface. This also adds enter/leavevt ioctls for use by the X Server. These would get stubbed out in a modesetting implementation, but are required while in an environment where the device's state is only managed by the DRM while X has the VT.
2008-06-10xgixp: Remove dependency on TTM fencesIan Romanick
2008-06-09RADEON: Add untested support for RS400 chipsAlex Deucher
GART setup appears to work the same as RS480 chips. Also RC4xx chips are actually RS400 based, not RS480 based.
2008-06-09RADEON: switch IGP gart to use radeon_write_agp_base()Alex Deucher
2008-06-08Fix typo in i915_suspendRobert Noland
Reported by vehemens
2008-06-08I915 suspend/resume for FreeBSDRobert Noland
2008-06-09r300/r500: add hier-z regsDave Airlie
2008-06-06[intel] remove settable use_mi_batchbuffer_startKeith Packard
The driver can know what hardware requires MI_BATCH_BUFFER vs MI_BATCH_BUFFER_START; there's no reason to let user mode configure this.
2008-06-06[intel-gem] Use timers to retire requests periodically.Keith Packard
Without the user IRQ running constantly, there's no wakeup when the ring empties to go retire requests and free buffers. Use a 1 second timer to make that happen more often.
2008-06-06[intel] free the hardware status page at driver_unloadKeith Packard
This goes with the other hardware status page patch.
2008-06-06[intel-gem] Add explicit throttle ioctlKeith Packard
Instead of throttling and execbuffer time, have the application ask to throttle explicitly. This allows the throttle to happen less often, and without holding the DRM lock.