Age | Commit message (Collapse) | Author |
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The "channel" detect doesn't work on my nv40, but the rest
seems to produce sane info.
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git+ssh://marcheu@git.freedesktop.org/git/mesa/drm into nouveau-1
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- Do important card init in firstopen
- Give each channel it's own cmdbuf dma object
- Move RAMHT config state to the same place as RAMRO/RAMFC
- Make sure instance mem for objects is *after* RAM{FC,HT,RO}
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nouveau-1
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On X init, PFIFO and PGRAPH are reset to defaults. This causes the GPU to
loose the configuration done by the drm. Perhaps a CARD_INIT ioctl a proper
solution to having this problem again in the future..
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into nouveau-1
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Conflicts:
linux-core/Makefile.kernel
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The binary driver will screw up either it's init or shutdown, leaving the
screen(s) in an unusable state without this. Something important in there?
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Bump libdrm version number to 2.2.0
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This will come in very handy for tiled buffers on intel hardware.
Also add some padding to interface structures to allow future binary backwards
compatible changes.
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Conflicts:
linux-core/drmP.h
linux-core/drm_drv.c
linux-core/drm_irq.c
linux-core/drm_stub.c
shared-core/drm.h
shared-core/i915_drv.h
shared-core/i915_irq.c
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that is now handled by the memory accounting.
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active channel's state is saved to RAMFC before PFIFO gets clobbered.
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Fix up init and destruction code.
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bug 8662
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Ok, I lied before.. it was a fluke it worked and required magic to repeat it..
It actually helps to fill in RAMFC entries in the correct place.
The code also clears RAMIN entirely instead of just the hash-table.
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code a bit.
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nouveau-1
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they seem to screw up the PGRAPH state.
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vals). Ch 1 GET now advances, but no ctx_switch.
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Fix buffer bound caching policy changing, Allow
on-the-fly changing of caching policy on bound buffers if the hardware
supports it.
Allow drivers to use driver-specific AGP memory types for TTM AGP pages.
Will make AGP drivers much easier to migrate.
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convinced it's an initialization issue.
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Adapt for new functions in the 2.6.19 kernel.
Remove the ability to have multiple regions in one TTM.
This simplifies a lot of code.
Remove the ability to access TTMs from user space.
We don't need it anymore without ttm regions.
Don't change caching policy for evicted buffers. Instead change it only
when the buffer is accessed by the CPU (on the first page fault).
This tremendously speeds up eviction rates.
Current code is safe for kernels <= 2.6.14.
Should also be OK with 2.6.19 and above.
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Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet).
Removed the PFIFO_REINIT ioctl. I hope it's that a good idea...
Requires the upcoming commit to the DDX.
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r100/r200 as others might be unsafe (r300 already does this), and add checking for these we need but aren't safe. Check the RADEON_CP_INDX_BUFFER packet on both r200 and r300 as it isn't safe neither.
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mach64_state.c: convert the DRM_MACH64_BLIT ioctl to submit a pointer to
user-space memory rather than a DMA buffer index, similar to DRM_MACH64_VERTEX.
This change allows the DDX to map the DMA buffers read-only and eliminate a
security problem where a client can alter the contents of the DMA buffer after
submission to the DRM.
This change also affects the DRI/DRM interface. Performace-wise, it basically
affects PCI mode where I get a ~12% speedup for some Mesa demos I tested.
This is mainly due to eliminating an ioctl for allocating the DMA buffer.
mach64_dma.c: move the responsibility for allocating memory for the DMA ring
in PCI mode to the DDX.
This change affects the DDX/DRM interface and unifies a couple of PCI/AGP code
paths for ring memory in the DRM.
Bump the mach64 DRM version major and date.
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Add DRM_PCI_BUFFER_RO flag for mapping PCI DMA buffer read-only. An additional
flag is needed, since PCI DMA buffers do not have an associated map.
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