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2008-05-20[gem] Clean up active/inactive list handling using helper functions.Eric Anholt
Additionally, a boolean active field is added to indicate which list an object is on, rather than smashing last_rendering_cookie to 0 to show inactive. This will help with flush-reduction later on, and makes the code clearer.
2008-05-17r500: add more register ranges for Mesa driverDave Airlie
2008-05-15[gem] Hold dev->struct_mutex to protect structure data.Eric Anholt
2008-05-15[gem] Rename the GTT LRU lists to active (executing) and inactive (idle).Eric Anholt
2008-05-13RS4xx: separate out RS400 and RS480 IGP chipsAlex Deucher
RS400 (intel based IGP) and RS480 (AMD based IGP) have different MC and GART setups. Currently we only support RS480.
2008-05-12[GEM] Typo (and thinking) fixes in drm-gem.txt and doxygen.Eric Anholt
2008-05-12[intel] When polling for ring space, sleep for a lot longer (10ms)Keith Packard
If the ring is full, the engine will surely be running for more than 10ms.
2008-05-12RADEON: fix copy/pasto in last commitAlex Deucher
2008-05-12R3/4/5: init pipe setup in drmAlex Deucher
Similar (broken) code in mesa needs to be removed
2008-05-12RADEON: cleanup radeon_do_engine_reset()Alex Deucher
2008-05-12R300+: fixup pixcache flushAlex Deucher
2008-05-12RS4xx: fix MCIND index maskAlex Deucher
2008-05-12RADEON: write AGP_BASE_2 on chips that support itAlex Deucher
2008-05-12R300+: fixup PURGE/FLUSH macrosAlex Deucher
2008-05-12Radeon IGP: merge RS4xx/RS6xx gart setupAlex Deucher
2008-05-12Radeon IGP: wrap MCIND accessAlex Deucher
first step in merging rs4xx/rs6xx gart setup
2008-05-12Radeon IGP: clean up registers and magic numbersAlex Deucher
2008-05-11[GEM] Make pread/pwrite manage memory domains. No luck with movnti though.Keith Packard
pread and pwrite must update the memory domains to ensure consistency with the GPU. At some point, it should be possible to avoid clflush through this path, but that isn't working for me.
2008-05-10Merge commit 'anholt/drm-gem' into drm-gemKeith Packard
2008-05-10[intel-GEM] Clean up GEM ioctl naming.Keith Packard
Rename 'validate_entry' to 'exec_object', then clean up some field names in structures (renaming buffer_offset to just offset, for example).
2008-05-09GEM: Separate the LRU into execution list and LRU list.Eric Anholt
Now, the LRU list has objects that are completely done rendering and ready to kick out, while the execution list has things with active rendering, which have associated cookies and reference counts on them.
2008-05-09[gem] API cleanup. allocate->create unreference->close name->flinkKeith Packard
Make the API names a bit more consistent.
2008-05-08[intel-gem] Move domains to relocation records. add set_domain ioctl.Keith Packard
Domain information is about buffer relationships, not buffer contents. That means a relocation contains the domain information as it knows how the source buffer references the target buffer. This also adds the set_domain ioctl so that user space can move buffers to the cpu domain.
2008-05-07GEM: Extend cache domain stuff for 965.Eric Anholt
One of our MI_FLUSH bits is reserved on 965, being always implied, and there's a vertex cache that was forgotten.
2008-05-06[intel-GEM] ref count objects in gtt-lru.Keith Packard
If objects on the lru aren't ref counted, they'll get pulled from the gtt as soon as they are freed. This change does cause objects to get stuck in the gtt until they're forced out by new requests. The lru should get cleaned when the irq occurs.
2008-05-06Merge commit 'anholt/drm-gem' into drm-gemKeith Packard
2008-05-06Start coding up memory domainsKeith Packard
2008-05-06GEM: Use irq-based fencing rather than syncing and evicting every exec.Eric Anholt
2008-05-05Dump last batch buffer when hardware lockup is detected.Keith Packard
2008-05-05Monitor ACTHD register while polling for idle ring.Keith Packard
When batch buffers are executing, the ring may be stuck for a long time. Monitor the ACTHD pointer which will show if the execution engine is actually hung.
2008-05-05Remove some debug messages.Keith Packard
2008-05-05Correct execbuffer offset. Add memory barrier and chipset flush.Keith Packard
2008-05-05Add i915_dispatch_gem_execbuffer (broken).Keith Packard
This function submits a gem-based execbuffer to the ring. It doesn't work yet.
2008-05-05r500: add allowed range for us config/pixsizeDave Airlie
2008-05-02Add name/open ioctls, separate handle and pointer ref counts.Keith Packard
Names are just another unique integer set (from another idr object). Names are removed when the user refernces (handles) are all destroyed -- this required that handles for objects be counted separately from internal kernel references (so that we can tell when the handles are all gone).
2008-05-02Remove drm_driver argument to functions taking drm_gem_object.Keith Packard
Now that drm_gem_object has a drm_driver * in it, functions don't need both parameters.
2008-05-02Fix nouveau warning when returning pointers in uint64_t objects.Keith Packard
2008-05-01Add alignment to all aperture allocation requests.Keith Packard
When pinning buffers, or using execbuffer, allow the application to specify the necessary aperture allocation alignment constraints.
2008-05-01Fix gem ioctls to be 32/64-bit clean.Keith Packard
mixed 32/64 bit systems need 'special' help for ioctl where the user-space and kernel-space datatypes differ. Fixing the datatypes to be the same size, and align the same way for both 32 and 64-bit ppc and x86 environments will elimiante the need to have magic 32/64-bit ioctl translation code.
2008-05-01Make GEM object handles be nonzero.Eric Anholt
2008-05-01Remove _args from gem ioctl argument structure tags.Eric Anholt
2008-05-01Add pin/unpin object ioctls for gem.Eric Anholt
2008-05-01checkpoint: relocations support.Eric Anholt
2008-05-01checkpoint: gtt binding written.Eric Anholt
2008-05-01checkpoint: rename to GEM and a few more i915 bits.Eric Anholt
2008-05-02nv50: enable 0x400500 bit 0 after PGRAPH exception alsoBen Skeggs
No solid idea about what these 2 bits do, but nv50 can now survive a few PGRAPH exceptions just as nv40 does :)
2008-05-02nouveau: guard against channels potentially not having a context, fix nv50Ben Skeggs
2008-05-02nouveau: disable all card interrupts when unknown PFIFO IRQ occurs.Ben Skeggs
This is possibly temporary. I can trigger an unending IRQ storm on G8x in some circumstances, and have no idea how to handle that particular PFIFO exception correctly yet.
2008-05-02nouveau: restore original NV_PFIFO_CACHES_REASSIGN value in fifo handlerBen Skeggs
Doesn't fix any issue I've seen, but is a potential issue if a FIFO IRQ occurs during channel creation/takedown.
2008-05-02nouveau: gather nsource in trap_info()Ben Skeggs
The IRQ handling stuff really is a mess.. On the TODO :)