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2006-10-27Last minute changes to support multi-page size buffer offset alignments.Thomas Hellstrom
This will come in very handy for tiled buffers on intel hardware. Also add some padding to interface structures to allow future binary backwards compatible changes.
2006-10-19Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drmThomas Hellstrom
2006-10-18Merging drm-ttm-0-2-branchThomas Hellstrom
Conflicts: linux-core/drmP.h linux-core/drm_drv.c linux-core/drm_irq.c linux-core/drm_stub.c shared-core/drm.h shared-core/i915_drv.h shared-core/i915_irq.c
2006-10-17Remove max number of locked pages check and call, sinceThomas Hellstrom
that is now handled by the memory accounting.
2006-10-18Remove hack which delays activation of a additional channel. The previously ↵Ben Skeggs
active channel's state is saved to RAMFC before PFIFO gets clobbered.
2006-10-18Oops, we have more than 4 subchannels..Ben Skeggs
2006-10-17Useful output on a FIFO error interrupt.Ben Skeggs
2006-10-17typoBen Skeggs
2006-10-17Extend generality for more memory types.Thomas Hellstrom
Fix up init and destruction code.
2006-10-16dev->agp_buffer_map is not initialized for AGP DMA on savagesMichael Karcher
bug 8662
2006-10-17NV40: *Now* fifo ctx switching works for me..Ben Skeggs
Ok, I lied before.. it was a fluke it worked and required magic to repeat it.. It actually helps to fill in RAMFC entries in the correct place. The code also clears RAMIN entirely instead of just the hash-table.
2006-10-17NV40: FIFO context switching now WorksForMe(tm)Ben Skeggs
2006-10-17Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup ↵Ben Skeggs
code a bit.
2006-10-17Some info on NV40's RAMFCBen Skeggs
2006-10-15Merge branch 'master' of git://anongit.freedesktop.org/git/mesa/drm into ↵Stephane Marchesin
nouveau-1
2006-10-14Again more work on context switches. They work, sometimes. And when they do ↵Stephane Marchesin
they seem to screw up the PGRAPH state.
2006-10-14remove config.h from build no longer exists kbuild does itDave Airlie
2006-10-14Add the missing breaks.Stephane Marchesin
2006-10-13Fix the fifo context size on nv10, nv20 and nv30.Stephane Marchesin
2006-10-14Fix some randomness in activating a second channel on NV40 (odd GET/PUT ↵Ben Skeggs
vals). Ch 1 GET now advances, but no ctx_switch.
2006-10-12Oops.Stephane Marchesin
2006-10-12Still more work on the context switching code.Stephane Marchesin
2006-10-12Simplify the AGP backend interface somewhat.Thomas Hellstrom
Fix buffer bound caching policy changing, Allow on-the-fly changing of caching policy on bound buffers if the hardware supports it. Allow drivers to use driver-specific AGP memory types for TTM AGP pages. Will make AGP drivers much easier to migrate.
2006-10-12More work on the context switch code. Still doesn't work. I'm mostly ↵Stephane Marchesin
convinced it's an initialization issue.
2006-10-11Big update:Thomas Hellstrom
Adapt for new functions in the 2.6.19 kernel. Remove the ability to have multiple regions in one TTM. This simplifies a lot of code. Remove the ability to access TTMs from user space. We don't need it anymore without ttm regions. Don't change caching policy for evicted buffers. Instead change it only when the buffer is accessed by the CPU (on the first page fault). This tremendously speeds up eviction rates. Current code is safe for kernels <= 2.6.14. Should also be OK with 2.6.19 and above.
2006-10-11Context switching work.Stephane Marchesin
Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX.
2006-10-10only allow specific type-3 packets to pass the verifier instead of all for ↵Roland Scheidegger
r100/r200 as others might be unsafe (r300 already does this), and add checking for these we need but aren't safe. Check the RADEON_CP_INDX_BUFFER packet on both r200 and r300 as it isn't safe neither.
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #4.George Sapountzis
mach64_state.c: convert the DRM_MACH64_BLIT ioctl to submit a pointer to user-space memory rather than a DMA buffer index, similar to DRM_MACH64_VERTEX. This change allows the DDX to map the DMA buffers read-only and eliminate a security problem where a client can alter the contents of the DMA buffer after submission to the DRM. This change also affects the DRI/DRM interface. Performace-wise, it basically affects PCI mode where I get a ~12% speedup for some Mesa demos I tested. This is mainly due to eliminating an ioctl for allocating the DMA buffer. mach64_dma.c: move the responsibility for allocating memory for the DMA ring in PCI mode to the DDX. This change affects the DDX/DRM interface and unifies a couple of PCI/AGP code paths for ring memory in the DRM. Bump the mach64 DRM version major and date.
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #3.George Sapountzis
Add DRM_PCI_BUFFER_RO flag for mapping PCI DMA buffer read-only. An additional flag is needed, since PCI DMA buffers do not have an associated map.
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #2.George Sapountzis
Factor out from mach64_dma_dispatch_vertex() the code to reclaim an unsed buffer, in preperation for using it in mach64_dma_dispatch_blit() also.
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #1.George Sapountzis
Factor out from mach64_freelist_get() the code to reclaim a completed buffer, this is to improve readability for me.
2006-10-02Bug 6209: [mach64] AGP DMA buffers not mapped correctly.George Sapountzis
Map the DMA buffers from the same linear address as the vertex bufs. If dev->agp_buffer_token is not set, mach64 drm maps the DMA buffers from linear address 0x0.
2006-10-02Fix type of second argument to spin_lock_irqsave().Michel Dänzer
(cherry picked from f6238cf6244b32bd84e3d2819963d7f5473867c8 commit)
2006-10-02Fix type of second argument to spin_lock_irqsave().Michel Dänzer
2006-10-02drm_rmdraw: Declare id and idx as signed so testing for < 0 works as intended.Felix Kühling
(cherry picked from d58389968124191a546a14b42ef84edc224be23d commit)
2006-10-02drm_rmdraw: Declare id and idx as signed so testing for < 0 works as intended.Felix Kühling
2006-09-29Bump driver date.Thomas Hellstrom
2006-09-29i915: Only schedule vblank tasklet if there are scheduled swaps pending.Michel Dänzer
This fixes issues on X server startup with versions of xf86-video-intel that enable the IRQ before they have a context ID. (cherry picked from 7af93dd9849442270ec89cb4bbeef5bfd4f9e424 commit)
2006-09-29i915: Only initialize IRQ fields in postinstall, not the PIPE_SET ioctl.Michel Dänzer
Some other minor changes in preparation for actually disabling user interrupts.
2006-09-29i915: Bump minor again to differentiate from vsync changes.Michel Dänzer
2006-09-29i915: Avoid mis-counting vblank interrupts when they're only enabled for pipe A.Michel Dänzer
It looks like 'after a while', I915REG_INT_IDENTITY_R for some reason always has VSYNC_PIPEB_FLAG set in the interrupt handler, even though pipe B is disabled. So we only increase dev->vbl_received if the corresponding bit is also set in dev->vblank_pipe. (cherry picked from 881ba569929ceafd42e3c86228b0172099083d1d commit)
2006-09-29i915: Bump minor for swap scheduling ioctl and secondary vblank support.Michel Dänzer
(cherry picked from 2627131e5d0c8cd5e3f0db06451c2e7ae7569b1b commit)
2006-09-29i915_vblank_swap: Add support for DRM_VBLANK_NEXTONMISS.Michel Dänzer
(cherry picked from 0356fe260dcf80f6d2d20e3384f2a1f4ee7f5b30 commit)
2006-09-29Only return EBUSY after we've established we need to schedule a new swap.Michel Dänzer
(cherry picked from 50a0284a61d4415c0ebdb02decee76ef3115007a commit)
2006-09-29Core vsync: Add flag DRM_VBLANK_NEXTONMISS.Michel Dänzer
When this flag is set and the target sequence is missed, wait for the next vertical blank instead of returning immediately. (cherry picked from 89e323e4900af84cc33219ad24eb0b435a039d23 commit)
2006-09-29Fix 'sequence has passed' condition in i915_vblank_swap().Michel Dänzer
(cherry picked from 7f09f957d9a61ac107f8fd29128d7899a3e8a228 commit)
2006-09-29Add SAREA fileds for determining which pipe to sync window buffer swaps to.Michel Dänzer
(cherry picked from c2bdb76814755c9ac6e66a8815f23af0fe4f3a91 commit)
2006-09-29Make handling of dev_priv->vblank_pipe more robust.Michel Dänzer
Initialize it to default value if it hasn't been set by the X server yet. In i915_vblank_pipe_set(), only update dev_priv->vblank_pipe and call i915_enable_interrupt() if the argument passed from userspace is valid to avoid corrupting dev_priv->vblank_pipe on invalid arguments. (cherry picked from 87c57cba1a70221fc570b253bf3b24682ef6b894 commit)
2006-09-29DRM_I915_VBLANK_SWAP ioctl: Take drm_vblank_seq_type_t instead of pipe number.Michel Dänzer
Handle relative as well as absolute target sequence numbers. Return error if target sequence has already passed, so userspace can deal with this situation as it sees fit. On success, return the sequence number of the vertical blank when the buffer swap is expected to take place. Also add DRM_IOCTL_I915_VBLANK_SWAP definition for userspace code that may want to use ioctl() instead of drmCommandWriteRead(). (cherry picked from d5a0f107511e128658e2d5e15bd7e6215c507f29 commit)
2006-09-29Change first valid DRM drawable ID to be 1 instead of 0.Michel Dänzer
This makes it easier for userspace to know when it needs to allocate an ID. Also free drawable information memory when it's no longer needed. (cherry picked from df7551ef7334d728ec0371423661bb403d3e270a commit)
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