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RS400 (intel based IGP) and RS480 (AMD based IGP) have
different MC and GART setups. Currently we only support
RS480.
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into modesetting-101
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It would be nice if one day the DRM driver was the canonical source for
register definitions and core macros. To that end, this patch cleans
things up quite a bit, removing redundant definitions (some with
different names referring to the same register) and generally tidying up
the header file.
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In order to avoid recursive ->detect->interrupt->detect->interrupt->...
we need to disable TV hotplug interrupts in
intel_tv.c:intel_tv_detect_type. We also need to enable the TV interrupt
detection and hotplug sequence properly in i915_irq.c.
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If the ring is full, the engine will surely be running for more than 10ms.
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drm_crtc->fb may point to NULL, f.e X server will allocate a new fb
and assign it to the CRTC at startup, when X server exits, it will destroy
the allocated fb, making drm_crtc->fb points to NULL.
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moving modeset init code into one function and correct error
handling druing i915 init
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We need to alloc a hw status page bo for G33 if modeset is enabled since the 2D
driver can't alloc gfx memory when working in drm modeset.
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Similar (broken) code in mesa needs to be removed
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first step in merging rs4xx/rs6xx gart setup
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pread and pwrite must update the memory domains to ensure consistency with
the GPU. At some point, it should be possible to avoid clflush through this
path, but that isn't working for me.
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Rename 'validate_entry' to 'exec_object', then clean up some field names in
structures (renaming buffer_offset to just offset, for example).
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Now, the LRU list has objects that are completely done rendering and ready
to kick out, while the execution list has things with active rendering,
which have associated cookies and reference counts on them.
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Fixup workqueue creation error handling and make sure we destroy the queue on
unload.
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Map the VBIOS (and therefore VBT) at init time for use by various output
initialization routines.
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Make the API names a bit more consistent.
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Domain information is about buffer relationships, not buffer contents. That
means a relocation contains the domain information as it knows how the
source buffer references the target buffer.
This also adds the set_domain ioctl so that user space can move buffers to
the cpu domain.
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This reverts commit 2a78ad22647933aa8842d534bce6495ff93fbf76.
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patch from F9 tree
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Conflicts:
linux-core/Makefile.kernel
shared-core/i915_drv.h
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One of our MI_FLUSH bits is reserved on 965, being always implied, and there's
a vertex cache that was forgotten.
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If objects on the lru aren't ref counted, they'll get pulled from the gtt as
soon as they are freed. This change does cause objects to get stuck in the
gtt until they're forced out by new requests. The lru should get cleaned
when the irq occurs.
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When batch buffers are executing, the ring may be stuck for a long time.
Monitor the ACTHD pointer which will show if the execution engine is
actually hung.
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This function submits a gem-based execbuffer to the ring.
It doesn't work yet.
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Names are just another unique integer set (from another idr object).
Names are removed when the user refernces (handles) are all destroyed --
this required that handles for objects be counted separately from
internal kernel references (so that we can tell when the handles are all
gone).
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Now that drm_gem_object has a drm_driver * in it, functions don't need both
parameters.
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When pinning buffers, or using execbuffer, allow the application to specify
the necessary aperture allocation alignment constraints.
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mixed 32/64 bit systems need 'special' help for ioctl where the user-space
and kernel-space datatypes differ. Fixing the datatypes to be the same size,
and align the same way for both 32 and 64-bit ppc and x86 environments will
elimiante the need to have magic 32/64-bit ioctl translation code.
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