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AgeCommit message (Collapse)Author
2004-04-121. Added a PCI ID.Thomas Hellstrom
2. Big change to the XvMC part of the SAREA. OpenGL clients will not suffer from this, and via XvMC is still alpha. Needed to make future additions to XvMC (More decoders and overlays) possible. 3. Bumped version number to 1.3.0.
2004-04-12Add mach64 to the trunkDave Airlie
2004-04-10white space changes to align with kernelDave Airlie
2004-04-08fix build problemAlan Hourihane
2004-04-08fixes from Linux kernelDave Airlie
2004-03-23Merged via-1-2-0Thomas Hellstrom
2004-03-12Fixes need to clean up the mess I made with the mesa merge. This codeJon Smirl
allows the mesa drivers to use a single definition of the DRM sarea/IOCTLS located in the drm driver directory. Adjustments were made to the 2D drivers to not include these changes. Changes to the mesa copy of DRM were copied to the DRI copy. XFree86 bug: Reported by: Submitted by: Reviewed by: Obtained from:
2004-02-18Fix sisfb header location for 2.6 kernelsMichel Daenzer
Submitted by: Andrew Morton
2004-01-10Make sure that all state packets are handled inMichel Daenzer
radeon_check_and_fixup_packets() Fix state packet IDs of R200 cubic offsets
2004-01-10R200_PP_CUBIC_OFFSET_F1_[0-6] state packets only contain 5 offsets, not 6Michel Daenzer
(thanks to Andreas Stenglein for spotting this)
2003-12-16Don't ioremap the framebuffer area. The ioremapped area wasn't used byEric Anholt
anything, and took up valuable KVA. While I'm in the area, clean up BSD MTRR stuff some more. Suggested by: jonsmirl
2003-11-05- Tie the DRM to a specific device: setunique no longer succeeds when givenEric Anholt
a busid that doesn't correspond to the device the DRM is attached to. This is a breaking of backwards-compatibility only for the multiple-DRI-head case with X Servers that don't use interface 1.1. - Move irq_busid to drm_irq.h and make it only return the IRQ for the current device. Retains compatibility with previous X Servers, cleans up unnecessary code. This means no irq_busid on !__HAVE_IRQ, but can be changed if necessary. - Bump interface version to 1.2. This version when set signifies that the control ioctl should ignore the irq number passed in and enable the interrupt handler for the attached device. Otherwise it errors out when the passed-in irq is not equal to the device's. - Store the highest version the interface has been set to in the device. - Fix a recursion on DRM_LOCK in irq_uninstall on FreeBSD. This leaves irq_uninstall being done without the lock in some cases, but it was racey anyways.
2003-11-05__linux__ is spelled with a lowercase 'l'Eric Anholt
2003-11-05Repo-copy linux/drm/kernel/drm.h to shared/drm/kernel/drm.h and use it onEric Anholt
both Linux and *BSD.
2003-11-04Memory layout transition:Michel Daenzer
the 2D driver initializes MC_FB_LOCATION and related registers sanely the DRM deduces the layout from these registers clients use the new SETPARAM ioctl to tell the DRM where they think the framebuffer is located in the card's address space the DRM uses all this information to check client state and fix it up if necessary This is a prerequisite for things like direct rendering with IGP chips and video capturing.
2003-10-23- Introduce a new ioctl, DRM_IOCTL_SET_VERSION. This ioctl allows theEric Anholt
server or client to notify the DRM that it expects a certain version of the device dependent or device independent interface. If the major doesn't match or minor is too large, EINVAL is returned. A major of -1 means that the requestor doesn't care about that portion of the interface. The ioctl returns the actual versions in the same struct. - Introduce DRM DI interface version 1.1. If the server requests version 1.1, then the DRM sets the unique itself according to the busid of the device it probed, which may then be accessed as normal using getunique. - Request version 1.1 in libdrm's drmOpenByBusID, allowing the X Server to request based on a BusID. Introduce a wrapper for DRM_IOCTL_SET_VERSION and bump libdrm minor version. - Pass the busid in DRIScreenInit if libdrm can handle both a busid and name. This allows drmOpenByBusID to be used to find the DRM instead of just the driver name, which allows us in the future to tie a DRM more strongly to the device it probed to. Introduce a function DRICreatePCIBusID which creates a busid in the form pci:oooo:bb:dd.f similar to linux's pci_name() function. This matches the format used by the DRM in version 1.1. libdrm knows how to match both this format and the old PCI:b:d:f format. - Use the new DRICreatePCIBusID function in the *_dri.c to request the new, more exact busid format.
2003-10-17- Move IRQ functions from drm_dma.h to new drm_irq.h and disentangle themEric Anholt
from __HAVE_DMA. This will be useful for adding vblank sync support to sis and tdfx. Rename dma_service to irq_handler, which is more accurately what it is. - Fix the #if _HAVE_DMA_IRQ in radeon, r128, mga, i810, i830, gamma to have the right number of underscores. This may have been a problem in the case that the server died without doing its DRM_IOCTL_CONTROL to uninit.
2003-10-17- Converted Linux drivers to initialize DRM instances based on PCI IDs, notEric Anholt
just a single instance. Moved the PCI ID lists from <card>_drv.c in BSD to <card>.h. The PCI ID lists include a driver private field, which may be used by drivers for chip family or other information. Based on work by jonsmirl. - Make tdfx_drv.c and tdfx.h match other drivers. - Fixed up linking of sis shared files. Tested with Radeon and SiS on Linux and FreeBSD, including a Linux setup with 2 SiS cards in a machine, but only one head being used (with DRI)
2003-10-16Introduce COMMIT_RING() as in radeon DRM, stop using error prone writebackMichel Daenzer
for ring read pointer (Paul Mackerras) Get rid of some superfluous stuff, minor fixes
2003-10-16Try that again. It's a long.Eric Anholt
2003-10-16Debug printf format fix.Eric Anholt
2003-09-12resolve merge conflictsAlan Hourihane
2003-09-07Correct format in debug printfs (free is a pointer, not an int).Eric Anholt
2003-08-29Port the SiS DRM to FreeBSD. This includes the ability for the DRM toEric Anholt
allocate framebuffer memory without sisfb, and a new ioctl to be used by the X Server which tells the DRM what region of framebuffer memory to allocate from. Also fixes a possibility to panic the kernel I believe. Tested on linux with sisfb and FreeBSD (without sisfb) with new DRI only.
2003-08-26Remove artificial PCI GART limitations, rename AGP to GART whereMichel Daenzer
appropriate
2003-08-18Clean up Radeon DRI resume codeMichel Daenzer
2003-08-18Make r128_do_wait_for_idle static, as it's only used in this file.Eric Anholt
Noticed by: CScout
2003-08-18Remove an unnecessary #define __NO_VERSION__Eric Anholt
Noticed by: CScout
2003-08-12Whitespace cleanup from the pageflipping commit.Eric Anholt
2003-08-08Added some information as to when (which DRM version) various queries wereIan Romanick
added.
2003-07-29IRQ code cleanup suggested by Linus TorvaldsMichel Daenzer
i830 build fix
2003-07-26Degrade uninformative error message to debug message, as in other driversMichel Daenzer
2003-07-26Add Rage 128 pageflipping support, defaults to off. DRM version bump toEric Anholt
2.5.0. It still has some issues, including a flicker in the fps meter in tuxracer and I've seen garbage left behind after moving/closing windows. However, it's usable. Add the Option "EnablePageFlip" "YES" to use it.
2003-07-25Compile fixes for recent 2.5/2.6 Linux kernels. I hope this doesn't breakMichel Daenzer
the i830 driver or the BSDs. :)
2003-06-16Possibly fix stanford checker complaints about sareaKeith Whitwell
2003-06-10Texture rectangle support for r100Keith Whitwell
2003-06-09Revert bogus last commitKeith Whitwell
2003-06-09Don't activate blend fallbacks unless blending is enabledKeith Whitwell
2003-05-28Restore change to _DRM_VBLANK_SIGNAL from rev. 1.41, which was revertedLeif Delgass
with the documentation merge.
2003-05-27Merged DRM documentation.Jose Fonseca
2003-05-26Add support to r128 for MESA_ycbcr_texture (Ian Romanick, Leif Delgass)Leif Delgass
2003-05-20DRM part of Radeon DRI suspend/resume support (Charl Botha).David Dawes
2003-05-20Support for building DRM module on OpenBSD (Wilbern Cobb, Matthieu Herrb).David Dawes
(resync with XFree86 trunk)
2003-05-16Support AGP bridges where the AGP aperture can't be accessed directly byMichel Daenzer
the CPU (David Mosberger, Benjamin Herrenschmidt, myself, Paul Mackerras, Jeff Wiedemeier)
2003-05-06fix warning on machines where sizeof(drm_addr_t) != 4 (Randy Dunlap)Michel Daenzer
2003-04-30Merged texmem-0-0-1Ian Romanick
2003-04-26Remove the map argument from DRM_*MEMORYBARRIER. Not all of the uses ofEric Anholt
DRM_*MEMORYBARRIER we had were related to an MMIO space. This means arch-specific code on the BSDs, unfortunately. Also add DRM_MEMORYBARRIER() and change the DRM_READMEMORYBARRIER()s that used to be read/write barriers to it.
2003-04-26Ensure driver has been initialized (dev_private != NULL) before installingLeif Delgass
irq handler in DRM(irq_install). Modify all drivers to ensure irq handler is removed before cleanup and cleanup is called at takedown. Remove unused buffer private struct fields in i810, i830. Check for lock on init/cleanup in all drivers except i810/i830. The current DDX for i810 and i830 doesn't hold the lock on kernel init (FIXME?).
2003-04-22get rid of superfluous fields in struct drm_radeon_ring_bufferMichel Daenzer
use correct address for ring read pointer writeback (yes, we seem to have been running with bogus values for the ring read pointer, which 'worked' because the return value of radeon_wait_ring() is never checked and the ring usually never fills up)
2003-04-22Remove AGP dependency in kernel config for radeon, sis. RemoveLeif Delgass
PCIGART_ENABLED define for radeon, pcigart support now included for any arch.
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#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"

/*
 * NV20
 * -----
 * There are 3 families :
 * NV20 is 0x10de:0x020*
 * NV25/28 is 0x10de:0x025* / 0x10de:0x028*
 * NV2A is 0x10de:0x02A0
 *
 * NV30
 * -----
 * There are 3 families :
 * NV30/31 is 0x10de:0x030* / 0x10de:0x031*
 * NV34 is 0x10de:0x032*
 * NV35/36 is 0x10de:0x033* / 0x10de:0x034*
 *
 * Not seen in the wild, no dumps (probably NV35) :
 * NV37 is 0x10de:0x00fc, 0x10de:0x00fd
 * NV38 is 0x10de:0x0333, 0x10de:0x00fe
 *
 */

#define NV20_GRCTX_SIZE (3580*4)
#define NV25_GRCTX_SIZE (3529*4)
#define NV2A_GRCTX_SIZE (3500*4)

#define NV30_31_GRCTX_SIZE (24392)
#define NV34_GRCTX_SIZE    (18140)
#define NV35_36_GRCTX_SIZE (22396)

static void nv20_graph_context_init(struct drm_device *dev,
                                    struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;
/*
write32 #1 block at +0x00740adc NV_PRAMIN+0x40adc of 3369 (0xd29) elements:
+0x00740adc: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b3c: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bbc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bfc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

+0x00740c1c: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
+0x00740c3c: 00000000 00000000 00000000 44400000 00000000 00000000 00000000 00000000
+0x00740c5c: 00000000 00000000 00000000 00000000 00000000 00000000 00030303 00030303
+0x00740c7c: 00030303 00030303 00000000 00000000 00000000 00000000 00080000 00080000
+0x00740c9c: 00080000 00080000 00000000 00000000 01012000 01012000 01012000 01012000
+0x00740cbc: 000105b8 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008
+0x00740cdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740cfc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740d1c: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740d3c: 00000000 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000

+0x00740d5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d9c: 00000001 00000000 00004000 00000000 00000000 00000001 00000000 00040000
+0x00740dbc: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740ddc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
*/
	INSTANCE_WR(ctx, (0x33c/4)+0, 0xffff0000);
	INSTANCE_WR(ctx, (0x33c/4)+25, 0x0fff0000);
	INSTANCE_WR(ctx, (0x33c/4)+26, 0x0fff0000);
	INSTANCE_WR(ctx, (0x33c/4)+80, 0x00000101);
	INSTANCE_WR(ctx, (0x33c/4)+85, 0x00000111);
	INSTANCE_WR(ctx, (0x33c/4)+91, 0x44400000);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+102+i, 0x00030303);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+110+i, 0x00080000);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+116+i, 0x01012000);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+120+i, 0x000105b8);
	for (i = 0; i < 4; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+124+i, 0x00080008);
	for (i = 0; i < 16; ++i)
		INSTANCE_WR(ctx, (0x33c/4)+136+i, 0x07ff0000);
	INSTANCE_WR(ctx, (0x33c/4)+154, 0x4b7fffff);
	INSTANCE_WR(ctx, (0x33c/4)+176, 0x00000001);
	INSTANCE_WR(ctx, (0x33c/4)+178, 0x00004000);
	INSTANCE_WR(ctx, (0x33c/4)+181, 0x00000001);
	INSTANCE_WR(ctx, (0x33c/4)+183, 0x00040000);
	INSTANCE_WR(ctx, (0x33c/4)+184, 0x00010000);

/*
...
+0x0074239c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x007423bc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x007423dc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x007423fc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
...
+0x00742bdc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742bfc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742c1c: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742c3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
*/
	for (i = 0; i < 0x880; i += 0x10) {
		INSTANCE_WR(ctx, ((0x1c1c + i)/4)+0, 0x10700ff9);
		INSTANCE_WR(ctx, ((0x1c1c + i)/4)+1, 0x0436086c);
		INSTANCE_WR(ctx, ((0x1c1c + i)/4)+2, 0x000c001b);
	}

/*
write32 #1 block at +0x00742fbc NV_PRAMIN+0x42fbc of 4 (0x4) elements:
+0x00742fbc: 3f800000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x281c/4), 0x3f800000);

/*
write32 #1 block at +0x00742ffc NV_PRAMIN+0x42ffc of 12 (0xc) elements:
+0x00742ffc: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000
+0x0074301c: 00000000 bf800000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x285c/4)+0, 0x40000000);
	INSTANCE_WR(ctx, (0x285c/4)+1, 0x3f800000);
	INSTANCE_WR(ctx, (0x285c/4)+2, 0x3f000000);
	INSTANCE_WR(ctx, (0x285c/4)+4, 0x40000000);
	INSTANCE_WR(ctx, (0x285c/4)+5, 0x3f800000);
	INSTANCE_WR(ctx, (0x285c/4)+7, 0xbf800000);
	INSTANCE_WR(ctx, (0x285c/4)+9, 0xbf800000);

/*
write32 #1 block at +0x00742fcc NV_PRAMIN+0x42fcc of 4 (0x4) elements:
+0x00742fcc: 00000000 3f800000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x282c/4)+1, 0x3f800000);

/*
write32 #1 block at +0x0074302c NV_PRAMIN+0x4302c of 4 (0x4) elements:
+0x0074302c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743c9c NV_PRAMIN+0x43c9c of 4 (0x4) elements:
+0x00743c9c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743c3c NV_PRAMIN+0x43c3c of 8 (0x8) elements:
+0x00743c3c: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x349c/4)+2, 0x000fe000);

/*
write32 #1 block at +0x00743c6c NV_PRAMIN+0x43c6c of 4 (0x4) elements:
+0x00743c6c: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743ccc NV_PRAMIN+0x43ccc of 4 (0x4) elements:
+0x00743ccc: 00000000 000003f8 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x352c/4)+1, 0x000003f8);

/* write32 #1 NV_PRAMIN+0x43ce0 <- 0x002fe000 */
	INSTANCE_WR(ctx, 0x3540/4, 0x002fe000);

/*
write32 #1 block at +0x00743cfc NV_PRAMIN+0x43cfc of 8 (0x8) elements:
+0x00743cfc: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c
*/
	for (i = 0; i < 8; ++i)
		INSTANCE_WR(ctx, (0x355c/4)+i, 0x001c527c);
}

static void nv2a_graph_context_init(struct drm_device *dev,
                                    struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;

	INSTANCE_WR(ctx, 0x33c/4, 0xffff0000);
	for(i = 0x3a0; i< 0x3a8; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0fff0000);
	INSTANCE_WR(ctx, 0x47c/4, 0x00000101);
	INSTANCE_WR(ctx, 0x490/4, 0x00000111);
	INSTANCE_WR(ctx, 0x4a8/4, 0x44400000);
	for(i = 0x4d4; i< 0x4e4; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00030303);
	for(i = 0x4f4; i< 0x504; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00080000);
	for(i = 0x50c; i< 0x51c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x01012000);
	for(i = 0x51c; i< 0x52c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x000105b8);
	for(i = 0x52c; i< 0x53c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00080008);
	for(i = 0x55c; i< 0x59c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x07ff0000);
	INSTANCE_WR(ctx, 0x5a4/4, 0x4b7fffff);
	INSTANCE_WR(ctx, 0x5fc/4, 0x00000001);
	INSTANCE_WR(ctx, 0x604/4, 0x00004000);
	INSTANCE_WR(ctx, 0x610/4, 0x00000001);
	INSTANCE_WR(ctx, 0x618/4, 0x00040000);
	INSTANCE_WR(ctx, 0x61c/4, 0x00010000);

	for (i=0x1a9c; i <= 0x22fc/4; i += 32) {
		INSTANCE_WR(ctx, i/4    , 0x10700ff9);
		INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
		INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
	}

	INSTANCE_WR(ctx, 0x269c/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26b0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26dc/4, 0x40000000);
	INSTANCE_WR(ctx, 0x26e0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26e4/4, 0x3f000000);
	INSTANCE_WR(ctx, 0x26ec/4, 0x40000000);
	INSTANCE_WR(ctx, 0x26f0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x26f8/4, 0xbf800000);
	INSTANCE_WR(ctx, 0x2700/4, 0xbf800000);
	INSTANCE_WR(ctx, 0x3024/4, 0x000fe000);
	INSTANCE_WR(ctx, 0x30a0/4, 0x000003f8);
	INSTANCE_WR(ctx, 0x33fc/4, 0x002fe000);
	for(i = 0x341c; i< 0x343c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x001c527c);
}

static void nv25_graph_context_init(struct drm_device *dev,
                                    struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;
/*
write32 #1 block at +0x00740a7c NV_PRAMIN.GRCTX0+0x35c of 173 (0xad) elements:
+0x00740a7c: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740a9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740abc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740adc: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bbc: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
+0x00740bdc: 00000000 00000000 00000000 00000080 ffff0000 00000001 00000000 00000000
+0x00740bfc: 00000000 00000000 44400000 00000000 00000000 00000000 00000000 00000000
+0x00740c1c: 4b800000 00000000 00000000 00000000 00000000 00030303 00030303 00030303
+0x00740c3c: 00030303 00000000 00000000 00000000 00000000 00080000 00080000 00080000
+0x00740c5c: 00080000 00000000 00000000 01012000 01012000 01012000 01012000 000105b8

+0x00740c7c: 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 00000000
+0x00740c9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 07ff0000
+0x00740cbc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740cdc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 00000000
+0x00740cfc: 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d1c: 00000000 00000000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x35c/4)+0, 0xffff0000);
	INSTANCE_WR(ctx, (0x35c/4)+25, 0x0fff0000);
	INSTANCE_WR(ctx, (0x35c/4)+26, 0x0fff0000);
	INSTANCE_WR(ctx, (0x35c/4)+80, 0x00000101);
	INSTANCE_WR(ctx, (0x35c/4)+85, 0x00000111);
	INSTANCE_WR(ctx, (0x35c/4)+91, 0x00000080);
	INSTANCE_WR(ctx, (0x35c/4)+92, 0xffff0000);
	INSTANCE_WR(ctx, (0x35c/4)+93, 0x00000001);
	INSTANCE_WR(ctx, (0x35c/4)+98, 0x44400000);
	INSTANCE_WR(ctx, (0x35c/4)+104, 0x4b800000);
	INSTANCE_WR(ctx, (0x35c/4)+109, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+110, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+111, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+112, 0x00030303);
	INSTANCE_WR(ctx, (0x35c/4)+117, 0x00080000);
	INSTANCE_WR(ctx, (0x35c/4)+118, 0x00080000);
	INSTANCE_WR(ctx, (0x35c/4)+119, 0x00080000);
	INSTANCE_WR(ctx, (0x35c/4)+120, 0x00080000);
	INSTANCE_WR(ctx, (0x35c/4)+123, 0x01012000);
	INSTANCE_WR(ctx, (0x35c/4)+124, 0x01012000);
	INSTANCE_WR(ctx, (0x35c/4)+125, 0x01012000);
	INSTANCE_WR(ctx, (0x35c/4)+126, 0x01012000);
	INSTANCE_WR(ctx, (0x35c/4)+127, 0x000105b8);
	INSTANCE_WR(ctx, (0x35c/4)+128, 0x000105b8);
	INSTANCE_WR(ctx, (0x35c/4)+129, 0x000105b8);
	INSTANCE_WR(ctx, (0x35c/4)+130, 0x000105b8);
	INSTANCE_WR(ctx, (0x35c/4)+131, 0x00080008);
	INSTANCE_WR(ctx, (0x35c/4)+132, 0x00080008);
	INSTANCE_WR(ctx, (0x35c/4)+133, 0x00080008);
	INSTANCE_WR(ctx, (0x35c/4)+134, 0x00080008);
	for (i=0; i<16; ++i)
		INSTANCE_WR(ctx, (0x35c/4)+143+i, 0x07ff0000);
	INSTANCE_WR(ctx, (0x35c/4)+161, 0x4b7fffff);

/*
write32 #1 block at +0x00740d34 NV_PRAMIN.GRCTX0+0x614 of 3136 (0xc40) elements:
+0x00740d34: 00000000 00000000 00000000 00000080 30201000 70605040 b0a09080 f0e0d0c0
+0x00740d54: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d74: 00000000 00000000 00000000 00000000 00000001 00000000 00004000 00000000
+0x00740d94: 00000000 00000001 00000000 00040000 00010000 00000000 00000000 00000000
+0x00740db4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
+0x00742214: 00000000 00000000 00000000 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742234: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742254: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742274: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
...
+0x00742a34: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a54: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a74: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a94: 10700ff9 0436086c 000c001b 00000000 00000000 00000000 00000000 00000000
+0x00742ab4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00742ad4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x614/4)+3, 0x00000080);
	INSTANCE_WR(ctx, (0x614/4)+4, 0x30201000);
	INSTANCE_WR(ctx, (0x614/4)+5, 0x70605040);
	INSTANCE_WR(ctx, (0x614/4)+6, 0xb0a09080);
	INSTANCE_WR(ctx, (0x614/4)+7, 0xf0e0d0c0);
	INSTANCE_WR(ctx, (0x614/4)+20, 0x00000001);
	INSTANCE_WR(ctx, (0x614/4)+22, 0x00004000);
	INSTANCE_WR(ctx, (0x614/4)+25, 0x00000001);
	INSTANCE_WR(ctx, (0x614/4)+27, 0x00040000);
	INSTANCE_WR(ctx, (0x614/4)+28, 0x00010000);
	for (i=0; i < 0x880/4; i+=4) {
		INSTANCE_WR(ctx, (0x1b04/4)+i+0, 0x10700ff9);
		INSTANCE_WR(ctx, (0x1b04/4)+i+1, 0x0436086c);
		INSTANCE_WR(ctx, (0x1b04/4)+i+2, 0x000c001b);
	}

/*
write32 #1 block at +0x00742e24 NV_PRAMIN.GRCTX0+0x2704 of 4 (0x4) elements:
+0x00742e24: 3f800000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x2704/4), 0x3f800000);

/*
write32 #1 block at +0x00742e64 NV_PRAMIN.GRCTX0+0x2744 of 12 (0xc) elements:
+0x00742e64: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000
+0x00742e84: 00000000 bf800000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x2744/4)+0, 0x40000000);
	INSTANCE_WR(ctx, (0x2744/4)+1, 0x3f800000);
	INSTANCE_WR(ctx, (0x2744/4)+2, 0x3f000000);
	INSTANCE_WR(ctx, (0x2744/4)+4, 0x40000000);
	INSTANCE_WR(ctx, (0x2744/4)+5, 0x3f800000);
	INSTANCE_WR(ctx, (0x2744/4)+7, 0xbf800000);
	INSTANCE_WR(ctx, (0x2744/4)+9, 0xbf800000);

/*
write32 #1 block at +0x00742e34 NV_PRAMIN.GRCTX0+0x2714 of 4 (0x4) elements:
+0x00742e34: 00000000 3f800000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x2714/4)+1, 0x3f800000);

/*
write32 #1 block at +0x00742e94 NV_PRAMIN.GRCTX0+0x2774 of 4 (0x4) elements:
+0x00742e94: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743804 NV_PRAMIN.GRCTX0+0x30e4 of 4 (0x4) elements:
+0x00743804: 00000000 00000000 00000000 00000000
write32 #1 block at +0x007437a4 NV_PRAMIN.GRCTX0+0x3084 of 8 (0x8) elements:
+0x007437a4: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x3084/4)+2, 0x000fe000);

/*
write32 #1 block at +0x007437d4 NV_PRAMIN.GRCTX0+0x30b4 of 4 (0x4) elements:
+0x007437d4: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743824 NV_PRAMIN.GRCTX0+0x3104 of 4 (0x4) elements:
+0x00743824: 00000000 000003f8 00000000 00000000
*/
	INSTANCE_WR(ctx, (0x3104/4)+1, 0x000003f8);

/* write32 #1 NV_PRAMIN.GRCTX0+0x3468 <- 0x002fe000 */
	INSTANCE_WR(ctx, 0x3468/4, 0x002fe000);

/*
write32 #1 block at +0x00743ba4 NV_PRAMIN.GRCTX0+0x3484 of 8 (0x8) elements:
+0x00743ba4: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c
*/
	for (i=0; i<8; ++i)
		INSTANCE_WR(ctx, (0x3484/4)+i, 0x001c527c);
}

static void nv30_31_graph_context_init(struct drm_device *dev,
                                       struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;

	INSTANCE_WR(ctx, 0x410/4, 0x00000101);
	INSTANCE_WR(ctx, 0x424/4, 0x00000111);
	INSTANCE_WR(ctx, 0x428/4, 0x00000060);
	INSTANCE_WR(ctx, 0x444/4, 0x00000080);
	INSTANCE_WR(ctx, 0x448/4, 0xffff0000);
	INSTANCE_WR(ctx, 0x44c/4, 0x00000001);
	INSTANCE_WR(ctx, 0x460/4, 0x44400000);
	INSTANCE_WR(ctx, 0x48c/4, 0xffff0000);
	for(i = 0x4e0; i< 0x4e8; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0fff0000);
	INSTANCE_WR(ctx, 0x4ec/4, 0x00011100);
	for(i = 0x508; i< 0x548; i += 4)
		INSTANCE_WR(ctx, i/4, 0x07ff0000);
	INSTANCE_WR(ctx, 0x550/4, 0x4b7fffff);
	INSTANCE_WR(ctx, 0x58c/4, 0x00000080);
	INSTANCE_WR(ctx, 0x590/4, 0x30201000);
	INSTANCE_WR(ctx, 0x594/4, 0x70605040);
	INSTANCE_WR(ctx, 0x598/4, 0xb8a89888);
	INSTANCE_WR(ctx, 0x59c/4, 0xf8e8d8c8);
	INSTANCE_WR(ctx, 0x5b0/4, 0xb0000000);
	for(i = 0x600; i< 0x640; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00010588);
	for(i = 0x640; i< 0x680; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00030303);
	for(i = 0x6c0; i< 0x700; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0008aae4);
	for(i = 0x700; i< 0x740; i += 4)
		INSTANCE_WR(ctx, i/4, 0x01012000);
	for(i = 0x740; i< 0x780; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00080008);
	INSTANCE_WR(ctx, 0x85c/4, 0x00040000);
	INSTANCE_WR(ctx, 0x860/4, 0x00010000);
	for(i = 0x864; i< 0x874; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00040004);
	for(i = 0x1f18; i<= 0x3088 ; i+= 16) {
		INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9);
		INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
		INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
	}
	for(i = 0x30b8; i< 0x30c8; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0000ffff);
	INSTANCE_WR(ctx, 0x344c/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x3808/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x381c/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x3848/4, 0x40000000);
	INSTANCE_WR(ctx, 0x384c/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x3850/4, 0x3f000000);
	INSTANCE_WR(ctx, 0x3858/4, 0x40000000);
	INSTANCE_WR(ctx, 0x385c/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x3864/4, 0xbf800000);
	INSTANCE_WR(ctx, 0x386c/4, 0xbf800000);

	/* nv30gl stuff */
	for (i=0; i<8; i++) {
		INSTANCE_WR(ctx, (0x4dfc/4)+i, 0x001c527d);
	}
	INSTANCE_WR(ctx, 0x4e3c/4, 0x001c527c);
/* these ones make dma fifo hang
	INSTANCE_WR(ctx, 0x567c/4, 0x000a0000);
	INSTANCE_WR(ctx, 0x0878/4, 0x01000000);
	INSTANCE_WR(ctx, 0x02f4/4, 0x0001ffff);

	INSTANCE_WR(ctx, 0x0028/4, INSTANCE_RD(ctx, 0x0028/4) | 1);
*/
}

static void nv34_graph_context_init(struct drm_device *dev,
                                    struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;

	INSTANCE_WR(ctx, 0x40c/4, 0x01000101);
	INSTANCE_WR(ctx, 0x420/4, 0x00000111);
	INSTANCE_WR(ctx, 0x424/4, 0x00000060);
	INSTANCE_WR(ctx, 0x440/4, 0x00000080);
	INSTANCE_WR(ctx, 0x444/4, 0xffff0000);
	INSTANCE_WR(ctx, 0x448/4, 0x00000001);
	INSTANCE_WR(ctx, 0x45c/4, 0x44400000);
	INSTANCE_WR(ctx, 0x480/4, 0xffff0000);
	for(i = 0x4d4; i< 0x4dc; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0fff0000);
	INSTANCE_WR(ctx, 0x4e0/4, 0x00011100);
	for(i = 0x4fc; i< 0x53c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x07ff0000);
	INSTANCE_WR(ctx, 0x544/4, 0x4b7fffff);
	INSTANCE_WR(ctx, 0x57c/4, 0x00000080);
	INSTANCE_WR(ctx, 0x580/4, 0x30201000);
	INSTANCE_WR(ctx, 0x584/4, 0x70605040);
	INSTANCE_WR(ctx, 0x588/4, 0xb8a89888);
	INSTANCE_WR(ctx, 0x58c/4, 0xf8e8d8c8);
	INSTANCE_WR(ctx, 0x5a0/4, 0xb0000000);
	for(i = 0x5f0; i< 0x630; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00010588);
	for(i = 0x630; i< 0x670; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00030303);
	for(i = 0x6b0; i< 0x6f0; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0008aae4);
	for(i = 0x6f0; i< 0x730; i += 4)
		INSTANCE_WR(ctx, i/4, 0x01012000);
	for(i = 0x730; i< 0x770; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00080008);
	INSTANCE_WR(ctx, 0x850/4, 0x00040000);
	INSTANCE_WR(ctx, 0x854/4, 0x00010000);
	for(i = 0x858; i< 0x868; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00040004);
	for(i = 0x15ac; i<= 0x271c ; i+= 16) {
		INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9);
		INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
		INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
	}
	for(i = 0x274c; i< 0x275c; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0000ffff);
	INSTANCE_WR(ctx, 0x2ae0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x2e9c/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x2eb0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x2edc/4, 0x40000000);
	INSTANCE_WR(ctx, 0x2ee0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x2ee4/4, 0x3f000000);
	INSTANCE_WR(ctx, 0x2eec/4, 0x40000000);
	INSTANCE_WR(ctx, 0x2ef0/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x2ef8/4, 0xbf800000);
	INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000);
}

static void nv35_36_graph_context_init(struct drm_device *dev,
                                       struct nouveau_gpuobj *ctx)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i;

	INSTANCE_WR(ctx, 0x40c/4, 0x00000101);
	INSTANCE_WR(ctx, 0x420/4, 0x00000111);
	INSTANCE_WR(ctx, 0x424/4, 0x00000060);
	INSTANCE_WR(ctx, 0x440/4, 0x00000080);
	INSTANCE_WR(ctx, 0x444/4, 0xffff0000);
	INSTANCE_WR(ctx, 0x448/4, 0x00000001);
	INSTANCE_WR(ctx, 0x45c/4, 0x44400000);
	INSTANCE_WR(ctx, 0x488/4, 0xffff0000);
	for(i = 0x4dc; i< 0x4e4; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0fff0000);
	INSTANCE_WR(ctx, 0x4e8/4, 0x00011100);
	for(i = 0x504; i< 0x544; i += 4)
		INSTANCE_WR(ctx, i/4, 0x07ff0000);
	INSTANCE_WR(ctx, 0x54c/4, 0x4b7fffff);
	INSTANCE_WR(ctx, 0x588/4, 0x00000080);
	INSTANCE_WR(ctx, 0x58c/4, 0x30201000);
	INSTANCE_WR(ctx, 0x590/4, 0x70605040);
	INSTANCE_WR(ctx, 0x594/4, 0xb8a89888);
	INSTANCE_WR(ctx, 0x598/4, 0xf8e8d8c8);
	INSTANCE_WR(ctx, 0x5ac/4, 0xb0000000);
	for(i = 0x604; i< 0x644; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00010588);
	for(i = 0x644; i< 0x684; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00030303);
	for(i = 0x6c4; i< 0x704; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0008aae4);
	for(i = 0x704; i< 0x744; i += 4)
		INSTANCE_WR(ctx, i/4, 0x01012000);
	for(i = 0x744; i< 0x784; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00080008);
	INSTANCE_WR(ctx, 0x860/4, 0x00040000);
	INSTANCE_WR(ctx, 0x864/4, 0x00010000);
	for(i = 0x868; i< 0x878; i += 4)
		INSTANCE_WR(ctx, i/4, 0x00040004);
	for(i = 0x1f1c; i<= 0x308c ; i+= 16) {
		INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9);
		INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
		INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
	}
	for(i = 0x30bc; i< 0x30cc; i += 4)
		INSTANCE_WR(ctx, i/4, 0x0000ffff);
	INSTANCE_WR(ctx, 0x3450/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x380c/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x3820/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x384c/4, 0x40000000);
	INSTANCE_WR(ctx, 0x3850/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x3854/4, 0x3f000000);
	INSTANCE_WR(ctx, 0x385c/4, 0x40000000);
	INSTANCE_WR(ctx, 0x3860/4, 0x3f800000);
	INSTANCE_WR(ctx, 0x3868/4, 0xbf800000);
	INSTANCE_WR(ctx, 0x3870/4, 0xbf800000);
}

int nv20_graph_create_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
	unsigned int ctx_size;
	unsigned int idoffs = 0x28/4;
	int ret;

	switch (dev_priv->chipset) {
	case 0x20:
		ctx_size = NV20_GRCTX_SIZE;
		ctx_init = nv20_graph_context_init;
		idoffs = 0;
		break;
	case 0x25:
	case 0x28:
		ctx_size = NV25_GRCTX_SIZE;
		ctx_init = nv25_graph_context_init;
		break;
	case 0x2a:
		ctx_size = NV2A_GRCTX_SIZE;
		ctx_init = nv2a_graph_context_init;
		idoffs = 0;
		break;
	case 0x30:
	case 0x31:
		ctx_size = NV30_31_GRCTX_SIZE;
		ctx_init = nv30_31_graph_context_init;
		break;
	case 0x34:
		ctx_size = NV34_GRCTX_SIZE;
		ctx_init = nv34_graph_context_init;
		break;
	case 0x35:
	case 0x36:
		ctx_size = NV35_36_GRCTX_SIZE;
		ctx_init = nv35_36_graph_context_init;
		break;
	default:
		ctx_size = 0;
		ctx_init = nv35_36_graph_context_init;
		DRM_ERROR("Please contact the devs if you want your NV%x"
		          " card to work\n", dev_priv->chipset);
		return -ENOSYS;
		break;
	}

	if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16,
					  NVOBJ_FLAG_ZERO_ALLOC,
					  &chan->ramin_grctx)))
		return ret;

	/* Initialise default context values */