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2008-09-26radeon: make atom on r4xx a module optionAlex Deucher
default is legacy modesetting. pass module option r4xx_atom to try using atom on r4xx.
2008-09-25Seperate modesetting userspace bits into drm_mode.hJakob Bornecrantz
2008-09-24radeon: add r600 modesetting registers writesDave Airlie
2008-09-18radeon: add function to configure PCIE lanesAlex Deucher
2008-09-18Radeon: restructure PLL dataAlex Deucher
- store pixel clocks, core clock, and memory clocks separately - grab all pll limits from bios tables
2008-09-18radeon: fixup buffer and cs bitsDave Airlie
2008-09-18radeon: fail properly if we can't create the ring.Dave Airlie
Normally this will be due to an AGP driver needing updating
2008-09-18radeon: do proper memory controller init and setupDave Airlie
2008-09-18radeon: remove unneeded debuggingDave Airlie
2008-09-18make text reserve 256kDave Airlie
2008-09-18radeon: add initial suspend/resume supportDave Airlie
plus a bunch of fixes
2008-09-17nv50: add initial context for chipset 0xaaBen Skeggs
This just doesn't look right..
2008-09-17nv50: add initial context to match ctxprog for chipset 0x50Ben Skeggs
2008-09-17nv50: add ctxprog for chipset 0x50Ben Skeggs
2008-09-17nv50: add ctxprog for chipset 0xaaBen Skeggs
2008-09-17nv50: add support for chipset 0x92Ben Skeggs
2008-09-06[FreeBSD] Ensure that drm_pci_alloc is never called while locks are held.Robert Noland
2008-09-07radeon: change interface from headers add pin_domain into paddingDave Airlie
2008-09-05i915: fix i915_ring_validate()Robert Noland
2008-09-05nouveau: 8200 cards are 0xA0 family.Stephane Marchesin
2008-08-31radeon: make writeback work after suspend/resume.Dave Airlie
While re-writing this for modesetting, I find we disable writeback on resume.
2008-08-29[FreeBSD] Replace typedefs on bsd.vehemens
Signed-off-by: Robert Noland <rnoland@2hip.net>
2008-08-27drm: fix some whitespaceDave Airlie
2008-08-26radeon: fixup domains and use them properlyDave Airlie
2008-08-24i915: Fix i915 build on FreeBSDRobert Noland
ifdef out all the gem stuff for now. Also, the msi stuff isn't portable the way it is... I'll try and fix that up sometime soon.
2008-08-24i915: Convert vblank on disabled pipe DRM_ERROR to DRM_DEBUG.Robert Noland
2008-08-24i915: Clear sarea_priv during lastclose.Robert Noland
sarea_priv needs to be NULL before i915_initialized is called to properly reset it. The stale value produces a panic any time something opens/closes drm without calling initialize. i.e. version checking
2008-08-24i915: Free dev->dev_private on unload.Robert Noland
2008-08-24i915: Move spinlock init / destroy to load / unload time.Robert Noland
This resolves the panic on FreeBSD during VT switch, without attempting any of the more lofty goals for the time being.
2008-08-19nouveau: fifo and graphics engine suspend and resume for nv04-nv4xroot
Corresponding DDX patch at http://people.freedesktop.org/~stuart/nv0x-nv4x_suspend/
2008-08-19radeon: oops set correct scratchDave Airlie
2008-08-17radeon: first pass at bios scratch regsAlex Deucher
- todo: updated connected status
2008-08-17nouveau: make it compile under 2.6.27Maarten Maathuis
2008-08-16i915: finish removing TTM bitsJesse Barnes
Makes it build again.
2008-08-16Merge branch 'modesetting-gem' of ssh://git.freedesktop.org/git/mesa/drm ↵Jesse Barnes
into modesetting-gem
2008-08-16i915: set domain properly on fb mapping, flush out changesJesse Barnes
The user visible ioctl does this, but since we call into GEM internals directly, we have to flush things ourselves. Fixes initial fb console corruption.
2008-08-14radeon: add support for memory map initDave Airlie
2008-08-14radeon: add copy/solid regs for rn50Dave Airlie
2008-08-14i915: fixup from last merge hopefullyDave Airlie
2008-08-14Merge branch 'radeon-gem-cs' into modesetting-gemDave Airlie
Conflicts: libdrm/xf86drm.c linux-core/Makefile.kernel linux-core/drmP.h linux-core/drm_compat.h linux-core/drm_drv.c linux-core/drm_stub.c linux-core/drm_vm.c shared-core/i915_dma.c shared-core/r300_cmdbuf.c shared-core/radeon_drv.h
2008-08-14Get legacy working finallyAlex Deucher
- extra ~ in RADEON_WRITE_P() - re-arrange crtc setup a bit - add debugging for tracing calls - fix pitch calculation
2008-08-14Brute force port of legacy crtc/encoder codeAlex Deucher
- removed save/init/restore chain with set functions
2008-08-14radeon: fix kernel_mm properlyDave Airlie
2008-08-14radeon: remove debuggingDave Airlie
2008-08-14radeon: use mm_enabled variable to denote memory manager runningDave Airlie
2008-08-14radeon: make buffer swap for older drivers work again on GEMDave Airlie
2008-08-14radeon: add userspace call for mm support checkDave Airlie
2008-08-14radeon: FEDORA: add old DMA buffers on top of GEMDave Airlie
This really shouldn't go upstream, it just lets me run the old 3D driver on GEM setup system
2008-08-13i915: setup hardware status page if physical addrs are requiredJesse Barnes
Needed for the modesetting case where we initialize the ring at load time.
2008-08-13Merge branch 'modesetting-101' into modesetting-gemJesse Barnes
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-05 15:01:05 +0000
span class="hl com">/*224*/ volatile unsigned int vclipmax; /* Viewclip XY Max Bounds */ /*228*/ volatile unsigned int vclipzmin; /* Viewclip Z Min Bounds */ /*22c*/ volatile unsigned int vclipzmax; /* Viewclip Z Max Bounds */ /*230*/ volatile unsigned int dcsf; /* Depth Cue Scale Front Bound */ /*234*/ volatile unsigned int dcsb; /* Depth Cue Scale Back Bound */ /*238*/ volatile unsigned int dczf; /* Depth Cue Z Front */ /*23c*/ volatile unsigned int dczb; /* Depth Cue Z Back */ /*240*/ unsigned int pad9; /* Reserved */ /*244*/ volatile unsigned int blendc; /* Alpha Blend Control */ /*248*/ volatile unsigned int blendc1; /* Alpha Blend Color 1 */ /*24c*/ volatile unsigned int blendc2; /* Alpha Blend Color 2 */ /*250*/ volatile unsigned int fbramitc; /* FB RAM Interleave Test Control */ /*254*/ volatile unsigned int fbc; /* Frame Buffer Control */ /*258*/ volatile unsigned int rop; /* Raster OPeration */ /*25c*/ volatile unsigned int cmp; /* Frame Buffer Compare */ /*260*/ volatile unsigned int matchab; /* Buffer AB Match Mask */ /*264*/ volatile unsigned int matchc; /* Buffer C(YZ) Match Mask */ /*268*/ volatile unsigned int magnab; /* Buffer AB Magnitude Mask */ /*26c*/ volatile unsigned int magnc; /* Buffer C(YZ) Magnitude Mask */ /*270*/ volatile unsigned int fbcfg0; /* Frame Buffer Config 0 */ /*274*/ volatile unsigned int fbcfg1; /* Frame Buffer Config 1 */ /*278*/ volatile unsigned int fbcfg2; /* Frame Buffer Config 2 */ /*27c*/ volatile unsigned int fbcfg3; /* Frame Buffer Config 3 */ /*280*/ volatile unsigned int ppcfg; /* Pixel Processor Config */ /*284*/ volatile unsigned int pick; /* Picking Control */ /*288*/ volatile unsigned int fillmode; /* FillMode */ /*28c*/ volatile unsigned int fbramwac; /* FB RAM Write Address Control */ /*290*/ volatile unsigned int pmask; /* RGB PlaneMask */ /*294*/ volatile unsigned int xpmask; /* X PlaneMask */ /*298*/ volatile unsigned int ypmask; /* Y PlaneMask */ /*29c*/ volatile unsigned int zpmask; /* Z PlaneMask */ /*2a0*/ ffb_auxclip auxclip[4]; /* Auxilliary Viewport Clip */ /* New 3dRAM III support regs */ /*2c0*/ volatile unsigned int rawblend2; /*2c4*/ volatile unsigned int rawpreblend; /*2c8*/ volatile unsigned int rawstencil; /*2cc*/ volatile unsigned int rawstencilctl; /*2d0*/ volatile unsigned int threedram1; /*2d4*/ volatile unsigned int threedram2; /*2d8*/ volatile unsigned int passin; /*2dc*/ volatile unsigned int rawclrdepth; /*2e0*/ volatile unsigned int rawpmask; /*2e4*/ volatile unsigned int rawcsrc; /*2e8*/ volatile unsigned int rawmatch; /*2ec*/ volatile unsigned int rawmagn; /*2f0*/ volatile unsigned int rawropblend; /*2f4*/ volatile unsigned int rawcmp; /*2f8*/ volatile unsigned int rawwac; /*2fc*/ volatile unsigned int fbramid; /*300*/ volatile unsigned int drawop; /* Draw OPeration */ /*304*/ unsigned int pad10[2]; /* Reserved */ /*30c*/ volatile unsigned int lpat; /* Line Pattern control */ /*310*/ unsigned int pad11; /* Reserved */ /*314*/ volatile unsigned int fontxy; /* XY Font coordinate */ /*318*/ volatile unsigned int fontw; /* Font Width */ /*31c*/ volatile unsigned int fontinc; /* Font Increment */ /*320*/ volatile unsigned int font; /* Font bits */ /*324*/ unsigned int pad12[3]; /* Reserved */ /*330*/ volatile unsigned int blend2; /*334*/ volatile unsigned int preblend; /*338*/ volatile unsigned int stencil; /*33c*/ volatile unsigned int stencilctl; /*340*/ unsigned int pad13[4]; /* Reserved */ /*350*/ volatile unsigned int dcss1; /* Depth Cue Scale Slope 1 */ /*354*/ volatile unsigned int dcss2; /* Depth Cue Scale Slope 2 */ /*358*/ volatile unsigned int dcss3; /* Depth Cue Scale Slope 3 */ /*35c*/ volatile unsigned int widpmask; /*360*/ volatile unsigned int dcs2; /*364*/ volatile unsigned int dcs3; /*368*/ volatile unsigned int dcs4; /*36c*/ unsigned int pad14; /* Reserved */ /*370*/ volatile unsigned int dcd2; /*374*/ volatile unsigned int dcd3; /*378*/ volatile unsigned int dcd4; /*37c*/ unsigned int pad15; /* Reserved */ /*380*/ volatile unsigned int pattern[32]; /* area Pattern */ /*400*/ unsigned int pad16[8]; /* Reserved */ /*420*/ volatile unsigned int reset; /* chip RESET */ /*424*/ unsigned int pad17[247]; /* Reserved */ /*800*/ volatile unsigned int devid; /* Device ID */ /*804*/ unsigned int pad18[63]; /* Reserved */ /*900*/ volatile unsigned int ucsr; /* User Control & Status Register */ /*904*/ unsigned int pad19[31]; /* Reserved */ /*980*/ volatile unsigned int mer; /* Mode Enable Register */ /*984*/ unsigned int pad20[1439]; /* Reserved */ } ffb_fbc, *ffb_fbcPtr; struct ffb_hw_context { int is_2d_only; unsigned int ppc; unsigned int wid; unsigned int fg; unsigned int bg; unsigned int consty; unsigned int constz; unsigned int xclip; unsigned int dcss; unsigned int vclipmin; unsigned int vclipmax; unsigned int vclipzmin; unsigned int vclipzmax; unsigned int dcsf; unsigned int dcsb; unsigned int dczf; unsigned int dczb; unsigned int blendc; unsigned int blendc1; unsigned int blendc2; unsigned int fbc; unsigned int rop; unsigned int cmp; unsigned int matchab; unsigned int matchc; unsigned int magnab; unsigned int magnc; unsigned int pmask; unsigned int xpmask; unsigned int ypmask; unsigned int zpmask; unsigned int auxclip0min; unsigned int auxclip0max; unsigned int auxclip1min; unsigned int auxclip1max; unsigned int auxclip2min; unsigned int auxclip2max; unsigned int auxclip3min; unsigned int auxclip3max; unsigned int drawop; unsigned int lpat; unsigned int fontxy; unsigned int fontw; unsigned int fontinc; unsigned int area_pattern[32]; unsigned int ucsr; unsigned int stencil; unsigned int stencilctl; unsigned int dcss1; unsigned int dcss2; unsigned int dcss3; unsigned int dcs2; unsigned int dcs3; unsigned int dcs4; unsigned int dcd2; unsigned int dcd3; unsigned int dcd4; unsigned int mer; }; #define FFB_MAX_CTXS 32 enum ffb_chip_type { ffb1_prototype = 0, /* Early pre-FCS FFB */ ffb1_standard, /* First FCS FFB, 100Mhz UPA, 66MHz gclk */ ffb1_speedsort, /* Second FCS FFB, 100Mhz UPA, 75MHz gclk */ ffb2_prototype, /* Early pre-FCS vertical FFB2 */ ffb2_vertical, /* First FCS FFB2/vertical, 100Mhz UPA, 100MHZ gclk, 75(SingleBuffer)/83(DoubleBuffer) MHz fclk */ ffb2_vertical_plus, /* Second FCS FFB2/vertical, same timings */ ffb2_horizontal, /* First FCS FFB2/horizontal, same timings as FFB2/vert */ ffb2_horizontal_plus, /* Second FCS FFB2/horizontal, same timings */ afb_m3, /* FCS Elite3D, 3 float chips */ afb_m6 /* FCS Elite3D, 6 float chips */ }; typedef struct ffb_dev_priv { /* Misc software state. */ int prom_node; enum ffb_chip_type ffb_type; u64 card_phys_base; struct miscdevice miscdev; /* Controller registers. */ ffb_fbcPtr regs; /* Context table. */ struct ffb_hw_context *hw_state[FFB_MAX_CTXS]; } ffb_dev_priv_t; extern struct file_operations DRM(fops); extern unsigned long ffb_get_unmapped_area(struct file *filp, unsigned long hint, unsigned long len, unsigned long pgoff, unsigned long flags);
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-05 15:01:05 +0000