Age | Commit message (Collapse) | Author |
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Bump libdrm version number to 2.2.0
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This will come in very handy for tiled buffers on intel hardware.
Also add some padding to interface structures to allow future binary backwards
compatible changes.
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Conflicts:
linux-core/drmP.h
linux-core/drm_drv.c
linux-core/drm_irq.c
linux-core/drm_stub.c
shared-core/drm.h
shared-core/i915_drv.h
shared-core/i915_irq.c
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that is now handled by the memory accounting.
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Fix up init and destruction code.
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bug 8662
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Fix buffer bound caching policy changing, Allow
on-the-fly changing of caching policy on bound buffers if the hardware
supports it.
Allow drivers to use driver-specific AGP memory types for TTM AGP pages.
Will make AGP drivers much easier to migrate.
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Adapt for new functions in the 2.6.19 kernel.
Remove the ability to have multiple regions in one TTM.
This simplifies a lot of code.
Remove the ability to access TTMs from user space.
We don't need it anymore without ttm regions.
Don't change caching policy for evicted buffers. Instead change it only
when the buffer is accessed by the CPU (on the first page fault).
This tremendously speeds up eviction rates.
Current code is safe for kernels <= 2.6.14.
Should also be OK with 2.6.19 and above.
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r100/r200 as others might be unsafe (r300 already does this), and add checking for these we need but aren't safe. Check the RADEON_CP_INDX_BUFFER packet on both r200 and r300 as it isn't safe neither.
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mach64_state.c: convert the DRM_MACH64_BLIT ioctl to submit a pointer to
user-space memory rather than a DMA buffer index, similar to DRM_MACH64_VERTEX.
This change allows the DDX to map the DMA buffers read-only and eliminate a
security problem where a client can alter the contents of the DMA buffer after
submission to the DRM.
This change also affects the DRI/DRM interface. Performace-wise, it basically
affects PCI mode where I get a ~12% speedup for some Mesa demos I tested.
This is mainly due to eliminating an ioctl for allocating the DMA buffer.
mach64_dma.c: move the responsibility for allocating memory for the DMA ring
in PCI mode to the DDX.
This change affects the DDX/DRM interface and unifies a couple of PCI/AGP code
paths for ring memory in the DRM.
Bump the mach64 DRM version major and date.
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Add DRM_PCI_BUFFER_RO flag for mapping PCI DMA buffer read-only. An additional
flag is needed, since PCI DMA buffers do not have an associated map.
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Factor out from mach64_dma_dispatch_vertex() the code to reclaim an unsed
buffer, in preperation for using it in mach64_dma_dispatch_blit() also.
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Factor out from mach64_freelist_get() the code to reclaim a completed buffer,
this is to improve readability for me.
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Map the DMA buffers from the same linear address as the vertex bufs. If
dev->agp_buffer_token is not set, mach64 drm maps the DMA buffers from
linear address 0x0.
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(cherry picked from f6238cf6244b32bd84e3d2819963d7f5473867c8 commit)
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(cherry picked from d58389968124191a546a14b42ef84edc224be23d commit)
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This fixes issues on X server startup with versions of xf86-video-intel that
enable the IRQ before they have a context ID.
(cherry picked from 7af93dd9849442270ec89cb4bbeef5bfd4f9e424 commit)
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Some other minor changes in preparation for actually disabling user interrupts.
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It looks like 'after a while', I915REG_INT_IDENTITY_R for some reason always has
VSYNC_PIPEB_FLAG set in the interrupt handler, even though pipe B is disabled.
So we only increase dev->vbl_received if the corresponding bit is also set in
dev->vblank_pipe.
(cherry picked from 881ba569929ceafd42e3c86228b0172099083d1d commit)
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(cherry picked from 2627131e5d0c8cd5e3f0db06451c2e7ae7569b1b commit)
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(cherry picked from 0356fe260dcf80f6d2d20e3384f2a1f4ee7f5b30 commit)
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(cherry picked from 50a0284a61d4415c0ebdb02decee76ef3115007a commit)
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When this flag is set and the target sequence is missed, wait for the next
vertical blank instead of returning immediately.
(cherry picked from 89e323e4900af84cc33219ad24eb0b435a039d23 commit)
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(cherry picked from 7f09f957d9a61ac107f8fd29128d7899a3e8a228 commit)
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(cherry picked from c2bdb76814755c9ac6e66a8815f23af0fe4f3a91 commit)
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Initialize it to default value if it hasn't been set by the X server yet.
In i915_vblank_pipe_set(), only update dev_priv->vblank_pipe and call
i915_enable_interrupt() if the argument passed from userspace is valid to avoid
corrupting dev_priv->vblank_pipe on invalid arguments.
(cherry picked from 87c57cba1a70221fc570b253bf3b24682ef6b894 commit)
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Handle relative as well as absolute target sequence numbers.
Return error if target sequence has already passed, so userspace can deal with
this situation as it sees fit.
On success, return the sequence number of the vertical blank when the buffer
swap is expected to take place.
Also add DRM_IOCTL_I915_VBLANK_SWAP definition for userspace code that may want
to use ioctl() instead of drmCommandWriteRead().
(cherry picked from d5a0f107511e128658e2d5e15bd7e6215c507f29 commit)
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This makes it easier for userspace to know when it needs to allocate an ID.
Also free drawable information memory when it's no longer needed.
(cherry picked from df7551ef7334d728ec0371423661bb403d3e270a commit)
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(cherry picked from d04751facea36cb888c7510b126658fdbc4277d5 commit)
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This uses the core facility to schedule a driver callback that will be called
ASAP after the given vertical blank interrupt with the HW lock held.
(cherry picked from 257771fa290b62d4d2ad896843cf3a207978d0bb commit)
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(cherry picked from 23d2833aaa37a33b9ddcf06cc796f59befc0d360 commit)
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(cherry picked from 43f8675534c7e95efbc92eaf2c8cc43aef95f125 commit)
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Also improve diagnostic output.
(cherry picked from af48be1096221d551319c67a9e782b50ef58fefd commit)
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Actually make the existing ioctls for adding and removing drawables do
something useful, and add another ioctl for the X server to update drawable
information. The only kind of drawable information tracked so far is cliprects.
(cherry picked from 29598e5253ff5c085ccf63580fd24b84db848424 commit)
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When the vertical blank interrupt is enabled for both pipes, pipe A is
considered primary and pipe B secondary. When it's only enabled for one pipe,
it's always considered primary for backwards compatibility.
(cherry picked from 0c7d7f43610f705e8536a949cf2407efaa5ec217 commit)
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(cherry picked from ab351505f36a6c66405ea7604378268848340a42 commit)
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Fix up some comments.
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This fixes issues on X server startup with versions of xf86-video-intel that
enable the IRQ before they have a context ID.
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It looks like 'after a while', I915REG_INT_IDENTITY_R for some reason always has
VSYNC_PIPEB_FLAG set in the interrupt handler, even though pipe B is disabled.
So we only increase dev->vbl_received if the corresponding bit is also set in
dev->vblank_pipe.
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When this flag is set and the target sequence is missed, wait for the next
vertical blank instead of returning immediately.
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