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2008-07-03i915: official name for GM45 chipsetZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
2008-07-01i915: only use tiled blits on 965+Jesse Barnes
When scheduled swaps occur, we need to blit between front & back buffers. I the buffers are tiled, we need to set the appropriate XY_SRC_COPY tile bit, only on 965 chips, since it will cause corruption on pre-965 (e.g. 945). Bug reported by and fix tested by Tomas Janousek <tomi@nomi.cz>. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-06-25nv50: when destroying a channel make sure it's not still current on PFIFOBen Skeggs
We won't get a PFIFO context switch when the same channel ID is recreated if the hw still thinks the channel is already active, which causes fun issues. Should allow X to be stopped and started without tearing down the entire card state in lastclose().
2008-06-24i915: register definition & header file cleanupJesse Barnes
It would be nice if one day the DRM driver was the canonical source for register definitions and core macros. To that end, this patch cleans things up quite a bit, removing redundant definitions (some with different names referring to the same register) and generally tidying up the header file.
2008-06-23nv50: oops, keep VRAM allocations aligned at 64KiB - that's our page size..Ben Skeggs
2008-06-23nv50: use same dma object for fb/tt accessBen Skeggs
We depend on the VM fully now for memory protection, separate DMA objects for VRAM and GART are unneccesary. However, until the next interface break (soon) a client can't depend on the objects being the same and must still call NV_OBJ_SET_DMA_* methods appropriately.
2008-06-23nouveau: allocate drm-use vram buffers from end of vram.Ben Skeggs
This avoids seeing garbage from engine setup etc before X gets around to pointing the CRTCs at a new scanout buffer. Not actually a noticable problem before G80 as PRAMIN is forced to the end of VRAM by the hardware already.
2008-06-21RADEON: 0x1002 0x5657 is actually an RV410Alex Deucher
See bug 14289
2008-06-20r300: fix warningDave Airlie
2008-06-18i915: Add support for Intel 4 series chipsetsZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
2008-06-15radeon: *really* fix screen corruption thanks to Lukasz KrotowskiJerome Glisse
2008-06-15radeon: actualy try to fix the corruptionJerome Glisse
2008-06-15radeon: fix screen corruption introduced by last patchJerome Glisse
2008-06-13radeon: bump driver date to know if lockup fix is inJerome Glisse
2008-06-13radeon: r345xx fixe hard lockupJerome Glisse
This patch should fixe hard lockup and convert them in softlockup (ie you can ssh the box but the gpu is busted and we are waiting in loop for it to come back to reason).
2008-06-11RADEON: use DSTCACHE_CTLSTAT rather than RB2D_DSTCACHE_CTLSTATAlex Deucher
According to the hw guys, you should use DSTCACHE_CTLSTAT to flush the 2D dst cache rather than RB2D_DSTCACHE_CTLSTAT.
2008-06-10xgixp: Remove dependency on TTM fencesIan Romanick
2008-06-09RADEON: Add untested support for RS400 chipsAlex Deucher
GART setup appears to work the same as RS480 chips. Also RC4xx chips are actually RS400 based, not RS480 based.
2008-06-09RADEON: switch IGP gart to use radeon_write_agp_base()Alex Deucher
2008-06-08Fix typo in i915_suspendRobert Noland
Reported by vehemens
2008-06-08I915 suspend/resume for FreeBSDRobert Noland
2008-06-09r300/r500: add hier-z regsDave Airlie
2008-06-05radeon: Restore software interrupt on resume.Dennis Kasprzyk
Fixes performance drop after suspend/resume on some systems.
2008-06-03drm: sg alloc should write back the handle to userspaceDave Airlie
2008-05-30RADEON: fix typo in last commitAlex Deucher
2008-05-30r500: attempt to make AGP work by programming agp base in the MC correctlyDave Airlie
2008-05-28radeon: split microcode out into a separate header file.Dave Airlie
2008-05-28i915: fix BSD bh, DRI2 not uses anywhere elseDave Airlie
2008-05-28radeon: bump release date/version for r500 3D supportDave Airlie
2008-05-27RADEON: add get_param for number of GB pipesAlex Deucher
2008-05-27[i915] Fix typo in (unused) START_ADDR definition.Jie Luo
2008-05-27[FreeBSD] Add vblank-rework support and get drivers building.Robert Noland
The i915 driver now works again.
2008-05-23r500: add two more register ranges for mesa driver to setupDave Airlie
2008-05-23drm: fix nouveau warningDave Airlie
2008-05-21rs690/r500: vblank support.Dave Airlie
The new display controller has the vblank interrupts in a different place. Add support for vbl interrupts for these chips
2008-05-17r500: add more register ranges for Mesa driverDave Airlie
2008-05-13RS4xx: separate out RS400 and RS480 IGP chipsAlex Deucher
RS400 (intel based IGP) and RS480 (AMD based IGP) have different MC and GART setups. Currently we only support RS480.
2008-05-12RADEON: fix copy/pasto in last commitAlex Deucher
2008-05-12R3/4/5: init pipe setup in drmAlex Deucher
Similar (broken) code in mesa needs to be removed
2008-05-12RADEON: cleanup radeon_do_engine_reset()Alex Deucher
2008-05-12R300+: fixup pixcache flushAlex Deucher
2008-05-12RS4xx: fix MCIND index maskAlex Deucher
2008-05-12RADEON: write AGP_BASE_2 on chips that support itAlex Deucher
2008-05-12R300+: fixup PURGE/FLUSH macrosAlex Deucher
2008-05-12Radeon IGP: merge RS4xx/RS6xx gart setupAlex Deucher
2008-05-12Radeon IGP: wrap MCIND accessAlex Deucher
first step in merging rs4xx/rs6xx gart setup
2008-05-12Radeon IGP: clean up registers and magic numbersAlex Deucher
2008-05-05r500: add allowed range for us config/pixsizeDave Airlie
2008-05-02nv50: enable 0x400500 bit 0 after PGRAPH exception alsoBen Skeggs
No solid idea about what these 2 bits do, but nv50 can now survive a few PGRAPH exceptions just as nv40 does :)
2008-05-02nouveau: guard against channels potentially not having a context, fix nv50Ben Skeggs
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