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2007-06-28nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bitBen Skeggs
2007-06-28nouveau: simplify PRAMIN accessBen Skeggs
2007-06-28nouveau: name some regsBen Skeggs
2007-06-28nouveau/nv50: skeletal backendBen Skeggs
2007-06-28nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)Ben Skeggs
For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaksBen Skeggs
2007-06-26More 64-bit padding.Thomas Hellstrom
2007-06-26Add support SiS based XGI chips to SiS DRM.Ian Romanick
2007-06-25nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303Ben Skeggs
2007-06-24nouveau: kill some dead codeBen Skeggs
2007-06-24nouveau: NV04/NV10/NV20 PGRAPH engtab functionsBen Skeggs
NV04/NV10 load_context()/save_context() are stubs. I don't know enough about how they work to implement them sanely. The "old" context_switch() code remains hooked up, so it shouldn't break anything. NV20 will probably break if load_context() works. No inital context values are filled in, so when the first channel is created PGRAPH will probably end up having its state zeroed. Some setup from nv20_graph_init() will probably need to be moved to the per-channel context setup.
2007-06-24nouveau: NV3X PGRAPH engtab functionsBen Skeggs
2007-06-24nouveau: NV1X/2X/3X PFIFO engtab functionsBen Skeggs
Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC entry size.
2007-06-24nouveau: NV04 PFIFO engtab functionsBen Skeggs
2007-06-24nouveau: NV4X PGRAPH engtab functionsBen Skeggs
2007-06-24nouveau: NV4X PFIFO engtab functionsBen Skeggs
2007-06-24nouveau: split PFIFO/PGRAPH context creationBen Skeggs
2007-06-24nouveau: (mostly) hook up put_base againBen Skeggs
2007-06-24nouveau: prototype PFIFO/PGRAPH engtab APIBen Skeggs
2007-06-24nouveau: rename engtab functionsBen Skeggs
2007-06-22Merge branch 'vblank-rework' into vblankJesse Barnes
2007-06-22more vblank reworkJesse Barnes
- use a timer for disabling vblank events to avoid enable/disable calls too often - make i915 work with pre-965 chips again (would like to structure this better, but this hack works on my test system)
2007-06-22radeon: Acknowledge all interrupts we're interested in.Michel Dänzer
Failure to do so was probably the root cause of fd.o bug 11287.
2007-06-22drm_modeset_ctl_t fixes.Michel Dänzer
s/u64/drm_u64_t/ to allow userspace code using drm.h to compile. Move 64 bit arg member to the beginning to avoid alignment issues with 32 bit userspace on 64 bit kernels.
2007-06-22Remove mask parameter from radeon_acknowledge_irqs().Michel Dänzer
Simply always acknowledge all interrupts we're interested in, to avoid hard hangs when an unexpected interrupt is flagged.
2007-06-21Merge branch 'vblank-rework' into vblankJesse Barnes
2007-06-21RADEON: fix race in vblank interrupt handlingJesse Barnes
It's possible that we disable vblank interrupts and clear the corresponding flag in irq_enable_reg, but receive an interrupt at just the wrong time, causing us to not ack it properly, nor report to the core kernel that it was handled. Fix that case by always handling vblank interrupts, even if the irq_enable_reg field is clear.
2007-06-21r300: Synchronized the register defines file; documentation changes.Oliver McFadden
2007-06-21r300: Allow writes to R300_VAP_PVS_WAITIDLE.Oliver McFadden
2007-06-18Remove broken CRTC enable checks and incorrect user irq enable in set_pipeJesse Barnes
routine.
2007-06-18radeon: VBlank rework fixups.Michel Dänzer
Fix range of frame counter registers. Use DRM_ERR() instead of Linux specific error codes in shared code. Remove duplicate register definitions and superfluous local variables.
2007-06-18r300: Registers 0x2220-0x2230 are known as R300_VAP_CLIP_X_0-R300_VAP_CLIP_Y_1.Oliver McFadden
2007-06-18r300: Synchronized the register defines file again.Oliver McFadden
2007-06-15Remove broken crtc enable checks, radeon does it slightly differentlyJesse Barnes
(this makes get_vblank_counter return an actual value).
2007-06-15First cut at radeon support for the vblank rework.Jesse Barnes
2007-06-15i915: Fix handling of breadcrumb counter wraparounds.Michel Dänzer
2007-06-15Wake up vblank waitqueue in drm_handle_vblank().Michel Dänzer
2007-06-15i915: Fix tests for vblank interrupts being enabled on CRTC by X server.Michel Dänzer
2007-06-15Fix memory leaks in vblank error paths.Michel Dänzer
Also use drm_calloc instead of drm_alloc and memset, and use the size of the struct instead of the size of the pointer for allocation...
2007-06-14Comment new vblank routines and fixup several issues:Jesse Barnes
- use correct refcount variable in get/put routines - extract counter update from drm_vblank_get - make signal handling callback per-crtc - update interrupt handling logic, drivers should use drm_handle_vblank - move wakeup and counter update logic to new drm_handle_vblank routine - fixup usage of get/put in light of counter update extraction - fix longstanding bug in signal code, update pending counter only *after* we're sure we'll setup signal handling
2007-06-12Remove unnecessary (and uncommented!) read barrier from the interruptJesse Barnes
path. It doesn't appear to serve any useful purpose.
2007-06-12Update vblank code:Jesse Barnes
- move pre/post modeset ioctl to core - fixup i915 buffer swap - fix outstanding signal count code - create new core vblank init routine - test (works with glxgears) - simplify i915 interrupt handler
2007-06-12Initial checkin of vblank rework. Code attempts to reduce the numberJesse Barnes
of vblank interrupt in order to save power.
2007-06-12Fix some obvious bugs.Thomas Hellstrom
2007-06-12Try to make buffer object / fence object ioctl args 64-bit safe.Thomas Hellstrom
Introduce tile members for future tiled buffer support. Allow user-space to explicitly define a fence-class. Remove the implicit fence-class mechanism. 64-bit wide buffer object flag member.
2007-06-08r300: Added the CP maximum fetch size and ring rptr update variables.Oliver McFadden
2007-06-05r300: Small correction to the previous commit.Oliver McFadden
2007-06-05r300: Document more of the RADEON_RBBM_STATUS register.Alex Deucher
2007-06-05Add support for the G33, Q33, and Q35 chipsets.Wang Zhenyu
These require that the status page be referenced by a pointer in GTT, rather than phsyical memory. So, we have the X Server allocate that memory and tell us the address, instead.
2007-06-04nouveau: fix RAMHT wrappingMaurice van der Pot
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