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My 965GM gets interrupts stuck when using the old PIPE_VBLANK interrupt.
Switch to the PIPE_EVENT interrupt mechanism, and set the PIPE*STAT
registers to use START_VBLANK on 965 and VBLANK on previous chips.
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Will hopefully work a bit better than previous code, which depended on
knowing the channel's most recent PUT value. Some chips always return
0 on reading these regs, and currently userspace is the only other entity
which knows the value.
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Not only was this entirely pointless, it actually causes my NV30GL to
die randomly when channels are destroyed.
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this adds something to say the kernel initialised the memory region not
the userspace. and blocks userspace from deallocating kernel areas
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taken from modesetting branch but could be useful outside it.
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Rip out the whole head thing and replace it with an idr and drm_minor
structure.
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writting relocations, otherwise the GPU probably sees some
inconsistent data. Fix fd.o bug#14656
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to leap it's vblank count a huge value.
This will stall some applications that switch video mode if vblank_mode is set to a non zero value in drirc.
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In particular -EAGAINs, which should be common during Xserver operation.
Also handle the fence creation failure case.
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Texture uploads could hit the blitter coordinate limit, adjust the texture
offset when uploading the pieces. Make sure to check the end address of the
upload too.
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Thanks to Todd Merrill for pointing it out.
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This matches the changes in mesa to use the system drm includes
for the definitions of the drm ioctl structs.
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Failing to preserve the MI_ARB_STATE register was causing FIFO underruns on
the VGA output on my HP 2510p after resume.
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Make sure we have enough room for all the GR registers or we'll end up
clobbering the AR index register (which should actually be harmless
unless the BIOS is making an assumption about it).
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On resume, if the interrupt state isn't restored correctly, we may end
up with a flood of unexpected or ill-timed interrupts, which could cause
the kernel to disable the interrupt or vblank events to happen at the
wrong time. So save/restore them properly.
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since a breadcrumb may actually turn up before a corresponding fence object
has been placed on the fence ring.
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And make nv30_graph_init a bit more like mmio-traces
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- Moved the fix from the ddx to drm, because it seemed more appropriate.
- Don't be shy, report if it works for you or not.
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waiting types.
Add a "command_stream_barrier" method to the bo driver.
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With some luck the drm-side will be OK now for this chipset.
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bug 14289
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This adds support for configuring the RS690 GART.
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don't disable vblank interrupts (similar to r128)
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Should be 0x08 rather than 0xa0, and shouldn't use typedefs.
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This requires updated Mesa to handle the new relocation format.
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We need to return an accurate vblank count to the callers of
->get_vblank_counter, and in the Intel case the actual frame count
register isn't udpated until the next active line is displayed, so we
need to return one more than the frame count register if we're currently
in a vblank period.
However, none of the various ways of doing this is working yet, so
disable the logic for now. This may result in a few missed events, but
should fix the hangs some people have seen due to the current code
tripping the wraparound logic in drm_update_vblank_count.
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Switch relocs to using copy from user and remove index and pass buffer
handles in instead.
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Should use vtotal not htotal to figure out if we're in a vblank period.
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One to many parantheses...
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The frame count registers don't increment until the start of the next
frame, so make sure we return an incremented count if called during the
actual vblank period.
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Ack the IRQs correctly (PIPExSTAT first followed by IIR). Don't read
vblank counter registers on disabled pipes (might hang otherwise). And
deal with flipped pipe/plane mappings if present.
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