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2007-09-18i915: Reinstate check that drawable has valid information in i915_vblank_swap.Michel Dänzer
2007-09-18i915: Fix scheduled buffer swaps.Michel Dänzer
One instance of unlocking a spinlock was converted incorrectly when this code was fixed to build on BSD.
2007-09-18Add ioc32 compat layer for XGI DRM.Ian Romanick
2007-09-12Remove plane->pipe mapping from SAREA private after allJesse Barnes
We can figure out which pipe a given plane is mapped to by looking at the display control registers instead of tracking it in a new SAREA private field. If this becomes a performance problem, we could move to an ioctl based solution by adding a new parameter for the DDX to set (defaulting to the old behavior if the param was never set of course).
2007-09-11Merge branch 'master' of ssh://git.freedesktop.org/git/mesa/drmJesse Barnes
2007-09-11Disambiguate planes & pipes for swap operationsJesse Barnes
This mod makes the SAREA track plane to pipe mappings and corrects the name of the plane info variables (they were mislabeled as pipe info since until now all code assumed a direct mapping between planes and pipes). It also updates the flip ioctl argument to take a set of planes rather than pipes, since planes are flipped while pipes generate vblank events.
2007-09-10nouveau: nv10: add combiner registersPatrice Mandin
2007-09-09nouveau : nv10 fix NV10_PGRAPH_CTX_USER save/loadMatthieu Castet
2007-09-09nouveau : nv10 pipe ctx switch load/save.Matthieu Castet
This fix some issues with more than one 3D fifo, but there still some "corruption" sometimes
2007-09-08nouveau: Add Quadro NVS 140 pciidMaarten Maathuis
2007-09-07nouveau: Use nv41 ctxprog/vals on nv42.Ben Skeggs
2007-09-06Merge branch 'xgi-0-0-2'Ian Romanick
2007-09-06nouveau: fix some nv04 graph switching.Stephane Marchesin
2007-09-06nouveau: add pure nv30 support.Stephane Marchesin
2007-09-04Add context init voodoo and context switch code for NV41.Maarten Maathuis
2007-08-31Merge branch 'master' of ssh+git://git.freedesktop.org/git/mesa/drm into ↵Ian Romanick
xgi-0-0-2
2007-08-31nouveau: nv04 context switching support. Works for starting X up at least.Stephane Marchesin
2007-08-31nouveau: give nv03 the last cut.Stephane Marchesin
2007-08-28Add register defines for hw binningKeith Packard
2007-08-28drm: remove XFREE86_VERSION macrosDave Airlie
2007-08-26nouveau : add NV04_PGRAPH_TRAPPED_ADDR definitionMatthieu Castet
- fix offset for nv04 - use it in nv10 graph ctx switch for getting next channel - dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+
2007-08-25nouveau : nv1x graph reworksMatthieu Castet
- add forgotten init value - use the same PGRAPH_DEBUG than the blob - remove init of ddx reg : it should be done with object - better handle of channel destruction hope I didn't break anything ;)
2007-08-25nouveau: nv10: output a warning if last channel invalid, and switch to nextPatrice Mandin
2007-08-23nouveau: nv10: check some NULL pointers inside context switchPatrice Mandin
2007-08-22nouveau : fix some potential crashes with objects causing hash collisionMatthieu Castet
2007-08-22nouveau/nv40: Preserve other bits in 0x400304/0x400310 like NVIDIA do.Ben Skeggs
2007-08-22nouveau/nv40: Dump extra info on ucode state if ctx switch fails.Ben Skeggs
2007-08-22nouveau: NV4c ctx ucode.Ben Skeggs
Seems we already have a nv4c_ctx_init() somehow, a quick check shows the ucode matches it still.
2007-08-22nouveau/nv50: Correct thinko for 8800 chips + cleanup a bit.Ben Skeggs
2007-08-22nouveau: redo nv30_graph.c. Should work better, but we still lack a couple ↵Stephane Marchesin
of cards.
2007-08-22nouveau: fix the comment and debug message for PCIGART sizeStephane Marchesin
2007-08-21nouveau: Add NV44 ctx ucode. Patch from stillunknown.Ben Skeggs
Microcode is similar enough to the NV4A one that it should be able to use the same initial PGRAPH context. One day this mess will go away, honest..
2007-08-21nouveau: Poke 0x2230 on NV47 also.Ben Skeggs
Makes 0x2220 work the same way as on NV40.
2007-08-19Check also for Linux, as it's not supported on different OSPatrice Mandin
2007-08-19Function pci_get_bus_and_slot needs 2.6.19 or laterPatrice Mandin
2007-08-17nouveau: Detect memory on NFORCE/NFORCE2 correctly.Ben Skeggs
2007-08-15nouveau: Use count parameter in nouveau_notifier_alloc().Ben Skeggs
2007-08-15nouveau: Turn some messages into DRM_DEBUGs..Ben Skeggs
2007-08-15nouveau: Allow GART notifiers when using sgdma code.Ben Skeggs
2007-08-15nouveau: Workaround mysterious PRAMIN clobbering by the card.Ben Skeggs
2007-08-14Eliminate unused / useless ioctls.Ian Romanick
2007-08-15nouveau: Catch all NV4x chips instead of just NV_40.Ben Skeggs
2007-08-15nouveau/nv40: Fix channel scheduling.Ben Skeggs
Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels will appear to "freeze" in some circumstances.
2007-08-11i915: i965 non-secure batchbuffer bit has moved.Dave Airlie
2007-08-10nouveau/nv50: demagic instmem setup.Ben Skeggs
2007-08-10nouveau: Allow creation of gpuobjs before any other init has taken place.Ben Skeggs
2007-08-09Unify alloc and free ioctls.Ian Romanick
The DRM_XGI_PCIE_ALLOC and DRM_XGI_FB_ALLOC ioctls (and the matching free ioctls) are unified to DRM_XGI_ALLOC. The desired memory region is selected by xgi_mem_alloc::location. The region is magically encoded in xgi_mem_alloc::index, which is used to release the memory. Bump to version 0.11.0. This update requires a new DDX.
2007-08-09nouveau: silence irq handler a bitBen Skeggs
2007-08-09nouveau/nv40: add some missing pciids.Ben Skeggs
2007-08-08nouveau : nv10, nv20, nv30 : don't save all channel in the same RAMFC entryMatthieu Castet
This should improve multi fifo
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