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2008-05-02Add name/open ioctls, separate handle and pointer ref counts.Keith Packard
Names are just another unique integer set (from another idr object). Names are removed when the user refernces (handles) are all destroyed -- this required that handles for objects be counted separately from internal kernel references (so that we can tell when the handles are all gone).
2008-05-02Remove drm_driver argument to functions taking drm_gem_object.Keith Packard
Now that drm_gem_object has a drm_driver * in it, functions don't need both parameters.
2008-05-02Fix nouveau warning when returning pointers in uint64_t objects.Keith Packard
2008-05-01Add alignment to all aperture allocation requests.Keith Packard
When pinning buffers, or using execbuffer, allow the application to specify the necessary aperture allocation alignment constraints.
2008-05-01Fix gem ioctls to be 32/64-bit clean.Keith Packard
mixed 32/64 bit systems need 'special' help for ioctl where the user-space and kernel-space datatypes differ. Fixing the datatypes to be the same size, and align the same way for both 32 and 64-bit ppc and x86 environments will elimiante the need to have magic 32/64-bit ioctl translation code.
2008-05-01Make GEM object handles be nonzero.Eric Anholt
2008-05-01Remove _args from gem ioctl argument structure tags.Eric Anholt
2008-05-01Add pin/unpin object ioctls for gem.Eric Anholt
2008-05-01checkpoint: relocations support.Eric Anholt
2008-05-01checkpoint: gtt binding written.Eric Anholt
2008-05-01checkpoint: rename to GEM and a few more i915 bits.Eric Anholt
2008-04-30Hacking towards hooking up execbuffer.Eric Anholt
2008-04-29Remove the remainder of the mmfs device.Eric Anholt
2008-04-29Move mmfs ioctls into the DRM. Untested.Eric Anholt
2008-04-23Add pread/pwrite ioctls to mmfs.Eric Anholt
2008-04-23Extend the mmfs basic test to do a couple of ioctls.Eric Anholt
2008-04-23Move mmfs.h userland interface to shared-core.Eric Anholt
2008-04-22i915: gfx hw and i945gme fixes from upstreamDave Airlie
From Jesse and Zhenyu originally.
2008-04-20[I915] Handle tiled buffers in vblank taskletKeith Packard
The vblank tasklet update code must build 2D blt commands with the appropriate tiled flags.
2008-04-20On I965, use correct 3DSTATE_DRAWING_RECTANGLE command in vblankKeith Packard
The batchbuffer submission paths were fixed to use the 965-specific command, but the vblank tasklet was not. When the older version is sent, the 965 will lock up.
2008-04-11Save and restore dsparb and d_state regsKeith Packard
2008-04-05nv50: primitive i2c interrupt handlerMaarten Maathuis
2008-04-03nv50: primitive display interrupt handler.Maarten Maathuis
2008-03-31nouveau: fix return from function..Dave Airlie
dude kernel moduless use kernel errors :) this fixes an oops on init when this codepath hits.
2008-03-30nouveau: forgot to add a breakMaarten Maathuis
2008-03-30nouveau: Add ctx values for nv86.Maarten Maathuis
- Note that this may not work for all nv86.
2008-03-30drm/r300: fix wait interface mixupDave Airlie
This interface was defined completely wrong, however userspace has only ever used 4 values from it (0x1, 0x2, 0x3 and 0x6), so fix the interface to do what userspace actually expected but define new defines for new users to use it properly.
2008-03-29r300: Correctly translate the value for the R300_CMD_WAIT command.Oliver McFadden
Previously, the R300_CMD_WAIT command would write the passed directly to the hardware. However this is incorrect because the R300_WAIT_* values used are internal interface values that do not map directly to the hardware. The new function I have added translates the R300_WAIT_* values into appropriate values for the hardware before writing the register. Thanks to John Bridgman for pointing this out. :-)
2008-03-25nouveau: nv20 bios does not initialise PTIMERStuart Bennett
The wait functions depend on PTIMER, so write the old (incorrect, but working) values for uninitialised hw
2008-03-24i915: fix oops on agp=offDave Airlie
Kernel bug 10289.
2008-03-24Merge branch 'r500-fp'Dave Airlie
2008-03-24nv40: voodoo - not quite.Ben Skeggs
2008-03-24nv40: allocate massive amount of PRAMIN for grctx on all chipsets.Ben Skeggs
More or less a workaround for issues on some chipsets where a context switch results in critical data in PRAMIN being overwritten by the GPU. The correct fix is known, but may take some time before it's a feasible option.
2008-03-21r500: fragment program upload is also used to upload constants.Dave Airlie
Limit frag address to 8 bits
2008-03-20drm: fixup r500fp submissionDave Airlie
2008-03-20nouveau: do not set on-board timer's numerator/denominator to bad valuesStuart Bennett
2008-03-19RADEON: switch over to new production microcodeAlex Deucher
This needs to be tested thoroughly before pushing to the kernel.
2008-03-19RADEON: production microcode for all radeons, r1xx-r6xxAlex Deucher
This updated microcode is not in use yet.
2008-03-19move some more r300 regs into not allowed on r500Dave Airlie
2008-03-18drm: add new rs690 pci idDave Airlie
2008-03-17initial r500 RS and FP register and upload codeDave Airlie
2008-03-17drm/pcigart: fix the pci gart to use the drm_pci wrapper.Dave Airlie
This is the correct fix for the RS690 and hopefully the dma coherent work. For now we limit everybody to a 32-bit DMA mask but it is possible for RS690 to use a 40-bit DMA mask for the GART table itself, and the PCIE cards can use 40-bits for the table entries. Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-03-16Avoid unnecessary waits for command regulator pause.Thomas Hellstrom
2008-03-16[via] Remove some leftover vars.Thomas Hellstrom
2008-03-16[via] The millionth fixup for the millionth-1 attempt to stabilize the AGPThomas Hellstrom
DMA command submission. It's worth remembering that all new bright ideas on how to make this command reader work properly and according to docs will probably fail :( Bring in some old code.
2008-03-16[via] Fix driver after vblank-rework merge.Thomas Hellstrom
2008-03-16drm/rs690: set AGP_BASE_2 to 0Dave Airlie
2008-03-16drm: set rs690 gart base completly.Dave Airlie
The docs state bits 4-11 represent bits 32-39 of a 40-bit address
2008-03-12Fix chip family for RV550Alex Deucher
2008-03-13nv50: force channel vram access through vmBen Skeggs
If we ever want to be able to use the 3D engine we have no choice. It appears that the tiling setup (required for 3D on G8x) is in the page tables. The immediate benefit of this change however is that it's now not possible for a client to use the GPU to render over the top of important engine setup tables, which also live in VRAM. G8x VRAM size is limited to 512MiB at the moment, as we use a 1-1 mapping of real vram pages to their offset within the start of a channel's VRAM DMA object and only populate a single PDE for VRAM use.