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2008-06-13[intel] Restructure irq to pend all work until after iir write.Keith Packard
The interrupt identity register must be writen before any work occurs lest we drop an interrupt on the floor. This patch just shuffles code around to make sure that IIR is written as early as possible.
2008-06-13[intel-gem] Use a delayed_work instead of a timer + work_structKeith Packard
We want request retirement to occur about once a second when the request queue is non-empty. This was done with a timer that queued a work_struct, using a delayed_work instead makes a lot more sense.
2008-06-13Fix i915_wait_irq in the presence of interrupt masking.Eric Anholt
In the short-circuit code for the breadcrumb already being new enough, we need to update the sarea_priv copy of the breadcrumb just as if we had waited. Otherwise userland error checking will notice that we returned too early based on its wrong information, and call wait_irq again (leading to spinning until someone else comes along and updates the sarea_priv). This bug was hidden when we had interrupt masking disabled, such as in master, since the interrupt handler would update sarea_priv.
2008-06-13[gem] Remove the interrupt handler for retiring requests.Eric Anholt
This was insufficient once we started masking interrupts to only when someone was waiting for them (and would thus retire requests themselves). It was replaced by the retire_timer.
2008-06-12Don't clear USER_INTERRUPT if we're not handling it.Eric Anholt
This fixes a regression from commit d434b64f6a760d85295e32298a9a1f3624ee1b69 which could cause us to fail to wake up for user interrupts if we lost a race.
2008-06-11[gem] Another round of cleanups from checkpatch.plEric Anholt
2008-06-11[gem] Move potentially device-specific ioctls to the intel driver.Eric Anholt
This is the create (may want location flags), pread/pwrite/mmap (performance tuning hints), and set_domain (will 32 bits be enough for everyone?) ioctls. Left in the generic set are just flink/open/close. The 2D driver must be updated for this change, and API but not ABI is broken for 3D. The driver version is bumped to mark this.
2008-06-10[intel] Fix BUG_ON trigger in irq masking if you did on/off with irqs disabled.Eric Anholt
2008-06-10[gem] Manage the ringbuffer from the kernel in the GEM case.Eric Anholt
This requires that the X Server use the execbuf interface for buffer submission, as it no longer has direct access to the ring. This is therefore a flag day for the gem interface. This also adds enter/leavevt ioctls for use by the X Server. These would get stubbed out in a modesetting implementation, but are required while in an environment where the device's state is only managed by the DRM while X has the VT.
2008-06-06[intel] remove settable use_mi_batchbuffer_startKeith Packard
The driver can know what hardware requires MI_BATCH_BUFFER vs MI_BATCH_BUFFER_START; there's no reason to let user mode configure this.
2008-06-06[intel-gem] Use timers to retire requests periodically.Keith Packard
Without the user IRQ running constantly, there's no wakeup when the ring empties to go retire requests and free buffers. Use a 1 second timer to make that happen more often.
2008-06-06[intel] free the hardware status page at driver_unloadKeith Packard
This goes with the other hardware status page patch.
2008-06-06[intel-gem] Add explicit throttle ioctlKeith Packard
Instead of throttling and execbuffer time, have the application ask to throttle explicitly. This allows the throttle to happen less often, and without holding the DRM lock.
2008-06-06[intel] Allocate hardware status page at driver load timeKeith Packard
I couldn't get the re-allocated HWS to work on my 965GM, so I just gave up and made it persist across the lifetime of the driver instead.
2008-06-06Ignore X server provided mmio addressKeith Packard
2008-05-30Merge commit 'origin/master' into drm-gemEric Anholt
Conflicts: linux-core/Makefile.kernel shared-core/i915_drv.h shared-core/nouveau_state.c
2008-05-30r500: attempt to make AGP work by programming agp base in the MC correctlyDave Airlie
2008-05-28radeon: split microcode out into a separate header file.Dave Airlie
2008-05-27[intel-gem] Replace idlelock usage with real lock acquisition.Eric Anholt
2008-05-28i915: fix BSD bh, DRI2 not uses anywhere elseDave Airlie
2008-05-28radeon: bump release date/version for r500 3D supportDave Airlie
2008-05-27RADEON: add get_param for number of GB pipesAlex Deucher
2008-05-27[i915] Fix typo in (unused) START_ADDR definition.Jie Luo
2008-05-27[FreeBSD] Add vblank-rework support and get drivers building.Robert Noland
The i915 driver now works again.
2008-05-26[i915] leave interrupts masked off when not in use.Keith Packard
The interrupt enable register cannot be used to temporarily disable interrupts, instead use the interrupt mask register. Note that this change means that a pile of buffers will be left stuck on the chip as the final interrupts will not be recognized to come and drain things.
2008-05-25[intel-gem] Add DRM_I915_GEM_BUSY ioctl to check for idle buffers.Keith Packard
This new ioctl returns whether re-using the buffer would force a wait.
2008-05-22[intel] Add debug code to verify the cached ring tail pointer.Keith Packard
Recording the tail pointer in a local variable improves performance, but if someone messes up and fails to reload at the right time, the driver will write commands to the wrong part of the ring and scramble execution badly. This change (available by setting I915_RING_VALIDATE to 1) checks to make sure the cached tail pointer matches the hardware tail pointer at each ring buffer addition, calling BUG_ON when that's not true.
2008-05-22[gem] Release GEM buffers from work task scheduled from IRQ.Eric Anholt
There are now 3 lists. Active is buffers currently in the ringbuffer. Flushing is not in the ringbuffer, but needs a flush before unbinding. Inactive is as before. This prevents object_free → unbind → wait_rendering → object_reference and a kernel oops about weird refcounting. This also avoids an synchronous extra flush and wait when freeing a buffer which had a write_domain set (such as a temporary rendered to and then from using the 2d engine). It will sit around on the flushing list until the appropriate flush gets emitted, or we need the GTT space for another operation.
2008-05-23r500: add two more register ranges for mesa driver to setupDave Airlie
2008-05-23drm: fix nouveau warningDave Airlie
2008-05-21[gem] Replace ring throttling hack with actual time measurement.Eric Anholt
2008-05-21rs690/r500: vblank support.Dave Airlie
The new display controller has the vblank interrupts in a different place. Add support for vbl interrupts for these chips
2008-05-20[gem] Use a separate sequence number field from classic/ttmEric Anholt
This lets us get some qualities we desire, such as using the full 32-bit range (except zero), avoiding DRM_WAIT_ON, and a 1:1 mapping of active sequence numbers to request structs, which will be used soon for throttling and interrupt-driven list cleanup.
2008-05-20[gem] Rename sequence numbers from "cookie" to "seqno"Eric Anholt
2008-05-20[gem] Clean up active/inactive list handling using helper functions.Eric Anholt
Additionally, a boolean active field is added to indicate which list an object is on, rather than smashing last_rendering_cookie to 0 to show inactive. This will help with flush-reduction later on, and makes the code clearer.
2008-05-17r500: add more register ranges for Mesa driverDave Airlie
2008-05-15[gem] Hold dev->struct_mutex to protect structure data.Eric Anholt
2008-05-15[gem] Rename the GTT LRU lists to active (executing) and inactive (idle).Eric Anholt
2008-05-13RS4xx: separate out RS400 and RS480 IGP chipsAlex Deucher
RS400 (intel based IGP) and RS480 (AMD based IGP) have different MC and GART setups. Currently we only support RS480.
2008-05-12[GEM] Typo (and thinking) fixes in drm-gem.txt and doxygen.Eric Anholt
2008-05-12[intel] When polling for ring space, sleep for a lot longer (10ms)Keith Packard
If the ring is full, the engine will surely be running for more than 10ms.
2008-05-12RADEON: fix copy/pasto in last commitAlex Deucher
2008-05-12R3/4/5: init pipe setup in drmAlex Deucher
Similar (broken) code in mesa needs to be removed
2008-05-12RADEON: cleanup radeon_do_engine_reset()Alex Deucher
2008-05-12R300+: fixup pixcache flushAlex Deucher
2008-05-12RS4xx: fix MCIND index maskAlex Deucher
2008-05-12RADEON: write AGP_BASE_2 on chips that support itAlex Deucher
2008-05-12R300+: fixup PURGE/FLUSH macrosAlex Deucher
2008-05-12Radeon IGP: merge RS4xx/RS6xx gart setupAlex Deucher
2008-05-12Radeon IGP: wrap MCIND accessAlex Deucher
first step in merging rs4xx/rs6xx gart setup