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AgeCommit message (Expand)Author
2005-11-11remove extra spacesDave Airlie
2005-11-11cleanup ioctl/max_ioctl to use header file for extern symbolsDave Airlie
2005-11-08Correct a LOR issue on FreeBSD by allocating temporary space and doing aEric Anholt
2005-11-08Initial port of savage to FreeBSD for the AGP and !ShadowStatus case. AddsEric Anholt
2005-11-08Correct a LOR on FreeBSD by allocating a temporary buffer and doing aEric Anholt
2005-11-08Fix FreeBSD DRM for latest MGA changes to agp support, which cleans thingsEric Anholt
2005-11-08Catch FreeBSD up to the pcie gart changes. Required minor modification toEric Anholt
2005-11-03Converts the remaining drm_agp_foo functions to be a drm_agp_foo andIan Romanick
2005-10-22via: Sync via_drm.h with 3D driver. Bump via patchlevel and date.Thomas Hellstrom
2005-10-20fix G550 cardsDave Airlie
2005-10-20via and r300 still need installed reg headers.Adam Jackson
2005-10-20via: PCI DMA bugfixes and DOS due to too many mapped pages checks.Thomas Hellstrom
2005-10-20dma access also needs some workDave Airlie
2005-10-20the old init path needs to set WAGP_ENABLE by defaultDave Airlie
2005-10-14Doig a full clean up from mga_do_dma_bootstrap whenIan Romanick
2005-10-14Fixed a cut-and-paste bug that could cause an oops in mga_do_cleanup_dmaIan Romanick
2005-10-13Add X300 RV370Dave Airlie
2005-10-06Skeleton nv drm driver, to enable DMA in EXA. (Lars Knoll, minor updates byAdam Jackson
2005-09-30Add support to turn writeback off via radeon module optionDave Airlie
2005-09-30fix pci overriding from userspaceDave Airlie
2005-09-25Add the via PCI DMA blit code.Thomas Hellstrom
2005-09-25hopefully fix server recycling on PCIEDave Airlie
2005-09-12add some pci express chipsDave Airlie
2005-09-12make PCI Express work on 64-bit machines, thanks to Alex Deucher (agd5f)Dave Airlie
2005-09-11Add GART in FB support for ati pcigart, and PCIE support for r300Dave Airlie
2005-09-09Add support for GL_ATI_fragment_shader, new packets R200_EMIT_PP_AFS_0/1,Roland Scheidegger
2005-09-09Add another R300 PCI id. Submitted by: Daniel EstévezVladimir Dergachev
2005-09-03convert ioctl flags to use flags instead of separate intsDave Airlie
2005-08-26- Don't try to allocate mappings of less than a PAGE_SIZE in MGA DMA code.Eric Anholt
2005-08-25Add missing .cvsignore files for autotoolery.Eric Anholt
2005-08-22remove i915_pm code as it causes too many issues with current softwareAlan Hourihane
2005-08-21We don't need to install all the internal headers files only drm.h andDave Airlie
2005-08-20Fix silly install issue by moving the header install rules for shared-coreAdam Jackson
2005-08-17commit toggle switch to make Linux drm_handle_t unsigned intDave Airlie
2005-08-16add Egberts 32/64 bit patch (its in kernel already...)Dave Airlie
2005-08-15Port the VIA DRM to FreeBSD. Original patch by Jake, with some cleanup byEric Anholt
2005-08-14VIA bugvixes by Joris van Rantwijk Initial commit.Thomas Hellstrom
2005-08-12Reverting the previous via security-fix commit, since the assumption ofThomas Hellstrom
2005-08-10Security fix on via: Checking that the specified context belongs to theThomas Hellstrom
2005-08-09Make sure savage has 3rd ioctl parameterJon Smirl
2005-08-07make some functions static in the savage drm driverDave Airlie
2005-08-07fix ioctl in r128 drm direction from Egbert Eich.Dave Airlie
2005-08-05Rename the driver hooks in the DRM to something a little moreEric Anholt
2005-08-04Mark some radeon init variables deprecated. These used to be passed in butJon Smirl
2005-08-04Split the control of master vs root priv. Everything is still marked asJon Smirl
2005-08-04Whitespace fixups.Eric Anholt
2005-08-04Fix the MGA driver on BSD by passing in the proper chipset flags to theEric Anholt
2005-08-04Add a debugging error message from testing new MGA code on BSD.Eric Anholt
2005-07-28Fix issues with buffer aging when more than one dma buffer is discarded inEric Anholt
2005-07-27Correct a couple of descriptions of files in comments (were justEric Anholt
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-06 14:28:58 +0000
0008 #define RADEON_UPLOAD_MASKS 0x00000010 #define RADEON_UPLOAD_VIEWPORT 0x00000020 #define RADEON_UPLOAD_SETUP 0x00000040 #define RADEON_UPLOAD_TCL 0x00000080 #define RADEON_UPLOAD_MISC 0x00000100 #define RADEON_UPLOAD_TEX0 0x00000200 #define RADEON_UPLOAD_TEX1 0x00000400 #define RADEON_UPLOAD_TEX2 0x00000800 #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ #define RADEON_REQUIRE_QUIESCENCE 0x00010000 #define RADEON_UPLOAD_ALL 0x0001ffff #define RADEON_FRONT 0x1 #define RADEON_BACK 0x2 #define RADEON_DEPTH 0x4 /* Primitive types */ #define RADEON_POINTS 0x1 #define RADEON_LINES 0x2 #define RADEON_LINE_STRIP 0x3 #define RADEON_TRIANGLES 0x4 #define RADEON_TRIANGLE_FAN 0x5 #define RADEON_TRIANGLE_STRIP 0x6 /* Vertex/indirect buffer size */ #define RADEON_BUFFER_SIZE 65536 /* Byte offsets for indirect buffer data */ #define RADEON_INDEX_PRIM_OFFSET 20 #define RADEON_HOSTDATA_BLIT_OFFSET 32 #define RADEON_SCRATCH_REG_OFFSET 32 /* Keep these small for testing */ #define RADEON_NR_SAREA_CLIPRECTS 12 /* There are 2 heaps (local/AGP). Each region within a heap is a * minimum of 64k, and there are at most 64 of them per heap. */ #define RADEON_LOCAL_TEX_HEAP 0 #define RADEON_AGP_TEX_HEAP 1 #define RADEON_NR_TEX_HEAPS 2 #define RADEON_NR_TEX_REGIONS 64 #define RADEON_LOG_TEX_GRANULARITY 16 #define RADEON_MAX_TEXTURE_LEVELS 11 #define RADEON_MAX_TEXTURE_UNITS 3 #endif /* __RADEON_SAREA_DEFINES__ */ typedef struct { unsigned int red; unsigned int green; unsigned int blue; unsigned int alpha; } radeon_color_regs_t; typedef struct { /* Context state */ unsigned int pp_misc; /* 0x1c14 */ unsigned int pp_fog_color; unsigned int re_solid_color; unsigned int rb3d_blendcntl; unsigned int rb3d_depthoffset; unsigned int rb3d_depthpitch; unsigned int rb3d_zstencilcntl; unsigned int pp_cntl; /* 0x1c38 */ unsigned int rb3d_cntl; unsigned int rb3d_coloroffset; unsigned int re_width_height; unsigned int rb3d_colorpitch; unsigned int se_cntl; /* Vertex format state */ unsigned int se_coord_fmt; /* 0x1c50 */ /* Line state */ unsigned int re_line_pattern; /* 0x1cd0 */ unsigned int re_line_state; unsigned int se_line_width; /* 0x1db8 */ /* Bumpmap state */ unsigned int pp_lum_matrix; /* 0x1d00 */ unsigned int pp_rot_matrix_0; /* 0x1d58 */ unsigned int pp_rot_matrix_1; /* Mask state */ unsigned int rb3d_stencilrefmask; /* 0x1d7c */ unsigned int rb3d_ropcntl; unsigned int rb3d_planemask; /* Viewport state */ unsigned int se_vport_xscale; /* 0x1d98 */ unsigned int se_vport_xoffset; unsigned int se_vport_yscale; unsigned int se_vport_yoffset; unsigned int se_vport_zscale; unsigned int se_vport_zoffset; /* Setup state */ unsigned int se_cntl_status; /* 0x2140 */ #ifdef TCL_ENABLE /* TCL state */ radeon_color_regs_t se_tcl_material_emmissive; /* 0x2210 */ radeon_color_regs_t se_tcl_material_ambient; radeon_color_regs_t se_tcl_material_diffuse; radeon_color_regs_t se_tcl_material_specular; unsigned int se_tcl_shininess; unsigned int se_tcl_output_vtx_fmt; unsigned int se_tcl_output_vtx_sel; unsigned int se_tcl_matrix_select_0; unsigned int se_tcl_matrix_select_1; unsigned int se_tcl_ucp_vert_blend_ctl; unsigned int se_tcl_texture_proc_ctl; unsigned int se_tcl_light_model_ctl; unsigned int se_tcl_per_light_ctl[4]; #endif /* Misc state */ unsigned int re_top_left; /* 0x26c0 */ unsigned int re_misc; } drm_radeon_context_regs_t; /* Setup registers for each texture unit */ typedef struct { unsigned int pp_txfilter; unsigned int pp_txformat; unsigned int pp_txoffset; unsigned int pp_txcblend; unsigned int pp_txablend; unsigned int pp_tfactor; unsigned int pp_border_color; #ifdef CUBIC_ENABLE unsigned int pp_cubic_faces; unsigned int pp_cubic_offset[5]; #endif } drm_radeon_texture_regs_t; typedef struct { unsigned char next, prev; unsigned char in_use; int age; } drm_radeon_tex_region_t; typedef struct { /* The channel for communication of state information to the kernel * on firing a vertex buffer. */ drm_radeon_context_regs_t context_state; drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; unsigned int dirty; unsigned int vertsize; unsigned int vc_format; /* The current cliprects, or a subset thereof. */ drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS]; unsigned int nbox; /* Counters for client-side throttling of rendering clients. */ unsigned int last_frame; unsigned int last_dispatch; unsigned int last_clear; drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; int tex_age[RADEON_NR_TEX_HEAPS]; int ctx_owner; } drm_radeon_sarea_t; /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmRadeon.h) */ typedef struct drm_radeon_init { enum { RADEON_INIT_CP = 0x01, RADEON_CLEANUP_CP = 0x02 } func; unsigned long sarea_priv_offset; int is_pci; int cp_mode; int agp_size; int ring_size; int usec_timeout; unsigned int fb_bpp; unsigned int front_offset, front_pitch; unsigned int back_offset, back_pitch; unsigned int depth_bpp; unsigned int depth_offset, depth_pitch; unsigned long fb_offset; unsigned long mmio_offset; unsigned long ring_offset; unsigned long ring_rptr_offset; unsigned long buffers_offset; unsigned long agp_textures_offset; } drm_radeon_init_t; typedef struct drm_radeon_cp_stop { int flush; int idle; } drm_radeon_cp_stop_t; typedef struct drm_radeon_fullscreen { enum { RADEON_INIT_FULLSCREEN = 0x01, RADEON_CLEANUP_FULLSCREEN = 0x02 } func; } drm_radeon_fullscreen_t; #define CLEAR_X1 0 #define CLEAR_Y1 1 #define CLEAR_X2 2 #define CLEAR_Y2 3 #define CLEAR_DEPTH 4 typedef union drm_radeon_clear_rect { float f[5]; unsigned int ui[5]; } drm_radeon_clear_rect_t; typedef struct drm_radeon_clear { unsigned int flags; unsigned int clear_color; unsigned int clear_depth; unsigned int color_mask; unsigned int depth_mask; drm_radeon_clear_rect_t *depth_boxes; } drm_radeon_clear_t; typedef struct drm_radeon_vertex { int prim; int idx; /* Index of vertex buffer */ int count; /* Number of vertices in buffer */ int discard; /* Client finished with buffer? */ } drm_radeon_vertex_t; typedef struct drm_radeon_indices { int prim; int idx; int start; int end; int discard; /* Client finished with buffer? */ } drm_radeon_indices_t; typedef struct drm_radeon_tex_image { unsigned int x, y; /* Blit coordinates */ unsigned int width, height; const void *data; } drm_radeon_tex_image_t; typedef struct drm_radeon_texture { int offset; int pitch; int format; int width; /* Texture image coordinates */ int height; drm_radeon_tex_image_t *image; } drm_radeon_texture_t; typedef struct drm_radeon_stipple { unsigned int *mask; } drm_radeon_stipple_t; typedef struct drm_radeon_indirect { int idx; int start; int end; int discard; } drm_radeon_indirect_t; #endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-06 14:28:57 +0000