| Age | Commit message (Collapse) | Author |
|---|
|
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
|
|
The kernel will now write data to the DRM fd for various event types if
requested. Currently, the only supported event is a vblank event: it contains
the vblank count for the event as well as a timestamp from when the event
ocurred. Since the DRM fd is now pollable, it's easy to integrate into
existing event loops.
|
|
|
|
|
|
Set the DONTNEED flag on cached buffers so that the kernel is free to
discard those when under memory pressure.
[anholt: This takes firefox-talos-gfx time from ~62 seconds to ~65 seconds
on my GM965, but it seems like a hit worth taking for the improved
functionality from saving memory]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
|
|
Kenrels doesn't expose this ioctl
|
|
|
|
airlied: modified the interface to drop busy return value, just return
it normally, also fixed int->uint32_t for domain
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
|
|
|
|
|
|
|
|
this rounds out the r6xx/r7xx stuff in radeon_drm.h
|
|
This lets us libdrm from master for r6xx/r7xx 3d
|
|
|
|
|
|
Signed-off-by: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
|
|
requires --enable-radeon-experimental-api for now
|
|
Normal map() should operate as before, and map_range()/map_flush() should
give correct results but lacking any performance difference from map().
Nothing exiting being done here yet, but the interface is a good start.
|
|
No idea what this reg does.. NVIDIA put 0x802 into it on some chips, the
criteria aren't too clear on when they do that however. Hopefully 0x800
will work everywhere...
|
|
|
|
Patch allows the backlight to be manipulated under gnome on apple powerpc
based NV30 machines. It works fine on my powerbook, and should also work
for older NV17/NV18 machines.
Note that older powerpc specific tools (pbbuttonsd) have some problems with
this implementation (because the device is not yet there at the start time
of the daemon, and the code makes incorrect assumptions about the max
brightness values). However, IMHO these things can and should be addressed
in the daemon.
Some style/warning fixes applied by Stuart Bennett <stuart@freedesktop.org>
|
|
This wraps the new DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID ioctl,
allowing applications to discover the pipe number corresponding
to a given CRTC ID. This is necessary for doing pipe-specific
operations such as waiting for vblank on a given CRTC.
|
|
|
|
|
|
|
|
|
|
IGPs
|
|
NV04 had a PFB_FIFO_DATA at the same address, which we don't use, so
remove it to reduce confusion
|
|
We also don't support anything old enough to need tsleep.
|
|
NV04 was completely busted. Push buffers were getting allocated at the
end of VRAM, overwriting PRAMIN. So, it turns out PRAMIN is in VRAM on
all chips. Question answered!
|
|
This also means dropping the DRM_ODD_MM_COMPAT case.
Signed-off-by: Pekka Paalanen <pq@iki.fi>
|
|
|
|
|
|
|
|
|
|
-Remove the old TTM interface
-Move register definitions to i915_reg.h
-Rework the irq handler
|
|
|
|
Several nvidia-based systems don't support backlight control via the
standard ACPI control mechanisms. Instead, it's necessary for the driver
to modify the backlight control registers directly. This patch adds
support for determining whether the registers appear to be in use, and
if so registers a kernel backlight device to control them. The backlight
can then be controlled via existing userspace tools.
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
|
|
|
|
|
|
NVIDIA do this fun little sequence after updating the PRAMIN page tables.
On 9xxx chips, none of the PRAMIN BAR bindings (except the initial one)
worked, hence the majority of the setup needed to create a channel
ended up in the wrong place, causing all sorts of fun.
This is done by NVIDIA on nv8x chips also, so we'll do it for them too,
even though they appear to work without it.
|
|
It won't work yet, just like the other 9xxx chips. Real soon now :)
|
|
I'm not 100% sure that the nv94 one we were using won't work. The context
layouts are identical (well.. same ctxprog, so of course!), only a couple
of registers differ. But, be safe until we actually get some 9xxx chips
working.
|
|
Suprisingly the card still worked without this...
|
|
Our PFIFO/PGRAPH context save/load functions don't really work well
(at all?) on nv5x yet. Depending on what random state the card is
in before the drm loads, fbcon probably won't work correctly.
Luckily we've setup the GPU in such a way that it'll actually do a
hw context switch for the first context. Not sure of how successful
this'd be currently on the older chips (actually, pretty sure it won't
work), so NV50 only for now.
|
|
Fixes nouveau_ioctl_mem_free Oops
|
|
Use of the new bits is guarded with a mm_enabled=0 hardcode.
|
|
|
|
Bug exposed by DDX change d9da090c
|
|
|
