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2007-01-18add missing quadro idDave Jones
2007-01-17nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.Jeremy Kolb
Hook into nv20 pgraph switching functions (they're identical for nv3x). Actually call nv30_pgraph_context_init so the ctx_table is allocated. Thanks to Carlos Martin for the help.
2007-01-14nouveau: opps nv20 ctx ramin size was wrongMatthieu Castet
2007-01-13nouveau: opps restored the wrong channelMatthieu Castet
2007-01-13nouveau: nv20 graph ctx switch.Matthieu Castet
Untested...
2007-01-13nouveau: first step to make graph ctx worksMatthieu Castet
It is still not working, but now we could use some 3D commands without needed to run nvidia blob before.
2007-01-13nouveau: add and indent pgraph regsMatthieu Castet
2007-01-13nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value.Stephane Marchesin
2007-01-12nouveau : remove useless init : we clear RAMIN beforeMatthieu Castet
2007-01-12Delay for a usec while spinning waiting for ring buffer space.Haihao Xiang
This means the loop will wait up to ~10ms for ring buffer space to become available, rather than just however long it takes to check the space 10000 times. This matches other drivers' behavior when waiting for ring buffer/fifo space.
2007-01-12nouveau: get nv30 context switching to work.Jeremy Kolb
* Pulled in some registers from nv10reg.h. Needed for context switching. * Filled in nv30 graphics context (based on nv40_graph.c). * Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-11radeon: Fix u32 overflows when determining AGP base address in card space.Michel Dänzer
The overflows could lead to the AGP aperture overlapping the framebuffer area in the card's address space when the latter is located at the very end of the 32 bit address space, which would result in a freeze on X server startup, probably because the card read commands from the framebuffer instead of from AGP. See http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=392915 .
2007-01-09novueau: try resource 3 if resource 2 is 0 lengthDave Airlie
This happens on my NV43 PPC
2007-01-08nouveau: fix nv4a context size.Stephane Marchesin
2007-01-08nouveau: nv4a context support.Stephane Marchesin
2007-01-08Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drmStephane Marchesin
2007-01-08nouveau: oopsBen Skeggs
2007-01-08nouveau: nv43 context stuffBen Skeggs
2007-01-08nouveau: fix a stupid bug from me.Stephane Marchesin
2007-01-08nouveau: avoid allocating vram that's used as instance memory.Ben Skeggs
2007-01-08nouveau: map pci resource 2 on >=nv40Ben Skeggs
2007-01-06Revert i915 drm driver name to i915; miniglx doesn't work otherwiseKeith Packard
Yes, this driver supports the new memory manager, that is indicated by the version number being >= 1.7.
2007-01-06Bump i915 minor for ARB_OC ioctlWang Zhenyu
2007-01-06i915: ARB_Occlusion_query(MMIO ioctl) support.Zou Nan hai
This adds a new ioctl for passing counter information from the chip back to applications, these counters include the data needed to perform OC.
2007-01-06nouveau: get c51 doing glxgears without the binary driver's help.Ben Skeggs
2007-01-06nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load.Ben Skeggs
2007-01-05nouveau: oops, we don't need OS_HAS_MTRR actually.Stephane Marchesin
2007-01-05Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drmStephane Marchesin
2007-01-05nouveau: Add an mtrr over the whole FBStephane Marchesin
2007-01-05Merge branch 'master' of git+ssh://matc@git.freedesktop.org/git/mesa/drm/Matthieu Castet
2007-01-05Add basic pgraph context for nv10.Matthieu Castet
It only fake a context switch : pgraph state are not save/restored.
2007-01-05Cleanup the nv04 fifo code a bit.Stephane Marchesin
2007-01-02i915: Fix a DRM_ERROR that should be DRM_DEBUG.Michel Dänzer
It would clutter up the kernel output in a situation which is legitimate before X.org 7.2 and handled correctly by the 3D driver.
2007-01-02nouveau: oops, forgot to free RAMIN..Ben Skeggs
2007-01-02nouveau: Hookup nv40_graph_init.Ben Skeggs
Now I can get 3D + working grctx switching on my NV40 without the binary driver initialising the card first. However, this change also breaks 3D on my C51 even *with* the binary driver's help. So, it's likely that the weird voodoo is card-specific.
2007-01-02nouveau: Hook up grctx code for NV4x.Ben Skeggs
This is enough to get grctx switching going on my NV40 and C51 after the binary driver has initialised the card first. Bumping the drm patchlevel because the ddx needs some modifications to have NV4x work at all with these changes.
2007-01-02nouveau: Add nv40-specific PGRAPH code, not hooked up yet.Ben Skeggs
2007-01-02nouveau: Only clobber PFIFO if no channels are already alloc'dBen Skeggs
With this change the GPU is responsible for doing the channel switch itself. This is needed for the upcoming NV4x PGRAPH context work as we don't yet know enough to manually swap PGRAPH contexts.
2006-12-28Add some new via chipsets.Thomas Hellstrom
Disable 3D functionality and AGP DMA for chipsets with the DX9 3D engine.
2006-12-27Leftover from previous commit.Thomas Hellstrom
2006-12-27Allow for non-power-of-two texture pitch alignment.Thomas Hellstrom
2006-12-27nouveau: return the *actual* type of memory alloc'd to userspaceBen Skeggs
2006-12-26nouveau: Alloc cmdbuf for each channel individuallyBen Skeggs
2006-12-21nouveau: save/restore endianness flag on FIFO switchBen Skeggs
This makes my G5 survive glxinfo and nouveau_demo - airlied
2006-12-20Some via PCI posting flushes.Thomas Hellstrom
2006-12-20Merge branch 'nouveau-1'Dave Airlie
2006-12-19fixup i915 return values from kernelDave Airlie
2006-12-19fix comment in r128Dave Airlie
2006-12-19fix some sizes in sis_drv.hDave Airlie
2006-12-19remove inline from large functionDave Airlie
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