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2006-11-04Add some getparams.Stephane Marchesin
2006-11-04Move the context object creation flag handling to the drm.Stephane Marchesin
2006-10-18Remove hack which delays activation of a additional channel. The previously ↵Ben Skeggs
active channel's state is saved to RAMFC before PFIFO gets clobbered.
2006-10-18Oops, we have more than 4 subchannels..Ben Skeggs
2006-10-17Useful output on a FIFO error interrupt.Ben Skeggs
2006-10-17typoBen Skeggs
2006-10-17NV40: *Now* fifo ctx switching works for me..Ben Skeggs
Ok, I lied before.. it was a fluke it worked and required magic to repeat it.. It actually helps to fill in RAMFC entries in the correct place. The code also clears RAMIN entirely instead of just the hash-table.
2006-10-17NV40: FIFO context switching now WorksForMe(tm)Ben Skeggs
2006-10-17Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup ↵Ben Skeggs
code a bit.
2006-10-17Some info on NV40's RAMFCBen Skeggs
2006-10-15Merge branch 'master' of git://anongit.freedesktop.org/git/mesa/drm into ↵Stephane Marchesin
nouveau-1
2006-10-14Again more work on context switches. They work, sometimes. And when they do ↵Stephane Marchesin
they seem to screw up the PGRAPH state.
2006-10-14Add the missing breaks.Stephane Marchesin
2006-10-13Fix the fifo context size on nv10, nv20 and nv30.Stephane Marchesin
2006-10-14Fix some randomness in activating a second channel on NV40 (odd GET/PUT ↵Ben Skeggs
vals). Ch 1 GET now advances, but no ctx_switch.
2006-10-12Oops.Stephane Marchesin
2006-10-12Still more work on the context switching code.Stephane Marchesin
2006-10-12More work on the context switch code. Still doesn't work. I'm mostly ↵Stephane Marchesin
convinced it's an initialization issue.
2006-10-11Context switching work.Stephane Marchesin
Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX.
2006-10-10only allow specific type-3 packets to pass the verifier instead of all for ↵Roland Scheidegger
r100/r200 as others might be unsafe (r300 already does this), and add checking for these we need but aren't safe. Check the RADEON_CP_INDX_BUFFER packet on both r200 and r300 as it isn't safe neither.
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #4.George Sapountzis
mach64_state.c: convert the DRM_MACH64_BLIT ioctl to submit a pointer to user-space memory rather than a DMA buffer index, similar to DRM_MACH64_VERTEX. This change allows the DDX to map the DMA buffers read-only and eliminate a security problem where a client can alter the contents of the DMA buffer after submission to the DRM. This change also affects the DRI/DRM interface. Performace-wise, it basically affects PCI mode where I get a ~12% speedup for some Mesa demos I tested. This is mainly due to eliminating an ioctl for allocating the DMA buffer. mach64_dma.c: move the responsibility for allocating memory for the DMA ring in PCI mode to the DDX. This change affects the DDX/DRM interface and unifies a couple of PCI/AGP code paths for ring memory in the DRM. Bump the mach64 DRM version major and date.
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #3.George Sapountzis
Add DRM_PCI_BUFFER_RO flag for mapping PCI DMA buffer read-only. An additional flag is needed, since PCI DMA buffers do not have an associated map.
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #2.George Sapountzis
Factor out from mach64_dma_dispatch_vertex() the code to reclaim an unsed buffer, in preperation for using it in mach64_dma_dispatch_blit() also.
2006-10-02Bug 6242: [mach64] Use private DMA buffers, part #1.George Sapountzis
Factor out from mach64_freelist_get() the code to reclaim a completed buffer, this is to improve readability for me.
2006-10-02Bug 6209: [mach64] AGP DMA buffers not mapped correctly.George Sapountzis
Map the DMA buffers from the same linear address as the vertex bufs. If dev->agp_buffer_token is not set, mach64 drm maps the DMA buffers from linear address 0x0.
2006-10-02Fix type of second argument to spin_lock_irqsave().Michel Dänzer
2006-10-02drm_rmdraw: Declare id and idx as signed so testing for < 0 works as intended.Felix Kühling
2006-09-29i915: Only schedule vblank tasklet if there are scheduled swaps pending.Michel Dänzer
This fixes issues on X server startup with versions of xf86-video-intel that enable the IRQ before they have a context ID.
2006-09-28i915: Avoid mis-counting vblank interrupts when they're only enabled for pipe A.Michel Dänzer
It looks like 'after a while', I915REG_INT_IDENTITY_R for some reason always has VSYNC_PIPEB_FLAG set in the interrupt handler, even though pipe B is disabled. So we only increase dev->vbl_received if the corresponding bit is also set in dev->vblank_pipe.
2006-09-28i915: Bump minor for swap scheduling ioctl and secondary vblank support.Michel Dänzer
2006-09-28i915_vblank_swap: Add support for DRM_VBLANK_NEXTONMISS.Michel Dänzer
2006-09-28Only return EBUSY after we've established we need to schedule a new swap.Michel Dänzer
2006-09-28Core vsync: Add flag DRM_VBLANK_NEXTONMISS.Michel Dänzer
When this flag is set and the target sequence is missed, wait for the next vertical blank instead of returning immediately.
2006-09-28Fix 'sequence has passed' condition in i915_vblank_swap().Michel Dänzer
2006-09-28Add SAREA fileds for determining which pipe to sync window buffer swaps to.Michel Dänzer
2006-09-28Make handling of dev_priv->vblank_pipe more robust.Michel Dänzer
Initialize it to default value if it hasn't been set by the X server yet. In i915_vblank_pipe_set(), only update dev_priv->vblank_pipe and call i915_enable_interrupt() if the argument passed from userspace is valid to avoid corrupting dev_priv->vblank_pipe on invalid arguments.
2006-09-28DRM_I915_VBLANK_SWAP ioctl: Take drm_vblank_seq_type_t instead of pipe number.Michel Dänzer
Handle relative as well as absolute target sequence numbers. Return error if target sequence has already passed, so userspace can deal with this situation as it sees fit. On success, return the sequence number of the vertical blank when the buffer swap is expected to take place. Also add DRM_IOCTL_I915_VBLANK_SWAP definition for userspace code that may want to use ioctl() instead of drmCommandWriteRead().
2006-09-28Change first valid DRM drawable ID to be 1 instead of 0.Michel Dänzer
This makes it easier for userspace to know when it needs to allocate an ID. Also free drawable information memory when it's no longer needed.
2006-09-28Add copyright notice.Michel Dänzer
2006-09-28i915: Add ioctl for scheduling buffer swaps at vertical blanks.Michel Dänzer
This uses the core facility to schedule a driver callback that will be called ASAP after the given vertical blank interrupt with the HW lock held.
2006-09-28Locking and memory management fixes.Michel Dänzer
2006-09-28Export drm_get_drawable_info symbol from core.Michel Dänzer
2006-09-28Only reallocate cliprect memory if the number of cliprects changes.Michel Dänzer
Also improve diagnostic output.
2006-09-28Add support for tracking drawable information to coreMichel Dänzer
Actually make the existing ioctls for adding and removing drawables do something useful, and add another ioctl for the X server to update drawable information. The only kind of drawable information tracked so far is cliprects.
2006-09-28Add support for secondary vertical blank interrupt to i915 driver.Michel Dänzer
When the vertical blank interrupt is enabled for both pipes, pipe A is considered primary and pipe B secondary. When it's only enabled for one pipe, it's always considered primary for backwards compatibility.
2006-09-28Add support for secondary vertical blank interrupt to DRM core.Michel Dänzer
2006-09-22bug 7092 : add pci ids for mach64 in Dell poweredge 4200Anish Mistry
2006-09-20do a TCL state flush before accessing VAP_CNTL to prevent lockups on r200 ↵Roland Scheidegger
when enabling/disabling vertex programs
2006-09-17Add pciid for GeForce Go 6150 (0x0244).Ben Skeggs
2006-09-15Use register writes instead of BITBLT_MULTI packets for buffer swap blits.Michel Dänzer
This takes up two more ring buffer entries per rectangle blitted but makes sure the blit is performed top to bottom, reducing the likelyhood of tearing.
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