| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-02-11 | drm/nv50: add context info for nv98 | Ben Skeggs | |
| It won't work yet, just like the other 9xxx chips. Real soon now :) | |||
| 2009-02-10 | drm/nv50: use a slightly different initial context for nv96 | Ben Skeggs | |
| I'm not 100% sure that the nv94 one we were using won't work. The context layouts are identical (well.. same ctxprog, so of course!), only a couple of registers differ. But, be safe until we actually get some 9xxx chips working. | |||
| 2009-01-27 | nv50: support chipset NV96 | Ben Skeggs | |
| ctxprog seen in okias' trace identical to one we use on NV94, assuming the initial context values for NV94 will work here too. | |||
| 2008-11-23 | nv50: support NV94 chipset | Ben Skeggs | |
| 2008-10-28 | nv50: move context-related tables a separate header file | Ben Skeggs | |
| This turns the various nvXX_graph_init_ctxvals() methods into tables, and speeds up compliation of nv50_graph.c quite a bit. This has bothered me for a while, but others are complaining now so it's time to fix it :) | |||
| 2008-09-17 | nv50: add initial context for chipset 0xaa | Ben Skeggs | |
| This just doesn't look right.. | |||
| 2008-09-17 | nv50: add initial context to match ctxprog for chipset 0x50 | Ben Skeggs | |
| 2008-09-17 | nv50: add ctxprog for chipset 0x50 | Ben Skeggs | |
| 2008-09-17 | nv50: add ctxprog for chipset 0xaa | Ben Skeggs | |
| 2008-09-17 | nv50: add support for chipset 0x92 | Ben Skeggs | |
| 2008-05-02 | nouveau: guard against channels potentially not having a context, fix nv50 | Ben Skeggs | |
| 2008-05-01 | nv50: I cave... Add nv84 initial context values. | Ben Skeggs | |
| I swore I'd actually do this properly and not go the horrible route we did with nv4x, but I won't get around to it just yet with so many *actually* interesting things to do first.. One day. Since someone already added nv86, why not! | |||
| 2008-03-30 | nouveau: forgot to add a break | Maarten Maathuis | |
| 2008-03-30 | nouveau: Add ctx values for nv86. | Maarten Maathuis | |
| - Note that this may not work for all nv86. | |||
| 2008-01-07 | nv50: more small changes | Ben Skeggs | |
| 2008-01-07 | nv50: abort on chips without ctx ucode | Ben Skeggs | |
| 2008-01-07 | nv50: some needed ctx vals | Ben Skeggs | |
| 2008-01-07 | nv50: some cleanups + small changes | Ben Skeggs | |
| 2008-01-06 | nouveau: Add ctx_voodoo for NV86 | Jeremy Kolb | |
| 2007-11-05 | drm: remove lots of spurious whitespace. | Dave Airlie | |
| Kernel "cleanfile" script run. | |||
| 2007-08-08 | nouveau/nv50: hack up initial channel context from current state | Ben Skeggs | |
| We really should be providing static values like the nv40 PGRAPH code does, however, this will do for now to keep X at least working. | |||
| 2007-08-08 | nouveau: enable/disable engine-specific interrupts in _init()/_takedown() | Ben Skeggs | |
| All interrupts are still masked by PMC until init is finished. | |||
| 2007-08-06 | nouveau: Pass channel struct around instead of channel id. | Ben Skeggs | |
| 2007-07-20 | Remove DRM_ERR OS macro. | Eric Anholt | |
| This was used to make all ioctl handlers return -errno on linux and errno on *BSD. Instead, just return -errno in shared code, and flip sign on return from shared code to *BSD code. | |||
| 2007-07-17 | nouveau: G8x PCIEGART | Ben Skeggs | |
| Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART support for G8X using the current mm has been hacked on top of it. | |||
| 2007-07-13 | nouveau: nuke internal typedefs, and drm_device_t use. | Ben Skeggs | |
| 2007-07-09 | nouveau/nv50: Initial channel/object support | Ben Skeggs | |
| Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80. | |||
| 2007-06-28 | nouveau/nv50: skeletal backend | Ben Skeggs | |
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index : renesas/drm.git | |
| libdrm, cloned from git://anongit.freedesktop.org/mesa/drm | Laurent Pinchart |
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