Age | Commit message (Collapse) | Author | |
---|---|---|---|
2007-05-12 | nouveau : nv10 graph clipping values were forgoten in ddx to drm commit | Matthieu Castet | |
2007-04-10 | nouveau: nv10 per channel init from ddx | Matthieu Castet | |
2007-04-01 | nouveau : nv10 ctx switch fix | Matthieu Castet | |
restoring NV10_PGRAPH_CTX_SWITCH1 now works | |||
2007-04-01 | nouveau : set the correct PGRAPH_CTX_CONTROL register | Matthieu Castet | |
"5a072f32 (Stephane Marchesin 2007-02-03 04:57:06 +0100" broke nv10 ctx switch by setting wrong PGRAPH_CTX_CONTROL reg | |||
2007-03-26 | nouveau: move card initialisation into the drm | Ben Skeggs | |
The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E | |||
2007-02-03 | nouveau: fix nv04 graph routines for new register names. | Stephane Marchesin | |
2007-02-03 | nouveau: rename registers to their proper names. | Stephane Marchesin | |
2007-02-02 | nouveau: nv ctx switch opps the size of array was wrong | Matthieu Castet | |
2007-02-02 | nouveau: nv10 ctx switch, some regs are nv17+ only | Matthieu Castet | |
2007-01-28 | nouveau: determine chipset type at startup, instead of every time we use it. | Ben Skeggs | |
2007-01-26 | make works ctx switch on nv10. | Matthieu Castet | |
2007-01-26 | nouveau: oops, wrong indexing in nv17 regs | Patrice Mandin | |
2007-01-26 | nouveau: read gpu type once | Patrice Mandin | |
2007-01-26 | nouveau: only save/restore nv17 regs on nv17,18 hw | Patrice Mandin | |
2007-01-26 | nouveau: add some nv10 pgraph defines | Patrice Mandin | |
2007-01-13 | nouveau: first step to make graph ctx works | Matthieu Castet | |
It is still not working, but now we could use some 3D commands without needed to run nvidia blob before. |