| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2008-02-02 | nouveau: NV40 can/should now be able to run after the blob. | Maarten Maathuis | |
| - Moved the fix from the ddx to drm, because it seemed more appropriate. - Don't be shy, report if it works for you or not. | |||
| 2008-01-04 | [PATCH] nouveau: reset AGP on init for < nv40 | Stuart Bennett | |
| This is necessary for AGP to work after running bios init scripts on nv3x, and is seen in mmio traces of all cards (nv04-nv4x) I'm not making the equivalent change to nv40_mc.c, as early cards (6200, 6800gt) use the 0x000018XX PBUS and later cards use the 0x000880XX PBUS and I don't know the effects of using the wrong one | |||
| 2007-11-14 | nouveau: Also wait until CACHE1 gets emptied. | Ben Skeggs | |
| 2007-11-14 | nouveau: store user control reg offsets in channel struct | Ben Skeggs | |
| 2007-11-14 | nouveau: funcs to determine active channel on PFIFO. | Ben Skeggs | |
| 2007-11-05 | drm: remove lots of spurious whitespace. | Dave Airlie | |
| Kernel "cleanfile" script run. | |||
| 2007-10-10 | nouveau : nv10 and nv04 PGRAPH_NSTATUS are different | Matthieu Castet | |
| 2007-10-10 | nouveau: try to fix big endian. | Stephane Marchesin | |
| 2007-09-30 | nouveau : nv20_graph replace nouveau_graph_wait_idle by nouveau_wait_for_idle | Matthieu Castet | |
| Also clean PGRAPH_CHANNEL macros | |||
| 2007-09-10 | nouveau: nv10: add combiner registers | Patrice Mandin | |
| 2007-08-26 | nouveau : add NV04_PGRAPH_TRAPPED_ADDR definition | Matthieu Castet | |
| - fix offset for nv04 - use it in nv10 graph ctx switch for getting next channel - dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+ | |||
| 2007-08-22 | nouveau/nv40: Dump extra info on ucode state if ctx switch fails. | Ben Skeggs | |
| 2007-08-10 | nouveau/nv50: demagic instmem setup. | Ben Skeggs | |
| 2007-07-18 | nouveau: Add bitfield names for NSOURCE and NSTATUS. | Pekka Paalanen | |
| Name strings and pretty-printing in nouveau_graph_dump_trap_info(). | |||
| 2007-07-18 | nouveau: Replace 0x00400104 and 0x00400108 with names. | Pekka Paalanen | |
| NV03_PGRAPH_NSTATUS and NV03_PGRAPH_NSOURCE. The prefix NV03 is chosen because nv10reg.h had no versioned prefix, and the code using these registers does not check card_type. | |||
| 2007-07-11 | Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel. | Arthur Huillet | |
| 2007-07-09 | nouveau/nv50: Initial channel/object support | Ben Skeggs | |
| Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80. | |||
| 2007-06-28 | nouveau: name some regs | Ben Skeggs | |
| 2007-06-24 | nouveau: NV04 PFIFO engtab functions | Ben Skeggs | |
| 2007-06-24 | nouveau: NV4X PFIFO engtab functions | Ben Skeggs | |
| 2007-04-06 | nouveau: make a note about a bit that breaks some cards | Ben Skeggs | |
| 2007-03-26 | nouveau: move card initialisation into the drm | Ben Skeggs | |
| The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E | |||
| 2007-03-07 | nouveau: remove a hack that's not needed since the last interface change. | Ben Skeggs | |
| 2007-02-28 | nouveau: intrusive drm interface changes | Ben Skeggs | |
| graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING. | |||
| 2007-02-06 | nouveau: more work on the nv04 context switch code. | Stephane Marchesin | |
| 2007-02-03 | nouveau: cleanup the nv04 pgraph save/restore mechanism. | Stephane Marchesin | |
| 2007-02-03 | nouveau: rename registers to their proper names. | Stephane Marchesin | |
| 2007-02-03 | nouveau: add NV04 registers required for PGRAPH context switching. | Stephane Marchesin | |
| 2007-01-26 | nouveau: add extra pgraph registers | Patrice Mandin | |
| 2007-01-13 | nouveau: nv20 graph ctx switch. | Matthieu Castet | |
| Untested... | |||
| 2007-01-13 | nouveau: add and indent pgraph regs | Matthieu Castet | |
| 2007-01-13 | nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value. | Stephane Marchesin | |
| 2007-01-12 | nouveau: get nv30 context switching to work. | Jeremy Kolb | |
| * Pulled in some registers from nv10reg.h. Needed for context switching. * Filled in nv30 graphics context (based on nv40_graph.c). * Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work. | |||
| 2007-01-06 | nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load. | Ben Skeggs | |
| 2007-01-05 | Cleanup the nv04 fifo code a bit. | Stephane Marchesin | |
| 2006-11-28 | For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context. | Matthieu Castet | |
| When cleaning a fifo, we shouldn't assume everybody use nv40 ;) Fill DMA_SUBROUTINE fill correct value. | |||
| 2006-11-14 | Completely untested NV10/20/30 FIFO context switching changes. | Ben Skeggs | |
| 2006-11-14 | Restructure initialisation a bit. | Ben Skeggs | |
| - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO} | |||
| 2006-11-06 | fixup fifo size so it is page aligned | Dave Airlie | |
| 2006-10-18 | Remove hack which delays activation of a additional channel. The previously ↵ | Ben Skeggs | |
| active channel's state is saved to RAMFC before PFIFO gets clobbered. | |||
| 2006-10-17 | Useful output on a FIFO error interrupt. | Ben Skeggs | |
| 2006-10-17 | Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup ↵ | Ben Skeggs | |
| code a bit. | |||
| 2006-10-17 | Some info on NV40's RAMFC | Ben Skeggs | |
| 2006-10-12 | Still more work on the context switching code. | Stephane Marchesin | |
| 2006-10-11 | Context switching work. | Stephane Marchesin | |
| Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX. | |||
| 2006-08-27 | initial import of nouveau code from nouveau CVS | Dave Airlie | |
 |
index : renesas/drm.git | |
| libdrm, cloned from git://anongit.freedesktop.org/mesa/drm | Laurent Pinchart |
| summaryrefslogtreecommitdiff |