renesas/drm.git - libdrm, cloned from git://anongit.freedesktop.org/mesa/drm

Age	Commit message (Collapse)	Author
2006-11-28	For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.	Matthieu Castet
	When cleaning a fifo, we shouldn't assume everybody use nv40 ;) Fill DMA_SUBROUTINE fill correct value.
2006-11-14	Completely untested NV10/20/30 FIFO context switching changes.	Ben Skeggs

2006-11-14	Restructure initialisation a bit.	Ben Skeggs
	- Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is after RAM{FC,HT,RO}
2006-11-06	fixup fifo size so it is page aligned	Dave Airlie

2006-10-18	Remove hack which delays activation of a additional channel. The previously ↵	Ben Skeggs
	active channel's state is saved to RAMFC before PFIFO gets clobbered.
2006-10-17	Useful output on a FIFO error interrupt.	Ben Skeggs

2006-10-17	Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup ↵	Ben Skeggs
	code a bit.
2006-10-17	Some info on NV40's RAMFC	Ben Skeggs

2006-10-12	Still more work on the context switching code.	Stephane Marchesin

2006-10-11	Context switching work.	Stephane Marchesin
	Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX.
2006-08-27	initial import of nouveau code from nouveau CVS	Dave Airlie