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path: root/radeon/radeon_surface.c
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2015-04-28drm: remove drm_public macroEmil Velikov
Some compilers (like the Oracle Studio), require that the function declaration must be annotated with the same visibility attribute as the definition. As annotating functions with drm_public is no longer required just remove the macro. Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@canonical.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28drm: rename libdrm{,_macros}.hEmil Velikov
Provide a more meaningful name, considering what it does. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-01-19radeon: align r600/700 fmask to 128 X blocks.Dave Airlie
After much searching and empricial testing, and reading of things I've no justifcation for this fix, other than it really appears this is what the hw is doing or close enough. It makes sense that each entry in the FMASK corresponds to an entry in the CMASKm and the CMASK is organised into 128x128 blocks, but I can't find anything in any of the docs/info from AMD. But I've spent a lot of time on this, and this seems to be the simplest fix, in that we don't over allocate things too much, once this fix in place we can nuke the extra multiplier in mesa. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-29radeon: Always multiply pitch_bytes by nsamples, not by slice_ptMichel Dänzer
slice_pt is tileb[0] / tile_split, which isn't directly related to the pitch. This caused pitch_bytes to be too large in some cases. [0] Tile size in bytes Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-28radeon: use drm_mmap/drm_munmap wrappersEmil Velikov
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2014-08-25radeon: Fix surf->bankh init by default value when surf->tile_split == 0Maks Naumov
Signed-off-by: Maks Naumov <maksqwe1@ukr.net> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2014-08-04radeon: Use symbol visibility.Maarten Lankhorst
All the bof_* symbols are now no longer exported. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-07-29radeon: fix typo in sample split / fixes MSAA on HawaiiMarek Olšák
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-07-16radeon: Remove superfluous parentheses.Thomas Klausner
Signed-off-by: Thomas Klausner <wiz@NetBSD.org>
2014-05-02radeon: add Mullins chip familySamuel Li
Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-12-24radeon: avoid possible divide by 0 in surface managerAlex Deucher
Some users report hitting a divide by 0 with the tile split in certain apps. Tile_split shouldn't ever be 0 unless the surface structure was not properly initialized. I think there may be some cases where mesa uses an improperly initialized surface struct, but I haven't had time to track it down. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=72425 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-11-26radeon: Update unaligned offset for 2D->1D tiling transition on SIMichel Dänzer
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71983 Tested-by: Arek Ruśniak <arek.rusi@gmail.com>
2013-11-23radeon: handle P16 pipe configs for HawaiiMarek Olšák
2013-11-23radeon: don't overallocate stencil by 4 on SI and CIKMichel Dänzer
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2013-11-23radeon: implement 2D tiling for CIKMarek Olšák
Bug fixes and simplification by Marek. We have to use the tile index of 0 for non-MSAA depth-stencil after all. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-23radeon: fix mipmap level 0 and 1 alignment for SI and CIKMichel Dänzer
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-13radeon: add hawaii chip familyAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-29radeon: fix pitch alignment for non-power-of-two mipmaps on SIMarek Olšák
This fixes VM protection faults. I have a new piglit test which can iterate over all possible widths, heights, and depths (including NPOT) and tests mipmapping with various texture targets. After this is committed, I'll make a new release of libdrm and bump the libdrm version requirement in Mesa.
2013-09-18radeon: Fix tiling mode index for 1D tiled depth/stencil surfaces on CIKMichel Dänzer
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeon: add CIK chip familiesAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-15radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transitionMarek Olšák
Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-13radeon: add HAINAN familyAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-12radeon: add si tiling support v5Jerome Glisse
v2: Only writte tile index if flags for it is set v3: Remove useless allow2d scanout flags v4: Split radeon_drm.h update to its own patch v5: update against lastest next tree for radeon Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-03-07radeonsi: make sure tile_split field are not garbageJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2013-02-04radeon: add OLAND familyAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-18radeon: Fix 1D tiling layout on SI.Michel Dänzer
Very similar to Evergreen, but slightly different rules for tile / slice alignment. Fortunately, these map quite naturally onto the previous fixes for linear aligned layout on SI. 2D tiling still needs more work here and possibly in the kernel. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-10-26radeon: fix tile_split of 128-bit surface formats with 8x MSAAMarek Olšák
The calculation led to the number 8192, which is too high. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-06radeon: fix stencil miptree allocation of combined ZS buffers on EG and SIMarek Olšák
This allows texturing with depth-stencil buffers directly without the copy to CB. The separate miptree description for stencil is added, because the stencil mipmap offsets are not really depth offsets/4 (at least for the texture units). Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-06radeon: don't force stencil tile split to 0Marek Olšák
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-03radeon: don't take the stencil-specific codepath for buffers without stencilMarek Olšák
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-06radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI.Michel Dänzer
Another corner case that isn't well-explained yet. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06radeon: Memory footprint of SI mipmap base level is padded to powers of two.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-05radeon: Fix layout of linear aligned mipmaps on SI.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-24radeon: align r600 msaa buffers to a multiple of macrotile size * num samplesMarek Olšák
I am not sure whether this is needed, but better be safe than sorry.
2012-08-24radeon: fix allocation of MSAA surfaces on r600-r700Marek Olšák
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-09radeon: tweak TILE_SPLIT for MSAA surfacesMarek Olšák
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-09radeon: force 2D tiling for MSAA surfacesMarek Olšák
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-09radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EGMarek Olšák
If we don't need stencil, don't allocate it. If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth. v2: actually do it correctly Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-09radeon: simplify ZS buffer checking on r600Marek Olšák
Setting those flags has no effect anywhere else. Reviewed-by: Christian König <christian.koenig@amd.com>
2012-06-17radeon/surface: free version after using it.Dave Airlie
fixes leak in valgrind. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-12radeon: force 1D array mode for z/stencil surfaceJerome Glisse
On r6xx or evergreen z/stencil surface don't support linear or linear aligned surface, force 1D tiled mode for those. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-11radeon: enabled 2D tiling for evergreen only on fixed kernelJerome Glisse
Due to a kernel bug, enabled 2D tiling for evergreen only on newer fixed kernel. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-11radeon: always properly initialize stencil_offset fieldJerome Glisse
Reported-by: Vadim Girlin <vadimgirlin@gmail.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-07radeon: fall back to 1D tiling only with broken kernelsAlex Deucher
Certain cards report the the wrong bank setup which causes surface init to fail in the ddx and leads to no accel. If we hit an invalid tiling parameter, just set a default value and disable 2D tiling. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=43448 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-05-16radeon: Add Southern Islands PCI IDs.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-03-20radeon: add TN surface supportAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-02-13radeon: fix pitch alignment for scanout bufferJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-03radeon: fix surface API for good before anyone start relying on itJerome Glisse
The mipmap level computation was wrong, we need to know the block width, height, depth of compressed texture to properly compute this. Change API to provide block width, height, depth instead of nblk_x, nblk_y, nblk_z. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-02radeon: surface fix macro -> micro tile fallbackJerome Glisse
We need to force 1D tiling only on old kernel the fallback was broken along the way. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-01radeon: add surface allocator helper v10Jerome Glisse
The surface allocator is able to build complete miptree when allocating surface for r600/r700/evergreen/northern islands GPU family. It also compute bo size and alignment for render buffer, depth buffer and scanout buffer. v2 fix r6xx/r7xx 2D tiling width align computation v3 add tile split support and fix 1d texture alignment v4 rework to more properly support compressed format, split surface pixel size and surface element size in separate fields v5 support texture array (still issue on r6xx) v6 split surface value computation and mipmap tree building, rework eg and newer computation v7 add a check for tile split and 2d tiled v8 initialize mode value before testing it in all case, reenable 2D macro tile mode on r6xx for cubemap and array. Fix cubemap to force array size to the number of face. v9 fix handling of stencil buffer on evergreen v10 on evergreen depth buffer need to have enough room for a stencil buffer just after depth one Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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