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path: root/radeon/r600_pci_ids.h
AgeCommit message (Collapse)Author
2013-03-08radeon: add pci ids for Richland APUsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-04radeon: add OLAND pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-11-21radeon: add new SI pci idAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-10-16radeon: add some new SI pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-06radeon: add some new SI pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-06radeon: add some missing evergreen pci idsAlex Deucher
Noticed by: Harald van Dijk <fdo@gigawatt.nl> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=53124 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-06-05radeon: add new pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-05-16radeon: Add Southern Islands PCI IDs.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-05-10radeon: Add new R600 PCI ids for surface managerAnisse Astier
This is the same list of PCI ids added by Alex Deucher in xf86-video-ati commit aacbd629b02cbee3f9e6a0ee452b4e3f21376bd3. This is needed since the addition of the surface allocator helper in commit c51f7f0e460dcadb9f1a56ecf1615810877c33c8 ; it needs to differentiate pre and post-R600 GPUs. Therefore we should maintain another PCI id list. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=48138 Signed-off-by: Anisse Astier <anisse@astier.eu> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-03-20radeon: add TN surface supportAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-02-01radeon: add surface allocator helper v10Jerome Glisse
The surface allocator is able to build complete miptree when allocating surface for r600/r700/evergreen/northern islands GPU family. It also compute bo size and alignment for render buffer, depth buffer and scanout buffer. v2 fix r6xx/r7xx 2D tiling width align computation v3 add tile split support and fix 1d texture alignment v4 rework to more properly support compressed format, split surface pixel size and surface element size in separate fields v5 support texture array (still issue on r6xx) v6 split surface value computation and mipmap tree building, rework eg and newer computation v7 add a check for tile split and 2d tiled v8 initialize mode value before testing it in all case, reenable 2D macro tile mode on r6xx for cubemap and array. Fix cubemap to force array size to the number of face. v9 fix handling of stencil buffer on evergreen v10 on evergreen depth buffer need to have enough room for a stencil buffer just after depth one Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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