index : renesas/drm.git	android live master
	libdrm, cloned from git://anongit.freedesktop.org/mesa/drm	Laurent Pinchart

summaryrefslogtreecommitdiff

log msg author committer range

path: root/linux-core

Age	Commit message (Expand)	Author
2004-05-10	do some real testing and fix the DRM initialising and unloading	Dave Airlie
2004-05-09	Commit sysfs and drm PCI changes for 2.6 kernel	Dave Airlie
2004-05-03	use drm.. not dri for class...	Dave Airlie
2004-05-02	fix 2.4 build	Dave Airlie
2004-05-02	better device class support from Jon Smirls patches..	Dave Airlie
2004-04-22	Add __user annotations from kernel	Dave Airlie
2004-04-22	add sparc ffb files from kernel just to keep things in sync	Dave Airlie
2004-04-21	bug from Linux kernel list caught by checker	Dave Airlie
2004-04-21	centralise pci ids into one place and use scripts to generate files for	Dave Airlie
2004-04-18	Move Makefile.linux to Makefile.	Michel Daenzer
2004-04-12	more files for mach64	Dave Airlie
2004-04-12	Add mach64 to the trunk	Dave Airlie
2004-04-10	include highmem.h	Dave Airlie
2004-04-10	patch from Andrew Morton tree from Arjan van de Ven fixes some oopses seen	Dave Airlie
2004-04-10	align code with Linux kernel.	Dave Airlie
2004-04-10	remove unused code	Dave Airlie
2004-04-10	update from linux kernel for ia64	Dave Airlie
2004-04-08	disable PCI DMA ioctls as they are not used currently until SAVAGE_CMD_DMA	Alan Hourihane
2004-04-08	big whitespace .. this aligns all the whitespace in this file with the bk	Dave Airlie
2004-04-08	2.6 sysfs patches + stubs in drmP.h for 2.4 compatibility	Dave Airlie
2004-04-08	long dev_t patches from 2.6 tree	Dave Airlie
2004-04-08	2.6 patches for larger dev_t	Dave Airlie
2004-04-08	more 2.4 compat fns	Dave Airlie
2004-04-08	patch from Linux kernel 2.6.5	Dave Airlie
2004-04-08	patch from lk	Dave Airlie
2004-03-31	VIA module fixes:	Thomas Hellstrom
2004-03-26	Added via driver to drm/linux/Config.in Reported by: Terry Barnaby	Thomas Hellstrom
2004-03-24	Exported symbols cause compilation failure of via_mm.c on 2.4 kernels.	Thomas Hellstrom
2004-03-24	Modified linux/Kconfig to include the via drm driver.	Thomas Hellstrom
2004-03-23	Merged via-1-2-0: Altered Makefiles in drm/linux	Thomas Hellstrom
2004-03-16	Add a missing ifdef CTX to get rid of the waring in the gamma driver build.	Jon Smirl
2004-03-12	Fixes need to clean up the mess I made with the mesa merge. This code	Jon Smirl
2004-02-28	Remove extraneous code accidentally added with revision 1.86	Michel Daenzer
2004-02-28	More differentiated error codes for DRM(agp_acquire)	Michel Daenzer
2004-02-24	Use DO_MUNMAP_4_ARGS macro defined in Makefile.linux (Steve Holland).	Felix Kuehling
2004-02-22	Merged the Savage DRM driver from the savage-2-0-0-branch into the trunk.	Felix Kuehling
2004-02-21	Conditionally add definition of list_for_each_entry_safe for kernel	Felix Kuehling
2004-02-20	drm_ctx_dtor.patch Submitted by: Erdi Chen	Keith Whitwell
2004-01-11	Adapt to nopage() prototype change in Linux 2.6.1.	Michel Daenzer
2003-12-16	Don't ioremap the framebuffer area. The ioremapped area wasn't used by	Eric Anholt
2003-11-06	Return EBUSY when attempting to addmap a DRM_SHM area with a lock in it if	Eric Anholt
2003-11-05	Changes to DRM(irq_install)...... wrap dev->dma usage with __HAVE_DMA in	Alan Hourihane
2003-11-05	- Tie the DRM to a specific device: setunique no longer succeeds when given	Eric Anholt
2003-11-04	Memory layout transition:	Michel Daenzer
2003-10-24	Switch pci enumeration call to work on both 2.4 and 2.6 pci_for_each_dev is	Jon Smirl
2003-10-23	Move to "old-style" probing as documented in linux/Documentation/pci.txt.	Eric Anholt
2003-10-23	- Introduce a new ioctl, DRM_IOCTL_SET_VERSION. This ioctl allows the	Eric Anholt
2003-10-22	- Add DRM_GET_PRIV_WITH_RETURN macro. This can be used in shared code to	Eric Anholt
2003-10-19	Fix probing on 2.5+ kernels, which require that drivers have .id_table set.	Eric Anholt
2003-10-17	- Move IRQ functions from drm_dma.h to new drm_irq.h and disentangle them	Eric Anholt

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generated by cgit v1.2.3 (git 2.25.1) at 2025-01-27 07:22:52 +0000

/*
 * Copyright (C) 2006 Ben Skeggs.
 *
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

/*
 * Authors:
 *   Ben Skeggs <darktama@iinet.net.au>
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"

/* NVidia uses context objects to drive drawing operations.

   Context objects can be selected into 8 subchannels in the FIFO,
   and then used via DMA command buffers.

   A context object is referenced by a user defined handle (CARD32). The HW
   looks up graphics objects in a hash table in the instance RAM.

   An entry in the hash table consists of 2 CARD32. The first CARD32 contains
   the handle, the second one a bitfield, that contains the address of the
   object in instance RAM.

   The format of the second CARD32 seems to be:

   NV4 to NV30:

   15: 0  instance_addr >> 4
   17:16  engine (here uses 1 = graphics)
   28:24  channel id (here uses 0)
   31	  valid (use 1)

   NV40:

   15: 0  instance_addr >> 4   (maybe 19-0)
   21:20  engine (here uses 1 = graphics)
   I'm unsure about the other bits, but using 0 seems to work.

   The key into the hash table depends on the object handle and channel id and
   is given as:
*/
static uint32_t
nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle)
{
	struct drm_nouveau_private *dev_priv=dev->dev_private;
	uint32_t hash = 0;
	int i;

	DRM_DEBUG("ch%d handle=0x%08x\n", channel, handle);

	for (i=32;i>0;i-=dev_priv->ramht_bits) {
		hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
		handle >>= dev_priv->ramht_bits;
	}
	if (dev_priv->card_type < NV_50)
		hash ^= channel << (dev_priv->ramht_bits - 4);
	hash <<= 3;

	DRM_DEBUG("hash=0x%08x\n", hash);
	return hash;
}

static int
nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht,
			  uint32_t offset)
{
	struct drm_nouveau_private *dev_priv=dev->dev_private;
	uint32_t ctx = INSTANCE_RD(ramht, (offset + 4)/4);

	if (dev_priv->card_type < NV_40)
		return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0);
	return (ctx != 0);
}

static int
nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
{
	struct drm_nouveau_private *dev_priv=dev->dev_private;
	struct nouveau_channel *chan = dev_priv->fifos[ref->channel];
	struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
	struct nouveau_gpuobj *gpuobj = ref->gpuobj;
	uint32_t ctx, co, ho;

	if (!ramht) {
		DRM_ERROR("No hash table!\n");
		return -EINVAL;
	}

	if (dev_priv->card_type < NV_40) {
		ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) |
		      (ref->channel   << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |
		      (gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);
	} else
	if (dev_priv->card_type < NV_50) {
		ctx = (ref->instance >> 4) |
		      (ref->channel   << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |
		      (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
	} else {
		ctx = (ref->instance  >> 4) |
		      (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
	}

	co = ho = nouveau_ramht_hash_handle(dev, ref->channel, ref->handle);
	do {
		if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
			DRM_DEBUG("insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
				  ref->channel, co, ref->handle, ctx);
			INSTANCE_WR(ramht, (co + 0)/4, ref->handle);
			INSTANCE_WR(ramht, (co + 4)/4, ctx);

			list_add_tail(&ref->list, &chan->ramht_refs);
			return 0;
		}
		DRM_DEBUG("collision ch%d 0x%08x: h=0x%08x\n",
			  ref->channel, co, INSTANCE_RD(ramht, co/4));

		co += 8;
		if (co >= dev_priv->ramht_size) {
			DRM_INFO("no space left after collision\n");
			co = 0;
			/* exit as it seems to cause crash with nouveau_demo and
			 * 0xdead0001 object */
			break;
		}
	} while (co != ho);

	DRM_ERROR("RAMHT space exhausted. ch=%d\n", ref->channel);
	return -ENOMEM;
}

static void
nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_channel *chan = dev_priv->fifos[ref->channel];
	struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
	uint32_t co, ho;

	if (!ramht) {
		DRM_ERROR("No hash table!\n");
		return;
	}

	co = ho = nouveau_ramht_hash_handle(dev, ref->channel, ref->handle);
	do {
		if (nouveau_ramht_entry_valid(dev, ramht, co) &&
		    (ref->handle == INSTANCE_RD(ramht, (co/4)))) {
			DRM_DEBUG("remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
				  ref->channel, co, ref->handle,
				  INSTANCE_RD(ramht, (co + 4)));
			INSTANCE_WR(ramht, (co + 0)/4, 0x00000000);
			INSTANCE_WR(ramht, (co + 4)/4, 0x00000000);

			list_del(&ref->list);
			return;
		}

		co += 8;
		if (co >= dev_priv->ramht_size)
			co = 0;
	} while (co != ho);

	DRM_ERROR("RAMHT entry not found. ch=%d, handle=0x%08x\n",
		  ref->channel, ref->handle);
}

int
nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
		   int size, int align, uint32_t flags,
		   struct nouveau_gpuobj **gpuobj_ret)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;
	struct nouveau_gpuobj *gpuobj;
	struct mem_block *pramin = NULL;
	int ret;

	DRM_DEBUG("ch%d size=%d align=%d flags=0x%08x\n",
		  chan ? chan->id : -1, size, align, flags);

	if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL)
		return -EINVAL;

	gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER);
	if (!gpuobj)
		return -ENOMEM;
	DRM_DEBUG("gpuobj %p\n", gpuobj);
	gpuobj->flags = flags;
	gpuobj->im_channel = chan ? chan->id : -1;

	list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);

	/* Choose between global instmem heap, and per-channel private
	 * instmem heap.  On <NV50 allow requests for private instmem
	 * to be satisfied from global heap if no per-channel area
	 * available.
	 */
	if (chan) {
		if (chan->ramin_heap) {
			DRM_DEBUG("private heap\n");
			pramin = chan->ramin_heap;
		} else
		if (dev_priv->card_type < NV_50) {
			DRM_DEBUG("global heap fallback\n");
			pramin = dev_priv->ramin_heap;
		}
	} else {
		DRM_DEBUG("global heap\n");
		pramin = dev_priv->ramin_heap;
	}

	if (!pramin) {
		DRM_ERROR("No PRAMIN heap!\n");
		return -EINVAL;
	}

	if (!chan && (ret = engine->instmem.populate(dev, gpuobj, &size))) {
		nouveau_gpuobj_del(dev, &gpuobj);
		return ret;
	}

	/* Allocate a chunk of the PRAMIN aperture */
	gpuobj->im_pramin = nouveau_mem_alloc_block(pramin, size,
						    drm_order(align),
						    (struct drm_file *)-2);
	if (!gpuobj->im_pramin) {
		nouveau_gpuobj_del(dev, &gpuobj);
		return -ENOMEM;
	}
	gpuobj->im_pramin->flags = NOUVEAU_MEM_INSTANCE;

	if (!chan && (ret = engine->instmem.bind(dev, gpuobj))) {
		nouveau_gpuobj_del(dev, &gpuobj);
		return ret;
	}

	if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
		int i;

		for (i = 0; i < gpuobj->im_pramin->size; i += 4)
			INSTANCE_WR(gpuobj, i/4, 0);
	}

	*gpuobj_ret = gpuobj;
	return 0;
}

int
nouveau_gpuobj_early_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	DRM_DEBUG("\n");

	INIT_LIST_HEAD(&dev_priv->gpuobj_list);

	return 0;
}

int
nouveau_gpuobj_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int ret;

	DRM_DEBUG("\n");

	if (dev_priv->card_type < NV_50) {
		if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset,
						   ~0, dev_priv->ramht_size,
						   NVOBJ_FLAG_ZERO_ALLOC |
						   NVOBJ_FLAG_ALLOW_NO_REFS,
						   &dev_priv->ramht, NULL)))
			return ret;
	}

	return 0;
}

void
nouveau_gpuobj_takedown(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	DRM_DEBUG("\n");

	nouveau_gpuobj_del(dev, &dev_priv->ramht);
}

void
nouveau_gpuobj_late_takedown(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *gpuobj = NULL;
	struct list_head *entry, *tmp;

	DRM_DEBUG("\n");

	list_for_each_safe(entry, tmp, &dev_priv->gpuobj_list) {
		gpuobj = list_entry(entry, struct nouveau_gpuobj, list);

		DRM_ERROR("gpuobj %p still exists at takedown, refs=%d\n",
			  gpuobj, gpuobj->refcount);
		gpuobj->refcount = 0;
		nouveau_gpuobj_del(dev, &gpuobj);
	}
}

int
nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->Engine;
	struct nouveau_gpuobj *gpuobj;

	DRM_DEBUG("gpuobj %p\n", pgpuobj ? *pgpuobj : NULL);

	if (!dev_priv || !pgpuobj || !(*pgpuobj))
		return -EINVAL;
	gpuobj = *pgpuobj;

	if (gpuobj->refcount != 0) {
		DRM_ERROR("gpuobj refcount is %d\n", gpuobj->refcount);
		return -EINVAL;
	}

	if (gpuobj->dtor)
		gpuobj->dtor(dev, gpuobj);

	if (gpuobj->im_backing) {
		if (gpuobj->flags & NVOBJ_FLAG_FAKE)
			drm_free(gpuobj->im_backing,
				 sizeof(*gpuobj->im_backing), DRM_MEM_DRIVER);
		else
			engine->instmem.clear(dev, gpuobj);
	}

	if (gpuobj->im_pramin) {
		if (gpuobj->flags & NVOBJ_FLAG_FAKE)
			drm_free(gpuobj->im_pramin, sizeof(*gpuobj->im_pramin),
				 DRM_MEM_DRIVER);
		else
			nouveau_mem_free_block(gpuobj->im_pramin);
	}

	list_del(&gpuobj->list);

	*pgpuobj = NULL;
	drm_free(gpuobj, sizeof(*gpuobj), DRM_MEM_DRIVER);
	return 0;
}

static int
nouveau_gpuobj_instance_get(struct drm_device *dev,
			    struct nouveau_channel *chan,
			    struct nouveau_gpuobj *gpuobj, uint32_t *inst)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *cpramin;

	/* <NV50 use PRAMIN address everywhere */
	if (dev_priv->card_type < NV_50) {
		*inst = gpuobj->im_pramin->start;
		return 0;
	}

	if (chan && gpuobj->im_channel != chan->id) {
		DRM_ERROR("Channel mismatch: obj %d, ref %d\n",
			  gpuobj->im_channel, chan->id);
		return -EINVAL;
	}

	/* NV50 channel-local instance */
	if (chan > 0) {
		cpramin = chan->ramin->gpuobj;
		*inst = gpuobj->im_pramin->start - cpramin->im_pramin->start;
		return 0;
	}

	/* NV50 global (VRAM) instance */
	if (gpuobj->im_channel < 0) {
		/* ...from global heap */
		if (!gpuobj->im_backing) {
			DRM_ERROR("AII, no VRAM backing gpuobj\n");
			return -EINVAL;
		}
		*inst = gpuobj->im_backing->start;
		return 0;
	} else {
		/* ...from local heap */
		cpramin = dev_priv->fifos[gpuobj->im_channel]->ramin->gpuobj;
		*inst = cpramin->im_backing->start +
			(gpuobj->im_pramin->start - cpramin->im_pramin->start);
		return 0;
	}

	return -EINVAL;
}

int
nouveau_gpuobj_ref_add(struct drm_device *dev, struct nouveau_channel *chan,
		       uint32_t handle, struct nouveau_gpuobj *gpuobj,
		       struct nouveau_gpuobj_ref **ref_ret)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj_ref *ref;
	uint32_t instance;
	int ret;

	DRM_DEBUG("ch%d h=0x%08x gpuobj=%p\n",
		  chan ? chan->id : -1, handle, gpuobj);

	if (!dev_priv || !gpuobj || (ref_ret && *ref_ret != NULL))
		return -EINVAL;

	if (!chan && !ref_ret)
		return -EINVAL;

	ret = nouveau_gpuobj_instance_get(dev, chan, gpuobj, &instance);
	if (ret)
		return ret;

	ref = drm_calloc(1, sizeof(*ref), DRM_MEM_DRIVER);
	if (!ref)
		return -ENOMEM;
	ref->gpuobj   = gpuobj;
	ref->channel  = chan ? chan->id : -1;
	ref->instance = instance;

	if (!ref_ret) {
		ref->handle = handle;

		ret = nouveau_ramht_insert(dev, ref);
		if (ret) {
			drm_free(ref, sizeof(*ref), DRM_MEM_DRIVER);
			return ret;
		}
	} else {
		ref->handle = ~0;
		*ref_ret = ref;
	}

	ref->gpuobj->refcount++;
	return 0;
}

int nouveau_gpuobj_ref_del(struct drm_device *dev, struct nouveau_gpuobj_ref **pref)
{
	struct nouveau_gpuobj_ref *ref;

	DRM_DEBUG("ref %p\n", pref ? *pref : NULL);

	if (!dev || !pref || *pref == NULL)
		return -EINVAL;
	ref = *pref;

	if (ref->handle != ~0)
		nouveau_ramht_remove(dev, ref);

	if (ref->gpuobj) {
		ref->gpuobj->refcount--;

		if (ref->gpuobj->refcount == 0) {
			if (!(ref->gpuobj->flags & NVOBJ_FLAG_ALLOW_NO_REFS))
				nouveau_gpuobj_del(dev, &ref->gpuobj);
		}
	}

	*pref = NULL;
	drm_free(ref, sizeof(ref), DRM_MEM_DRIVER);
	return 0;
}

int
nouveau_gpuobj_new_ref(struct drm_device *dev,
		       struct nouveau_channel *oc, struct nouveau_channel *rc,
		       uint32_t handle, int size, int align, uint32_t flags,
		       struct nouveau_gpuobj_ref **ref)
{
	struct nouveau_gpuobj *gpuobj = NULL;
	int ret;

	if ((ret = nouveau_gpuobj_new(dev, oc, size, align, flags, &gpuobj)))
		return ret;

	if ((ret = nouveau_gpuobj_ref_add(dev, rc, handle, gpuobj, ref))) {
		nouveau_gpuobj_del(dev, &gpuobj);
		return ret;
	}

	return 0;
}

int
nouveau_gpuobj_ref_find(struct nouveau_channel *chan, uint32_t handle,
			struct nouveau_gpuobj_ref **ref_ret)
{
	struct nouveau_gpuobj_ref *ref;
	struct list_head *entry, *tmp;

	list_for_each_safe(entry, tmp, &chan->ramht_refs) {
		ref = list_entry(entry, struct nouveau_gpuobj_ref, list);

		if (ref->handle == handle) {
			if (ref_ret)
				*ref_ret = ref;
			return 0;
		}
	}

	return -EINVAL;
}

int
nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t p_offset,
			uint32_t b_offset, uint32_t size,
			uint32_t flags, struct nouveau_gpuobj **pgpuobj,
			struct nouveau_gpuobj_ref **pref)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *gpuobj = NULL;
	int i;

	DRM_DEBUG("p_offset=0x%08x b_offset=0x%08x size=0x%08x flags=0x%08x\n",
		  p_offset, b_offset, size, flags);

	gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER);
	if (!gpuobj)
		return -ENOMEM;
	DRM_DEBUG("gpuobj %p\n", gpuobj);
	gpuobj->im_channel = -1;
	gpuobj->flags      = flags | NVOBJ_FLAG_FAKE;

	list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);

	if (p_offset != ~0) {
		gpuobj->im_pramin = drm_calloc(1, sizeof(struct mem_block),
					       DRM_MEM_DRIVER);
		if (!gpuobj->im_pramin) {
			nouveau_gpuobj_del(dev, &gpuobj);
			return -ENOMEM;
		}
		gpuobj->im_pramin->start = p_offset;
		gpuobj->im_pramin->size  = size;
	}

	if (b_offset != ~0) {
		gpuobj->im_backing = drm_calloc(1, sizeof(struct mem_block),
					       DRM_MEM_DRIVER);
		if (!gpuobj->im_backing) {
			nouveau_gpuobj_del(dev, &gpuobj);
			return -ENOMEM;
		}
		gpuobj->im_backing->start = b_offset;
		gpuobj->im_backing->size  = size;
	}

	if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
		for (i = 0; i < gpuobj->im_pramin->size; i += 4)
			INSTANCE_WR(gpuobj, i/4, 0);
	}

	if (pref) {
		if ((i = nouveau_gpuobj_ref_add(dev, NULL, 0, gpuobj, pref))) {
			nouveau_gpuobj_del(dev, &gpuobj);
			return i;
		}
	}

	if (pgpuobj)
		*pgpuobj = gpuobj;
	return 0;
}


static int
nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/*XXX: dodgy hack for now */
	if (dev_priv->card_type >= NV_50)
		return 24;
	if (dev_priv->card_type >= NV_40)
		return 32;
	return 16;
}

/*
   DMA objects are used to reference a piece of memory in the
   framebuffer, PCI or AGP address space. Each object is 16 bytes big
   and looks as follows:

   entry[0]
   11:0  class (seems like I can always use 0 here)
   12    page table present?
   13    page entry linear?
   15:14 access: 0 rw, 1 ro, 2 wo
   17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
   31:20 dma adjust (bits 0-11 of the address)
   entry[1]
   dma limit (size of transfer)
   entry[X]
   1     0 readonly, 1 readwrite
   31:12 dma frame address of the page (bits 12-31 of the address)
   entry[N]
   page table terminator, same value as the first pte, as does nvidia
   rivatv uses 0xffffffff

   Non linear page tables need a list of frame addresses afterwards,
   the rivatv project has some info on this.

   The method below creates a DMA object in instance RAM and returns a handle
   to it that can be used to set up context objects.
*/
int
nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
		       uint64_t offset, uint64_t size, int access,
		       int target, struct nouveau_gpuobj **gpuobj)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int ret;
	uint32_t is_scatter_gather = 0;

	/* Total number of pages covered by the request.
	 */
	const unsigned int page_count = (size + PAGE_SIZE - 1) / PAGE_SIZE;


	DRM_DEBUG("ch%d class=0x%04x offset=0x%llx size=0x%llx\n",
		  chan->id, class, offset, size);
	DRM_DEBUG("access=%d target=%d\n", access, target);

	switch (target) {
        case NV_DMA_TARGET_AGP:
                 offset += dev_priv->gart_info.aper_base;
                 break;
        case NV_DMA_TARGET_PCI_NONLINEAR:
                /*assume the "offset" is a virtual memory address*/
                is_scatter_gather = 1;
                /*put back the right value*/
                target = NV_DMA_TARGET_PCI;
                break;
        default:
                break;
        }

	ret = nouveau_gpuobj_new(dev, chan,
				 is_scatter_gather ? ((page_count << 2) + 12) : nouveau_gpuobj_class_instmem_size(dev, class),
				 16,
				 NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
				 gpuobj);
	if (ret) {
		DRM_ERROR("Error creating gpuobj: %d\n", ret);
		return ret;
	}

	if (dev_priv->card_type < NV_50) {
		uint32_t frame, adjust, pte_flags = 0;
		adjust = offset &  0x00000fff;
		if (access != NV_DMA_ACCESS_RO)
				pte_flags |= (1<<1);

		if ( ! is_scatter_gather )
			{